DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of species iii, fig. 1C, claims 1-25, in the reply filed on 11/17/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 13-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nomiya, US Publication No. 2010/0224396 A1.
Nomiya teaches:
13. An electronic package, comprising (see fig. 1):
a glass core (11/12; e.g. materials at para. [0053] – [0054]);
a first trace (15) in the glass core;
a second trace (e.g. adjacent 15) in the glass core, wherein the second trace is laterally adjacent to the first trace; and
a gap (e.g. layer 13 has pores, para. [0057]) above and below the first trace and the second trace. See Nomiya at para. [0001] – [0106], figs. 1-11.
14. The electronic package of claim 13, wherein the glass core (11/12) comprises three or more glass sublayers (e.g. There are a total of 5 layers of 11/12 in fig. 1)
15. The electronic package of claim 14, wherein the first trace (15) and the second trace (e.g. adjacent 15) are in a middle glass sublayer (e.g. forming interface with middle 12) of the three or more glass sublayers, fig. 1.
16. The electronic package of claim 14, wherein a seam (e.g. interfaces formed by layers is a seam) is provided between each of the glass sublayers (11/12), fig. 1.
17. The electronic package of claim 13, wherein the gap (e.g. layer 13 has pores, para. [0057]) comprises a first non-linear surface and a second non-linear surface (e.g. pores are non-linear).
18. The electronic package of claim 13, wherein vias (17) are provided through the glass core (11/12) adjacent to the first trace (15) and the second trace (e.g. adjacent 15), fig. 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 9-11, 13-18 and 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devnani et al., US Publication No. 2003/0183919 A1 in view of Seri, JP 2005285862 A.
Devnani teaches:
1. An electronic package, comprising (see fig. 7 annotated below):
a first layer (e.g. layer below 604), wherein the first layer comprises glass (e.g. glass ceramic at para. [0021]);
a second layer (605/602/603) over the first layer, wherein the second layer comprises glass (e.g. glass ceramic at para. [0021]);
a third layer (205/202/203) over the second layer, wherein the third layer comprises glass (e.g. glass ceramic at para. [0021]);
a pair of traces (601, 600) in the second layer;… See Devnani at para. [0001] – [0034], figs. 1-13.
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Devnani does not expressly teach:
a first gap below the pair of traces, wherein the first gap is in the first layer and the second layer; and
a second gap above the pair of traces, wherein the second gap is in the second layer and the third layer.
In an analogous art, Seri at English machine translation page 3 teaches:
“However, as a method of forming a roughened surface having good adhesion on the surface of the insulating layer… A gap between the wiring conductors located above and below the insulation layer is formed…”
Thus, Seri teaches roughening the surface of an insulating layer to achieve good adhesion. The roughening results in a gap between the wiring conductors located above and below the insulation layer.
It would have been obvious to one of ordinary skill in the art to modify Devnani with Seri for form “a first gap (e.g. from roughening) below the pair of traces (601, 600), wherein the first gap is in the first layer (e.g. layer below 604) and the second layer (605/602/603); and a second gap (e.g. from roughening) above the pair of traces (601, 600), wherein the second gap is in the second layer (605/602/603) and the third layer (205/202/203)”, as recited in the claim, in order to improve adhesion on the surface of the insulating layer.
Regarding claim 2:
Seri further teaches:
2. The electronic package of claim 1, wherein the first gap and the second gap are air gaps (“A gap between the wiring conductors located above and below the insulation layer is formed…”, Seri at English machine translation page 3)
Regarding claim 5:
Devnani further teaches:
5. The electronic package of claim 1, wherein vias (707, 726, 717, 720, 721, 722, 723) are formed through the first layer (e.g. layer below 604), the second layer (605/602/603), and the third layer (205/202/203), fig. 7.
Devnani does not expressly teach wherein the vias are adjacent to the first gap and the second gap.
Seri teaches roughening the surface of an insulating layer to achieve good adhesion. The roughening results in a gap between the wiring conductors located above and below the insulation layer.
It would have been obvious to one of ordinary skill in the art to modify Devnani with Seri for form “wherein the vias (707, 726, 717, 720, 721, 722, 723) are adjacent to the first gap (e.g. from roughening) and the second gap (e.g. from roughening)”, as recited in the claim, in order to improve adhesion on the surface of the insulating layer.
Regarding claim 9:
Devnani further teaches:
9. The electronic package of claim 1, wherein a thickness of the first layer (e.g. layer below 604) and the third layer (205/202/203) is greater than a thickness of the second layer (605/602/603), fig. 7.
Regarding claim 10:
Seri further teaches:
10. The electronic package of claim 1, wherein the first gap and the second gap comprise non-planar surfaces (e.g. Seri teaches the gaps are formed by roughening so the gaps obviously have non-planar surfaces. See Seri at English machine translation page 3.)
Regarding claim 11:
Devnani further teaches the first layer, the second layer, and the third layer comprise glass ceramic at para. [0021].
Devnani does not expressly teach used silica glass or borosilicate glass.
It would have been obvious to one having ordinary skill in the art to form the first layer, the second layer, and the third layer comprise fused silica glass or borosilicate glass, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Devnani teaches:
13. An electronic package, comprising (see fig. 7 annotated above):
a glass core (e.g. layer below 604+605/602/603+205/202/203);
a first trace (601) in the glass core;
a second trace (600) in the glass core, wherein the second trace is laterally adjacent to the first trace; and… See Devnani at para. [0001] – [0034], figs. 1-13.
Devnani does not expressly teach:
a gap above and below the first trace and the second trace.
In an analogous art, Seri at English machine translation page 3 teaches:
“However, as a method of forming a roughened surface having good adhesion on the surface of the insulating layer… A gap between the wiring conductors located above and below the insulation layer is formed…”
Thus, Seri teaches roughening the surface of an insulating layer to achieve good adhesion. The roughening results in a gap between the wiring conductors located above and below the insulation layer.
It would have been obvious to one of ordinary skill in the art to modify Devnani with Seri for form “a gap (e.g. from roughening) above and below the first trace (601) and the second trace (600)”, as recited in the claim, in order to improve adhesion on the surface of the insulating layer.
Devnani further teaches:
14. The electronic package of claim 13, wherein the glass core comprises three or more glass sublayers (e.g. layer below 604+605/602/603+205/202/203), fig. 7.
15. The electronic package of claim 14, wherein the first trace (601) and the second trace (600) are in a middle glass sublayer (605/602/603) of the three or more glass sublayers (e.g. layer below 604+605/602/603+205/202/203), fig. 7.
16. The electronic package of claim 14, wherein a seam (e.g. interfaces formed by layers is a seam) is provided between each of the glass sublayers (e.g. layer below 604+605/602/603+ 205/202/203), fig. 7.
Regarding claim 17:
Seri teaches the limitations as applied to claim 10 above.
Devnani further teaches:
18. The electronic package of claim 13, wherein vias (707, 726, 717, 720, 721, 722, 723) are provided through the glass core (e.g. layer below 604+605/602/603+205/202/203) adjacent to the first trace (601) and the second trace (600), fig. 7.
Devnani teaches:
23. An electronic system, comprising (see fig. 7 annotated above):
a board (400);
an electronic package coupled to the board, wherein the electronic package comprises:
a glass core (e.g. layer below 604+605/602/603+205/202/203);
serializer/deserializer (SERDES) traces (601, 600; e.g. see SERDES at para. [0001]) in the glass core;…
a die (100) coupled to the electronic package.
Devnani does not expressly teach:
a first air gap above the SERDES traces; and
a second air gap below the SERDES traces; and
In an analogous art, Seri at English machine translation page 3 teaches:
“However, as a method of forming a roughened surface having good adhesion on the surface of the insulating layer… A gap between the wiring conductors located above and below the insulation layer is formed…”
Thus, Seri teaches roughening the surface of an insulating layer to achieve good adhesion. The roughening results in a gap between the wiring conductors located above and below the insulation layer.
It would have been obvious to one of ordinary skill in the art to modify Devnani with Seri for form “a first air gap (e.g. from roughening) above the SERDES traces (601, 600); and a second air gap (e.g. from roughening) below the SERDES traces (601, 600)”, as recited in the claim, in order to improve adhesion on the surface of the insulating layer.
Regarding claim 24:
Devnani teaches the limitations as applied to claim 14 above.
Regarding claim 25:
Devnani teaches the limitations as applied to claim 15 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Devnani with the teachings of Seri because roughening the surface of an insulating layer results in a gap between the wiring conductors located above and below the insulation layer that can help achieve good adhesion. See Seri at English machine translation page 3.
Claim(s) 3, 4, 6, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devnani in view of Seri, as applied to claims 1 and 13 above, and further in view of Kang et al., US Publication No. 2021/0118765 A1.
Regarding claims 3, 4, 19 and 20:
Devnani and Seri teach all the limitations of claims 1 and 13 above, but do not expressly teach the traces have tapered sidewalls/edges or hourglass shaped cross-sections.
In an analogous art, Kang teaches wirings may have a tapered shaped or “a well-known shape, such as an hour-glass shape, a cylindrical shape, and the like…” See Kang at para. [0028].
Regarding claim 6:
One of ordinary skill in the art modifying Devnani with Kang to form wiring with tapered sidewalls/edges or hourglass shaped cross-sections, as set forth above in claims 3-4 would form “wherein the vias have one or more misaligned edges with each other (e.g. due to tapering)”, as recited in the claim.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Devnani with Kang, because (i) An hour-glass shape is “a well-known shape” (e.g. see Kang at para. [0028]); and (ii) It is within the general skill of a worker in the art to select favorite shape (e.g. tapered shape, hour glass shape, etc.) on the basis of its suitability for the intended use as a matter of obvious design choice. See MPEP § 2144.04 Legal Precedent as Source of Supporting Rationale, IV. Changes in Size, Shape, or Sequence of Adding Ingredients. Because the criticality of the particular shape of the traces has not been presented with persuasive evidence, the shape is considered a matter of choice which a person of ordinary skill in the art would have found obvious (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); MPEP 2144.04, IV(B).
Claim(s) 7 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devnani in view of Seri, as applied to claim 1 above, and further in view of Kulkami et al., US Publication No. 2023/0102183 A1.
Regarding claim 7:
Devnani and Seri teach all the limitations of claim 1 above, but do not expressly teach:
wherein the first layer is bonded to the second layer with a hybrid bonding architecture, and wherein the second layer is bonded to the third layer with a hybrid bonding architecture.
In an analogous art, Kulkami teaches:
wherein a first layer (310) is bonded to a second layer (320) with a hybrid bonding architecture, fig. 3. See Kulkami at para. [0024].
Regarding claim 12:
Kulkami further teaches:
12. The electronic package of claim 1, wherein the first layer is bonded to the second layer with solder, and wherein the second layer is bonded to the third layer with solder (e.g. solder paste at para. [0015])
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Devnani with the teachings of Kulkami to form “wherein a first layer is bonded to a second layer with a hybrid bonding architecture, and wherein a second layer is bonded to a third layer with a hybrid bonding architecture” because hybrid bonding is an “efficient method” for bonding two substrate (e.g. Kulkami at para. [0005]); and a reduced package height can be achieved.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devnani in view of Seri, as applied to claim 1 above, and further in view of Beaulieu et al., US Patent No. 7,696,631.
Regarding claim 8: Devnani and Seri teach all the limitations of claim 1 above, but do not expressly teach:
wherein the first gap and the second gap are hermetically sealed.
In an analogous art, Beaulieu teaches forming a housing (90) attached a package substrate (80) to hermetically seal a chip (10), fig. 4, col 7, ln 30–43.
One of ordinary skill in the art modifying Devnani with Beaulieu to form a housing surrounding Devnani’s electronic package would hermetically seal the first gap and the second gap, as recited in the claim.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Devnani with the teachings of Kang because “…a hermetic seal from the ambient to prevent adverse environmental effects on the semiconductor chip 10 such as oxidation or moisture ingress.” See Kang at col 7, ln 30–43.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomiya, as applied to claim13 above, and further in view of Kang et al., US Publication No. 2021/0118765 A1.
Regarding claims 19 and 20:
Nomiya teaches all the limitations of claims 1 and 13 above, but does not expressly teach the traces have tapered sidewalls/edges or hourglass shaped cross-sections.
In an analogous art, Kang teaches wirings may have a tapered shaped or “a well-known shape, such as an hour-glass shape, a cylindrical shape, and the like…” See Kang at para. [0028].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Nomiya with Kang, because (i) An hour-glass shape is “a well-known shape” (e.g. see Kang at para. [0028]); and (ii) It is within the general skill of a worker in the art to select favorite shape (e.g. tapered shape, hour glass shape, etc.) on the basis of its suitability for the intended use as a matter of obvious design choice. See MPEP § 2144.04 Legal Precedent as Source of Supporting Rationale, IV. Changes in Size, Shape, or Sequence of Adding Ingredients. Because the criticality of the particular shape of the traces has not been presented with persuasive evidence, the shape is considered a matter of choice which a person of ordinary skill in the art would have found obvious (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); MPEP 2144.04, IV(B).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomiya, as applied to claim 13 above, and further in view of Lee et al., US Publication No. 2014/0182897 A1.
Regarding claim 21:
Nomiya teaches all the limitations of claim 13 above, but does not expressly each:
organic buildup layers above and below the glass core.
In an analogous art, Lee teaches a circuit board includes: a core substrate comprised of a glass sheet or a plate glass; and, on the core substrate, at least one build-up insulating layer formed of organic material, para. [0042] - [0043].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Devnani with the teachings of Lee to reduce warpage. See Lee at para. [0151] – [0152].
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomiya, as applied to claim13 above.
Regarding claim 22:
Nomiya teaches all the limitations of claim 13 above, but does not expressly teach
the gap has a height up to approximately 200 μm both above and below the first trace and the second trace.
However, Nomiya teaches the pore size (-i.e. gap) is a result effective variable for adjusting thermal expansion coefficient, para. [0066].
It would have been obvious to one having ordinary skill in the art to form “the gap has a height up to approximately 200 μm both above and below the first trace and the second trace”, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
26 January 2026