DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 4/8/2026, responding to the Office action mailed on 2/17/2026, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 11043499 B2) in view of Wu et al. (US 20180012963 A1) and Peng et al. (US 20210343645 A1).
Re Claim 1 Tang teaches a three-dimensional memory device (10, col 62 line 14), comprising:
an array of vertically stacked memory cells (Cell Column & Row, col 2 line 39), the array of vertically stacked memory cells (FIG. 1), comprising:
access devices (FIG. 2, col 1 line 46, “The transistor is utilized to selective access the capacitor and may be referred to as an access device.”, col 3 line 25, “…the memory cell A1 includes the transistor T…”) each respectively including:
a first source/drain region (32, col 3 line 50) and a second source/drain region (34, col 3 line 51) separated by a respective channel region (28, col 3 line 37),
storage nodes (40, col 4 line 27) electrically coupled to the second source/drain regions (34) of the access devices (FIG. 2); and
digit lines (DL1, DL2) electrically coupled to the second source/drain regions (34, col 4 line 14, “The first source/drain region 32 is electrically coupled with the digit line DL1…”, 32 and 34 are electrically coupled to each other since they are part of the same transistor, and the digit lines are therefore electrically coupled to both source/drain regions) of the access devices (FIG. 1 and FIG. 2).
Tang does not teach a semiconductor material comprising a first source/drain region and a second source/drain region separated by a respective channel region, and a respective gate opposing the respective channel region and separated therefrom by a respective gate dielectric;
a first doped dielectric material adjacent to the respective gate and the semiconductor material; and
a second doped dielectric material adjacent to the gate and the semiconductor material, wherein the second doped dielectric material is opposite to the first doped dielectric material relative to the respective gate.
Wu teaches a semiconductor material (102) [0018-0019] comprising a first source/drain region and a second source/drain region separated by a respective channel region ([0019] “The fin structure 102 may include a source region, a drain region and a channel region (not shown). The source region and the drain region are separated by the channel region…”), and a respective gate (103) [0019] opposing the respective channel region (part of 102) and separated therefrom by a respective gate dielectric (104) [0022];
a first doped dielectric material (105a on left, FIG. 5J) adjacent to the gate (103) and the respective semiconductor material (102); and
a second doped dielectric material (105a on right, FIG. 5J) adjacent to the gate (103) and the respective semiconductor material (102), wherein the second doped dielectric material (105a on right) is opposite to the first doped dielectric material (105a on left) relative to the respective gate (103, FIG. 5J).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wu into the structure of Tang since Wu teaches a planar MOSFET semiconductor device with doped dielectric materials integrated around the gate.
The ordinary artisan would have been motivated to modify Wu in combination with Tang in the above manner for optimally integrating a gate and surrounding layers to a transistor and prevent shorting between the gates of adjacent transistors. [0004] states, “However, according to conventional fabrication techniques, it is very likely that the gate structures of FinFETs would get in direct contact with one another as the size of ICs get smaller. Accordingly, what is needed are FinFET structures that can prevent the shorting of adjacent metal gates.”
Tang in view of Wu does not teach the first doped dielectric material is above and below the first source/drain region, and the second doped dielectric material is above and below the second source/drain region.
Peng teaches the first dielectric material (112 [0022] and 172 [0033], both contain silicon nitride) is above and below the first source/drain region (150 on left, FIG. 16C, [0066]), and the second dielectric material (112 and 172 on right, FIG. 16C) is above and below the second source/drain region (150 on right).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Peng into the structure of Tang in view of Wu since Peng teaches a semiconductor device with dielectric materials integrated around the gate.
The ordinary artisan would have been motivated to modify Peng in combination with Tang in view of Wu in the above manner for optimally integrating dielectric layers above and below the source/drain regions to allow for the device to be as small as possible as the industry demands smaller devices. [0002] states, “The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation.”
Re Claim 2 Tang in view of Wu and Peng teaches the three-dimensional memory device of claim 1, wherein the first doped dielectric material (Wu, 105a on left in FIG. 5J) is an n-type material ([0024] states, “105a may be silicon oxide sidewalls doped with group III or group V elements…” Group V are N-type doping elements).
Re Claim 3 Tang in view of Wu and Peng teaches the three-dimensional memory device of claim 1, wherein the first doped dielectric material (Wu, 105a on left in FIG. 5J) is a p-type material ([0024] states, “105a may be silicon oxide sidewalls doped with group III or group V elements…” Group III are P-type doping elements).
Re Claim 4 Tang in view of Wu and Peng teaches the three-dimensional memory device of claim 2, wherein the second doped dielectric material (Wu, 105a on right in FIG. 5J) is an n-type material ([0024] states, “105a may be silicon oxide sidewalls doped with group III or group V elements…” Group V are N-type doping elements).
Re Claim 5 Tang in view of Wu and Peng teaches the three-dimensional memory device of claim 3, wherein the second doped dielectric material (Wu, 105a on right in FIG. 5J) is a p-type material ([0024] states, “105a may be silicon oxide sidewalls doped with group III or group V elements…” Group III are P-type doping elements).
Re Claim 8 Tang in view of Wu and Peng teaches the three-dimensional memory device of claim 1, wherein the semiconductor material (Wu, 102) comprises a crystalline silicon material ([0019] states, “The fin structure 102 … may be formed of the same material as the substrate 101.” [0018] states, “The substrate 101 may be a bulk silicon substrate, epitaxial silicon substrate…” Epitaxial silicon is crystalline silicon.).
Re Claim 9 Tang in view of Wu and Peng teaches the three-dimensional memory device of claim 1, wherein the semiconductor material (Wu, 102) comprises an undoped silicon material ([0019] states, “The fin structure 102 … may be formed of the same material as the substrate 101.” [0018] states, “The substrate 101 may be a bulk silicon substrate, epitaxial silicon substrate…” Epitaxial silicon is undoped silicon.).
Claims 6-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 11043499 B2) in view of Wu et al. (US 20180012963 A1) and Peng et al. (US 20210343645 A1) as applied to claim 1 above, and further in view of He (US 20240014305 A1).
Re Claim 6 Tang in view of Wu and Peng teaches the three-dimensional memory device of claim 1, but does not teach the first doped dielectric material is self-aligned to the respective gate.
He teaches the first doped dielectric material (302G) [0092] is self-aligned to the respective gate (306G, [0092], “The thickness of the conductive layer 306G can be the same as that of the thicknesses of the doped nitride-based semiconductor layers 302G and 304G.” The top and bottom surfaces are aligned as shown in FIG. 9).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by He into the structure of Tang in view of Wu since He teaches a semiconductor device with doped dielectric materials integrated around the device’s gate layer.
The ordinary artisan would have been motivated to modify He in combination with Tang in view of Wu in the above manner for the motivation of aligning the doped dielectric materials with the gate layer to help the device function at a peak level and satisfy demands for high power and frequency values. [0002] states, “III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.”
Re Claim 7 Tang in view of Wu and Peng and He teaches the three-dimensional memory device of claim 1, wherein the second doped dielectric material (He, 304G) [0092] is self-aligned to the respective gate (306G, [0092], “The thickness of the conductive layer 306G can be the same as that of the thicknesses of the doped nitride-based semiconductor layers 302G and 304G.” The top and bottom surfaces are aligned as shown in FIG. 9).
Re Claim 10 Tang in view of Wu and Peng and He teaches the three-dimensional memory device of claim 1, wherein the first doped dielectric (He, 302G) material and the second doped dielectric material (304G) are a nitride material [0092].
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/9/26
Prosecution Insights