DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I/Group I in the reply filed on 10/27/2025 is acknowledged. The traversal is on the grounds that the invention groups do not cause a serious burden. This is not found persuasive because in the instant case the product as claimed can be made by another and materially different process. Case in point, the device as claimed can be made via a method of manufacturing with differing temporal ordering.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
• the inventions have acquired a separate status in the art in view of their different classification
• the inventions have acquired a separate status in the art due to their recognized divergent subject matter
• the inventions require a different field of search (e.g., searching different classes /subclasses or electronic resources, or employing different search strategies or search queries)
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-10 are examined in this office action. Claims 11-20 are withdrawn from further consideration.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/16/2022 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 11043499 B2) in view of Wu (US 20180012963 A1).
Re Claim 1 Tang teaches a three-dimensional memory device (10, col 62 line 14), comprising:
an array of vertically stacked memory cells (Cell Column & Row, col 2 line 39), the array of vertically stacked memory cells (FIG. 1), comprising:
access devices (FIG. 2, col 1 line 46, “The transistor is utilized to selective access the capacitor and may be referred to as an access device.”, col 3 line 25, “…the memory cell A1 includes the transistor T…”) each respectively including:
a first source/drain region (32, col 3 line 50) and a second source/drain region (34, col 3 line 51) separated by a respective channel region (28, col 3 line 37),
storage nodes (40, col 4 line 27) electrically coupled to the respective second source/drain regions (34) of the access devices (FIG. 2); and
digit lines (DL1, DL2) electrically coupled to the second source/drain regions (34, col 4 line 14, “The first source/drain region 32 is electrically coupled with the digit line DL1…”, 32 and 34 are electrically coupled to each other since they are part of the same transistor, and the digit lines are therefore electrically coupled to both source/drain regions) of the access devices (FIG. 1 and FIG. 2).
Tang does not teach a semiconductor material comprising a first source/drain region and a second source/drain region separated by a respective channel region, and a respective gate opposing the respective channel region and separated therefrom by a respective gate dielectric;
a respective first doped dielectric material adjacent to the respective gate and the respective semiconductor material; and
a respective second doped dielectric material adjacent to the respective gate and the respective semiconductor material, wherein the respective second doped dielectric material is opposite to the respective first doped dielectric material relative to the respective gate.
Wu teaches a semiconductor material (102) [0018-0019] comprising a first source/drain region and a second source/drain region separated by a respective channel region ([0019] “The fin structure 102 may include a source region, a drain region and a channel region (not shown). The source region and the drain region are separated by the channel region…”), and a respective gate (103) [0019] opposing the respective channel region (part of 102) and separated therefrom by a respective gate dielectric (104) [0022];
a respective first doped dielectric material (105a on left, FIG. 5J) adjacent to the respective gate (103) and the respective semiconductor material (102); and
a respective second doped dielectric material (105a on right, FIG. 5J) adjacent to the respective gate (103) and the respective semiconductor material (102), wherein the respective second doped dielectric material (105a on right) is opposite to the respective first doped dielectric material (105a on left) relative to the respective gate (103, FIG. 5J).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wu into the structure of Tang since Wu teaches a planar MOSFET semiconductor device with doped dielectric materials integrated around the gate.
The ordinary artisan would have been motivated to modify Wu in combination with Tang in the above manner for optimally integrating a gate and surrounding layers to a transistor and prevent shorting between the gates of adjacent transistors. [0004] states, “However, according to conventional fabrication techniques, it is very likely that the gate structures of FinFETs would get in direct contact with one another as the size of ICs get smaller. Accordingly, what is needed are FinFET structures that can prevent the shorting of adjacent metal gates.”
Re Claim 2 Tang in view of Wu teaches the three-dimensional memory device of claim 1, wherein the respective first doped dielectric material (105a on left in FIG. 5J) is an n-type material ([0024] states, “105a may be silicon oxide sidewalls doped with group III or group V elements…” Group V are N-type doping elements).
Re Claim 3 Tang in view of Wu teaches the three-dimensional memory device of claim 1, wherein the respective first doped dielectric material (105a on left in FIG. 5J) is a p-type material ([0024] states, “105a may be silicon oxide sidewalls doped with group III or group V elements…” Group III are P-type doping elements).
Re Claim 4 Tang in view of Wu teaches the three-dimensional memory device of claim 2, wherein the respective second doped dielectric material (105a on right in FIG. 5J) is an n-type material ([0024] states, “105a may be silicon oxide sidewalls doped with group III or group V elements…” Group V are N-type doping elements).
Re Claim 5 Tang in view of Wu teaches the three-dimensional memory device of claim 3, wherein the respective second doped dielectric material (105a on right in FIG. 5J) is a p-type material ([0024] states, “105a may be silicon oxide sidewalls doped with group III or group V elements…” Group III are P-type doping elements).
Re Claim 8 Tang in view of Wu teaches the three-dimensional memory device of claim 1, wherein the respective semiconductor material (Wu, 102) comprises a crystalline silicon material ([0019] states, “The fin structure 102 … may be formed of the same material as the substrate 101.” [0018] states, “The substrate 101 may be a bulk silicon substrate, epitaxial silicon substrate…” Epitaxial silicon is crystalline silicon.).
Re Claim 9 Tang in view of Wu teaches the three-dimensional memory device of claim 1, wherein the respective semiconductor material (Wu, 102) comprises an undoped silicon material ([0019] states, “The fin structure 102 … may be formed of the same material as the substrate 101.” [0018] states, “The substrate 101 may be a bulk silicon substrate, epitaxial silicon substrate…” Epitaxial silicon is undoped silicon.).
Claims 6-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 11043499 B2) in view of Wu (US 20180012963 A1) and further in view of He (US 20240014305 A1).
Re Claim 6 Tang in view of Wu teaches the three-dimensional memory device of claim 1, but does not teach the respective first doped dielectric material is self-aligned to the respective gate.
He teaches the respective first doped dielectric material (302G) [0092] is self-aligned to the respective gate (306G, [0092], “The thickness of the conductive layer 306G can be the same as that of the thicknesses of the doped nitride-based semiconductor layers 302G and 304G.” The top and bottom surfaces are aligned as shown in FIG. 9).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by He into the structure of Tang in view of Wu since He teaches a semiconductor device with doped dielectric materials integrated around the device’s gate layer.
The ordinary artisan would have been motivated to modify He in combination with Tang in view of Wu in the above manner for the motivation of aligning the doped dielectric materials with the gate layer to help the device function at a peak level and satisfy demands for high power and frequency values. [0002] states, “III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.”
Re Claim 7 Tang in view of Wu and He teaches the three-dimensional memory device of claim 1, wherein the respective second doped dielectric material (He, 304G) [0092] is self-aligned to the respective gate (306G, [0092], “The thickness of the conductive layer 306G can be the same as that of the thicknesses of the doped nitride-based semiconductor layers 302G and 304G.” The top and bottom surfaces are aligned as shown in FIG. 9).
Re Claim 10 Tang in view of Wu and He teaches the three-dimensional memory device of claim 1, wherein the respective first doped dielectric (He, 302G) material and the respective second doped dielectric material (304G) are a nitride material [0092].
Conclusion
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/12/26