DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group I on December 11, 2025 and the election without traverse of Species B corresponding to claims 1, 3-16, and 19-20 in the reply filed on January 14, 2026 are acknowledged. As the election was made without traverse, the requirement is deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-9, 11-16, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20220384308A1 (“Lee”) in view of US20230062136A1 (“Wang”).
RE: Claim 1, Lee discloses A device (1g in FIG. 11A) comprising:
a bridge substrate (2 which includes 20, 25, 26, 27, 28, 29, [0059]; 2 is configured for signal transmission between 61 and 63, [0085]-[0087]); and
a redistribution layer (52) on a top surface of the bridge substrate.
Lee does not explicitly disclose the bridge substrate 2 comprises:
a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each trench of the plurality of trenches comprises a conductive filling;
a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer;
a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer; and
a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the conductive fillings of the plurality of trenches.
However, Lee discloses 25 is a deep trench capacitor, [0059].
In the same field of endeavor, Wang discloses deep trench capacitor structures 100 (FIG. 1E, FIG. 4F) comprising:
a plurality of trenches (In FIG. 1E: trenches in 92 are occupied or defined by 105; the term “trenches” is not defined in the instant specification and under a broad reasonable interpretation, is considered to mean holes or spaces that are occupied or not occupied by element(s)) extending vertically into a substrate (92) from a surface of the substrate (FIG. 1E shows trenches in 92 are adjacent to and extend from a top surface of 92, and the top surface of 92 is adjacent to layer 101), wherein each trench of the plurality of trenches comprises a conductive filling (105).
a conductive layer (103 or 101) partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer (102 or 104).
Wang further discloses more than one capacitor structure may be coupled together in parallel or series in the semiconductor package, depending on the application, [0046].
Wang further discloses several capacitor structures may be used to provide a very low impedance path, [0070].
FIG. 4D-4F show multiple capacitors 100 within the same substrate 90B.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the deep trench capacitor 25 in FIG. 11A of Lee so that it includes multiple deep trench capacitors as taught by Wang in order to provide a very low impedance path between electronic components 61, 62 as further taught by Wang.
Lee further discloses that in FIG. 9, the orientation of electronic component 2, the first redistribution structure 4, and the second redistribution structure 5d is disposed upside down relative to that shown in FIG. 6, [0078].
FIG. 11A shows the same orientation of electronic component 2, the first redistribution structure 4, and the second redistribution structure 5 as shown in FIG. 6.
FIG. 11A shows the deep trench capacitor 25 adjacent to the top surface of 2.
FIG. 9 shows the component 2 flipped upside down relative to the component 2 in FIG. 11A, with the deep trench capacitor 25 adjacent to the bottom surface of 20.
Accordingly, there was a need to determine at least the orientation of the electronic component 2, the first redistribution structure 4, and the second redistribution structure 5 before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the orientation of the electronic component 2, the first redistribution structure 4, and the second redistribution structure 5 shown in FIG. 9 of Lee since this would have been obvious to try as this is one solution for the orientation of the electronic component 2, the first redistribution structure 4, and the second redistribution structure 5 identified by Lee and this would have had a reasonable expectation of success, see MPEP 2143.
As a result, the electronic component 2 would be flipped upside down as shown in FIG. 9 of Lee, and Lee as modified by Wang discloses (using FIG. 9 of Lee as reference since this figure shows the relevant elements flipped upside down):
a plurality of trenches (In FIG. 9 Lee: trenches in 20 would be defined by Wang’s electrode 105 as shown in FIG. 1E of Wang) extending vertically into the bridge substrate from a bottom surface (In FIG. 9 Lee: bottom surface of 20 which would be adjacent to Wang’s electrode 101 as shown in FIG. 1E of Wang; As 2 in FIG. 9 is flipped upside down relative to FIG. 11A, the trenches would extend from the bottom surface of 20 in FIG. 9 Lee) of the bridge substrate, wherein each trench of the plurality of trenches comprises a conductive filling (Wang’s electrode 105 as shown in FIG. 1E of Wang);
a conductive layer (Wang’s electrode 103 or 101 as shown in FIG. 1E of Wang) partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer (Wang’s 102 or 104 as shown in FIG. 1E of Wang);
a plurality of first contact pads (In FIG. 9 Lee: first 28 and second 28 from left; In FIG. 9 of Lee, 25 is coupled to 61, 62 through 28; Accordingly as modified, Wang’s capacitors 100 would be coupled to 61, 62 through 28) under the bottom surface of the bridge substrate and coupled to the conductive layer (As 25 is coupled to 28 in FIG. 9 Lee, the first 28 and second 28 would be coupled to Wang’s electrode 103 or 101); and
a plurality of second contact pads (In FIG. 9 Lee: third 28 and fourth 28 from left; And optionally: Wang’s 106 which are in direct contact with Wang’s 105 as shown in FIG. 1E of Wang) under the bottom surface of the bridge substrate and coupled to the conductive fillings of the plurality of trenches (As 25 is coupled to 28 in FIG. 9 Lee, the third and fourth 28, and 106 would be coupled to Wang’s 105 / trenches in Lee’s 20);
a redistribution layer (In FIG. 9 of Lee: 42) on a top surface of the bridge substrate.
RE: Claim 3, Lee in view of Wang discloses The device of claim 1, wherein the plurality of trenches extends vertically through the bridge substrate (As modified, the trenches in 20 extend vertically at least partially through 20).
RE: Claim 4, Lee in view of Wang discloses The device of claim 1, wherein the conductive layer further extends along the bottom surface of the bridge substrate and extends between the plurality of trenches (As modified, the bottom surface of 20 in Lee corresponds to the surface of 20 adjacent to Wang’s 101; Accordingly, Wang’s electrode 101 would extend along the bottom surface of 20; In FIG. 1E of Wang, 101 extends between trenches in 92; Accordingly, Lee as modified with multiple capacitors from Wang, 101 would extend between trenches in 20), and wherein the dielectric layer further extends along the conductive layer and extends between the plurality of trenches (In FIG. 1E of Wang, 102 extends along 101 and between trenches in 92; Accordingly, in Lee as modified by Wang, 102 would extend along Wang’s 101 and between trenches in 20).
RE: Claim 5, Lee in view of Wang discloses The device of claim 1, wherein the dielectric layer comprises a high-k material having a relative permittivity of 20-15000 (In Lee, DL1, DL2 are patterned to form 102, 104, [0016]; Lee discloses DL1, DL2 are made of the high dielectric constant (k) material hafnium oxide, zirconium oxide, tantalum oxide [0015]; the reference US20070132040 discloses hafnium oxide (HfO.sub.2) or zirconium oxide (ZrO.sub.2) have a relative permittivity of about 22, tantalum oxide (Ta.sub.2O.sub.5) has a relative permittivity of about 25, [0089]; Accordingly, as modified, Lee’s 102, 104 have a relative permittivity of 22 or 25).
RE: Claim 6, Lee in view of Wang discloses The device of claim 1, wherein the plurality of first contact pads and the plurality of second contact pads lie in a same plane under the bottom surface of the bridge substrate (In FIG. 9 of Lee, each 28 lies in a plane under the bottom surface of 20; Accordingly in Lee modified by Wang, each 28 would lie in a plane under the bottom surface of 20).
RE: Claim 7, Lee in view of Wang discloses The device of claim 1, wherein the conductive layer, the dielectric layer and the conductive fillings of the plurality of trenches form an array of capacitors (As modified, Wang’s electrodes 101, 103, 105 and dielectrics 102,104 would form an array of capacitors in Lee’s 20; see the array of capacitors 100 in FIG. 4F of Wang).
RE: Claim 8, Lee in view of Wang discloses The device of claim 1, wherein the conductive layer is coupled to a reference voltage (Lee discloses The first electronic component 2 is configured for signal transmission between the second electronic component 61 and the third electronic component 63, [0087]; Accordingly, an electrical signal which carries a voltage would be coupled to 25 and therefore Wang’s conductive layer 101; Note the term “reference voltage” is an intended use of the structure which uses the voltage as a reference; it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987), see MPEP 2114 II).
RE: Claim 9, Lee in view of Wang discloses The device of claim 1, wherein the plurality of trenches is coupled to a power supply voltage (Lee discloses The first electronic component 2 is configured for signal transmission between the second electronic component 61 and the third electronic component 63, [0087]; Accordingly, an electrical signal which carries a voltage would be coupled to 25 and therefore trenches in Lee’s 20; Note the term “power supply voltage” is an intended use of the structure which uses a voltage as a power supply voltage; it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987), see MPEP 2114 II).
RE: Claim 11, Lee in view of Wang discloses The device of claim 1, wherein the conductive layer and the plurality of trenches are coupled to the redistribution layer (As modified, Wang’s 101 and the trenches in Lee’s 20 would be coupled to 42 as shown in the orientation of FIG. 9 of Lee).
RE: Claim 12, Lee in view of Wang discloses The device of claim 1, further comprising a package substrate (In the orientation of FIG. 9 Lee: 12, 14, 41, and/or 51, [0066]-[0067]), wherein the bridge substrate and the redistribution layer are at least partially embedded in the package substrate (In Lee FIG. 11A, 2, 42, 52 are at least partially embedded in 12, 14, 41, 51).
RE: Claim 13, Lee in view of Wang discloses The device of claim 12, wherein the conductive layer and the plurality of trenches are coupled to the package substrate through the plurality of first contact pads and the plurality of second contact pads, respectively (As shown in the orientation of FIG. 9 Lee, 2 is coupled to 51 by each 28; Accordingly as modified, Wang’s 101 and the trenches in Lee’s 20 would be coupled to 51 by each separate 28; Further, the trenches defined by Wang’s 105 are in direct contact with Wang’s 106 as shown in Wang FIG. 1E; Accordingly, the trenches in Lee’s 20 would be coupled to 51 by each of Wang’s 106 separately).
RE: Claim 14, Lee in view of Wang discloses The device of claim 12, further comprising a first die (61 in FIG. 11A Lee; 61 and 62 are semiconductor dice, [0085]-[0087]) and a second die (62 in FIG. 11A Lee) on the package substrate (In FIG. 11A of Lee as modified, 61 and 62 would be on 12, 14, 41, 51), wherein the bridge substrate and the redistribution layer form an embedded multi-die interconnect bridge (As modified, 2 and 4 form an embedded multi-die interconnect bridge for signal transmission between the two die 61, 62), and wherein the first die and the second die are coupled through the redistribution layer (As modified, 61 and 62 would be coupled through 4 which would have the orientation of 4 in FIG. 9 of Lee).
RE: Claim 15, Lee in view of Wang discloses The device of claim 14, wherein the conductive layer is coupled to the first die and the second die through the plurality of first contact pads (In the orientation of FIG. 9 Lee, 25 would be coupled to 61, 62 through 28; Accordingly as modified, Wang’s 101 would be coupled to 61, 62 through 28), and wherein each of the plurality of trenches is coupled to at least one of the first die or the second die through a respective one of the plurality of second contact pads (As modified, trenches in Lee’s 20 would be coupled to at least 61 or 62 through a respective one of Wang’s 106 directly in contact with 105 as shown in FIG. 1E of Wang).
RE: Claim 16, Lee in view of Wang discloses The device of claim 14, wherein the conductive layer and each of the plurality of trenches are coupled to at least one of the first die or the second die through the redistribution layer (As modified, Wang’s 101 and each trench in Lee’s 20 would be coupled to at least one of 61 or 62 through 4).
RE: Claim 19, Lee discloses A semiconductor package (1g in FIG. 11A) comprising:
a package substrate (12, 14, 41, and/or 51, [0066]-[0067]);
a bridge (2, 42, 52; 2 includes 20, 25, 26, 27, 28, 29, [0059]) at least partially embedded in the package substrate (In FIG. 11A, 2, 42, and 52 are at least partially embedded in 12, 14, 41, 51), the bridge comprising a bridge substrate (2) and a redistribution layer (52) on a top surface of the bridge substrate; and
a first die (61; 61 and 62 are semiconductor dice, [0085]-[0087]) and a second die (62) on the package substrate.
Lee does not explicitly disclose wherein the bridge substrate comprises:
a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each trench of the plurality of trenches comprises a conductive filling;
a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer; and
a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer, and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the plurality of trenches; and
wherein the first die and the second die are coupled to the conductive layer through the plurality of first contact pads;
wherein the first die is coupled to at least a respective one of the plurality of trenches through a corresponding one of the plurality of second contact pads;
wherein the second die is coupled to at least an other respective one of the plurality of trenches through an other corresponding one of the plurality of second contact pads.
However, Lee discloses 25 is a deep trench capacitor, [0059].
In the same field of endeavor, Wang discloses deep trench capacitor structures 100 (FIG. 1E, FIG. 4F) comprising:
a plurality of trenches (In FIG. 1E: trenches in 92 are occupied or defined by 105; the term “trenches” is not defined in the instant specification and under a broad reasonable interpretation, is considered to mean holes or spaces that are occupied or not occupied by element(s)) extending vertically into a substrate (92) from a surface of the substrate (FIG. 1E shows trenches in 92 are adjacent to and extend from a top surface of 92, and the top surface of 92 is adjacent to layer 101), wherein each trench of the plurality of trenches comprises a conductive filling (105).
a conductive layer (103 or 101) partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer (102 or 104).
Wang further discloses more than one capacitor structure may be coupled together in parallel or series in the semiconductor package, depending on the application, [0046].
Wang further discloses several capacitor structures may be used to provide a very low impedance path, [0070].
FIG. 4D-4F show multiple capacitors 100 within the same substrate 90B.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the deep trench capacitor 25 in FIG. 11A of Lee so that it includes multiple deep trench capacitors as taught by Wang in order to provide a very low impedance path between electronic components 61, 62 as further taught by Wang.
Lee further discloses that in FIG. 9, the orientation of electronic component 2, the first redistribution structure 4, and the second redistribution structure 5d is disposed upside down relative to that shown in FIG. 6, [0078].
FIG. 11A shows the same orientation of electronic component 2, the first redistribution structure 4, and the second redistribution structure 5 as shown in FIG. 6.
FIG. 11A shows the deep trench capacitor 25 adjacent to the top surface of 2.
FIG. 9 shows the component 2 flipped upside down relative to the component 2 in FIG. 11A, with the deep trench capacitor 25 adjacent to the bottom surface of 20.
Accordingly, there was a need to determine at least the orientation of the electronic component 2, the first redistribution structure 4, and the second redistribution structure 5 before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the orientation of the electronic component 2, the first redistribution structure 4, and the second redistribution structure 5 shown in FIG. 9 of Lee since this would have been obvious to try as this is one solution for the orientation of the electronic component 2, the first redistribution structure 4, and the second redistribution structure 5 identified by Lee and this would have had a reasonable expectation of success, see MPEP 2143. As a result, the electronic component 2 would be flipped upside down as shown in FIG. 9 of Lee, and Lee as modified by Wang discloses (using FIG. 9 of Lee as reference since this figure shows the relevant elements flipped upside down):
wherein the bridge substrate comprises:
a plurality of trenches (In FIG. 9 Lee: trenches in 20 would be defined by Wang’s electrode 105 as shown in FIG. 1E of Wang) extending vertically into the bridge substrate from a bottom surface (In FIG. 9 Lee: bottom surface of 20 which would be adjacent to Wang’s electrode 101 as shown in FIG. 1E of Wang; As 2 in FIG. 9 is flipped upside down relative to FIG. 11A, the trenches would extend from the bottom surface of 20 in FIG. 9 Lee) of the bridge substrate, wherein each trench of the plurality of trenches comprises a conductive filling (Wang’s electrode 105 as shown in FIG. 1E of Wang);
a conductive layer (Wang’s electrode 103 or 101 as shown in FIG. 1E of Wang) partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer (Wang’s 102 or 104 as shown in FIG. 1E of Wang); and
a plurality of first contact pads (In FIG. 9 Lee: first 28 and second 28 from left) under the bottom surface of the bridge substrate and coupled to the conductive layer (As 25 is coupled to 28 in FIG. 9 Lee, the first 28 and second 28 would be coupled to Wang’s electrode 103 or 101), and a plurality of second contact pads (In FIG. 9 Lee: third 28 and fourth 28 from left; And also: Wang’s 106 which are in direct contact with Wang’s 105 as shown in FIG. 1E of Wang) under the bottom surface of the bridge substrate and coupled to the plurality of trenches (As 25 is coupled to 28 in FIG. 9 Lee, the third and fourth 28, and 106 would be coupled to Wang’s 105 / trenches in Lee’s 20); and
wherein the first die and the second die are coupled to the conductive layer through the plurality of first contact pads (In FIG. 9 of Lee, 61, 62 are coupled to 25 through 28; Accordingly as modified, 61 and 62 would be coupled to Wang’s 101, 103 through 28);
wherein the first die is coupled to at least a respective one of the plurality of trenches through a corresponding one of the plurality of second contact pads (As modified, 61 would be coupled to a respective trench in Lee’s 20 through a corresponding one of Wang’s 106 directly in contact with 105 as shown in FIG. 1E of Wang);
wherein the second die is coupled to at least an other respective one of the plurality of trenches through an other corresponding one of the plurality of second contact pads (As modified, 62 would be coupled to another respective trench in Lee’s 20 through an other corresponding one of Wang’s 106 directly in contact with 105 as shown in FIG. 1E of Wang since there are multiple trenches and multiple 106).
Further, as modified, the bridge would comprise the bridge substrate (2) and a redistribution layer (42 in the orientation of FIG. 9 Lee) on a top surface of the bridge substrate.
RE: Claim 20, Lee in view of Wang discloses The semiconductor package of claim 19, wherein the first die and the second die overlie both the package substrate and the bridge (In FIG. 11A Lee: 61, 62 overlie both 2 and 12, 14, 41, and 51; this would remain unchanged in the orientation of FIG. 9 of Lee).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Wang as applied to claim 1 above, and further in view of US20090290282 A1 (“Knickerbocker”).
RE: Claim 10, Lee in view of Wang does not explicitly disclose The device of claim 1, wherein the plurality of trenches comprises a first group and a second group, wherein the first group of trenches is coupled to a first power supply voltage, and
wherein the second group of trenches is coupled to a second power supply voltage different from the first power supply voltage.
However, Lee discloses the deep trench capacitor is a decoupling capacitor, [0056].
In the same field of endeavor, Knickerbocker discloses a plurality of decoupling capacitors being segmented to support different voltages on the semiconductor chip, [0004] and supplying a specified voltage to the electronic components using corresponding decoupling capacitors, [0006].
Knickerbocker further discloses package 30 includes etched trenches of decoupling capacitors 50, [0013].
Knickerbocker further discloses The decoupling capacitor's 50 voltages are delivered using voltage planes 46 (shown in FIG. 2) and electrical connections (not shown), for example, wiring and/or vias 28, [0013].
Knickerbocker further discloses vias or TSV's 28 may also provide signal transmission, as well as, power or ground connections, [0013].
Knickerbocker further discloses It would therefore be desirable to provide or supplement a particular voltage within a 3D chip stack or package and maintain a low inductance capacitor locally and help control the voltage variations within a chip, 3D chip stack or for multiple chips in a package, [0003].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to segment the deep trench capacitors as taught by Knickerbocker in order to support a larger variety of different power voltages in the same package locally and therefore maintain a low inductance path.
In Wang FIG. 4F, each capacitor 100 is shown to have two trenches defined by electrode 105. Accordingly, Lee as modified by Wang with multiple capacitors 100 coupled to different power voltages, there would be at least three groups of trenches coupled to different power voltages. Note the term “power supply voltage” is an intended use of the structure which uses a power voltage as a power supply voltage; it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987), see MPEP 2114 II.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899