DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 7/28/25, responding to the Office action mailed on 5/14/25,
has been entered into the record. The present Office action is made with all the suggested
amendments being fully considered. Accordingly, claims 1-8 are pending in this application.
Specification
The amended title was appropriately updated after it was objected to in the Non-final Office Action 5/14/2025.
Claim Objections
Claim 1 was objected to for misspelling the word “gate”, and claim 1 was appropriately amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20170357113 A1) in view of Hosaka (US 10692994 B2).
Re Claim 1 Yamazaki teaches a transistor comprising:
a first gate electrode (111 or 114) [0312];
a second gate electrode (114 or 111, whichever the first gate electrode is NOT) opposed to the first gate electrode;
an oxide semiconductor layer (112) [0280] disposed between the first gate electrode and the second gate electrode; and
a source electrode (113a) [0280] and a drain electrode (113b) each connected to the oxide semiconductor layer, wherein
the oxide semiconductor layer includes a channel forming region([0306] states, “A region of the semiconductor layer 112 that overlaps with the conductive layer 111 corresponds to a channel formation region.”), a source region (113a & 112 overlap region), and a drain region (113b & 112 overlap region, FIG. 24A), and
the first gate electrode and the second gate electrode have different lengths (FIG. 24A).
Yamazaki does not teach a light irradiation region which is made low- resistance between the channel forming region and the source region and between the channel forming region and the drain region,
the light irradiation region includes a first region between the channel forming region and the source region and a second region between the channel forming region and the drain region,
the first region and the second region are overlapped with one of the first gate electrode and the second gate electrode, but not overlapped with the other of the first gate electrode and the second gate electrode, and
the first region and the second region have lower resistance than the channel forming region and higher resistance than the source region and the drain region.
Hasaka teaches a light irradiation region (108n, col 12 line 28, specifies 108 as semiconductor material which absorbs light, and 108n is part of 108) which is made low- resistance (col 12 line 31) between the channel forming region (108) and the source region (120a col 13, line 35) and between the channel forming region (108) and the drain region (120b),
the light irradiation region includes a first region (108n on left) between the channel forming region (108) and the source region (120a) and a second region (108n on right) between the channel forming region (108) and the drain region (120b),
the first region (108n on left) and the second region (108n on right) are overlapped with one of the first gate electrode (106) and the second gate electrode (112), but not overlapped with the other of the first gate electrode and the second gate electrode (light irradiation region 108n overlaps with 106 and NOT 112, FIG. 2B), and
the first region (108n on left, col 31 line 57 states, “As shown in FIG. 10A, low-resistance regions 108na are provided in regions of the semiconductor layer 108a…”) and the second region (108n on right) have lower resistance than the channel forming region (108, col 12 line 30 states, “The regions 108n are parts of the semiconductor layer 108 and have resistance lower than that of the channel formation region.”) and higher resistance than the source region and the drain region (col 32 line 38 states, “Moreover, an increase in the resistance of the low-resistance regions 108na in the semiconductor layer 108a due to the supply of oxygen thereto can be prevented, so that the resistance between a source and a drain can be low.” 108na had low resistance, and the resistance was increased, so the source and drain resistance can be low implying the source and drain have a lower resistivity.).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Hosaka into the structure of Yamazaki since both patents use semiconductors with similar chip architecture designs with relation to the source/drain, semiconductor layer and electrodes.
The ordinary artisan would have been motivated to modify Hosaka in combination with Yamazaki in the above manner for the motivation of optimizing the resistivity of the light irradiation regions to obtain an optimal image on a display device. Col 1 line 46 states, “A transistor including an oxide has high field-effect mobility; therefore, a high-performance display device where a display portion and a driver circuit are formed over the same substrate can be obtained.”
The limitation "by irradiating light" is merely a product-by-process limitation. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Re Claim 4 Yamazaki in view of Hosaka teaches the transistor according to claim 1, wherein the source electrode (Yamazaki, 113a) and the drain electrode (113b) contact the oxide semiconductor layer (112, [0273] states, “A source electrode and a drain electrode are provided in contact with a top surface and a side end portion of the semiconductor layer …”, FIG. 24A), and
the second gate electrode (114) is longer than the first gate electrode (111).
Re Claim 6 Yamazaki in view of Hosaka teaches the transistor according to claim 1, wherein the source electrode (Yamazaki, 113a) and the drain electrode (113b) contact the oxide semiconductor layer (112 [0273] states, “A source electrode and a drain electrode are provided in contact with a top surface and a side end portion of the semiconductor layer …”, FIG. 24A), and
the first gate electrode (111) is longer than the second gate electrode (114).
Claims 2-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20170357113 A1) in view of Hosaka (US 10692994 B2) and further in view of Yamazaki (US 20100051949 A1) (Yamazaki949).
Re Claim 2 Yamazaki in view of Hosaka teaches the transistor according to claim 1, wherein the second gate electrode (Yamazaki, 111) is longer than the first gate electrode (114, FIG. 24A).
Yamazaki in view of Hosaka does not teach the source region and the drain region each include an impurity element.
Yamazaki949 teaches the source region (104a) [0212] and the drain region (104b) each include an impurity element [0212] (FIG. 5B).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yamazaki949 into the structure of Yamazaki and Hosaka since the patents use semiconductors with similar chip architecture designs with relation to the source/drain, semiconductor layer, and electrodes.
The ordinary artisan would have been motivated to modify Yamazaki949 in combination with Yamazaki and Hosaka in the above manner for the motivation of having the source and drain regions contain impurity elements to help the chip function optimally and block oxygen. [0213] states, “Such an impurity element (for example, magnesium, aluminum, titanium, or the like), when included in the source and drain regions, has an oxygen blocking effect and the like.”
Re Claim 3 Yamazaki in view of Hosaka and Yamazaki949 teaches the transistor according to claim 2, wherein the impurity element is hydrogen, argon, phosphorous, or boron (Yamazaki949 [0213] uses identifies boron as an example impurity element).
Re Claim 5 Yamazaki in view of Hosaka teaches the transistor according to claim 1, wherein the first gate electrode is longer (Yamazaki, 111) than the second gate electrode (114).
Yamazaki in view of Hosaka does not teach the source region and the drain region each include an impurity element.
Yamazaki949 teaches the source region (104a) and the drain region (104b) each include an impurity element (Yamazaki949 [0130] states, “. . . an impurity element is included in the source and drain regions . . .”).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yamazaki949 into the structure of Yamazaki and Hosaka since the patents use semiconductors with similar chip architecture designs with relation to the source/drain, semiconductor layer, and electrodes.
The ordinary artisan would have been motivated to modify Yamazaki949 in combination with Yamazaki and Hosaka in the above manner for the motivation of having the source and drain regions contain impurity elements to help the chip function optimally and block oxygen. [0213] states, “Such an impurity element (for example, magnesium, aluminum, titanium, or the like), when included in the source and drain regions, has an oxygen blocking effect and the like.”
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Hosaka and further in view of Yoon (US 20120007158 A1).
Re Claim 7 Yamazaki in view of Hosaka teaches the transistor according to claim 1,
Yamazaki in view of Hosaka teaches further comprising an insulating layer (Yamazaki, 136, FIG. 24A) between the oxide semiconductor layer (112) and the second gate electrode (114),
Yamazaki in view of Hosaka does not teach wherein the insulating layer includes a first layer contacting the channel forming region and a second layer contacting the light irradiation region, and defects included in the first layer are less than defects included in the second layer.
Yoon teaches wherein the insulating layer includes a first layer (110A) [0059] contacting the channel forming region and a second layer (112A) [0043] contacting the light irradiation region (FIG. 3G), and defects included in the first layer are less than defects included in the second layer (FIG. 3G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yoon into the structure of Yamazaki in view of Hosaka since all the patents share similar transistor designs.
The ordinary artisan would have been motivated to modify Yoon in combination with Yamazaki in view of Hosaka in the above manner for the motivation of optimizing defects levels between the device layers. [0008] states, “In the flexible and transparent electronics, if a memory device can be built in a system, the functionality of the system can be greatly improved, power consumption can be reduced, and production cost can be reduced.”
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Hosaka and further in view of Oyamada (US 20080012475 A1).
Re Claim 8 Yamazaki in view of Hosaka teaches the transistor according to claim 1,
Yamazaki in view of Hosaka does not teach wherein the light has luminosity of 100 cd/m2 or more.
Oyamada teaches wherein the light has luminosity of 100 cd/m2 or more ([0138] states, “. . . the luminous brightness should be . . . 100 cd/m.sup.2 or more.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Oyamada into the structure of Yamazaki in view of Hosaka since both patents are all basic transistor devices. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal luminosity.
The ordinary artisan would have been motivated to modify Oyamada in combination with Yamazaki in view of Hosaka in the above manner for the motivation of optimizing the semiconductor device’s luminosity.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 10/22/25