Response to Amendment
The amendment filed 05/15/2026 has been accepted and entered.
Response to Arguments
Applicant’s amendments to independent claim 1, and its respective dependent claims and corresponding arguments, see page 8-10 of Applicant’s remarks filed 05/15/2026, with respect to the 35 U.S.C. 102 rejection of independent claim 1 has been fully considered and is persuasive. Cheng does not teach all of the limitations of amended claim 1 (i.e. the inclusion of a backside power delivery network with contacts connecting source/drain regions on the frontside of the semiconductor device) and thus and its respective dependent claims.
In view of the amendments, new references have been applied (new references US 2023/0411386 A1 Xie et al, see below). Claims 1-3, 6-8, 11-12, 14-16, and 21-25 now stand rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Xie, see below. Claims 4-5, 10, and 13 now stand rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Xie and further in view of Li, see below.
Status of Claims
Claims 1-8, 10-16, and 21-25 are pending.
Claims 9 and 17-20 are cancelled.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites the element “the dielectric isolation” in line 14 of the claim. It should instead read “the dielectric isolation layer”. Appropriate correction is required.
Claim 22 is objected to because of the following informalities: Claim 22 recites two commas in line 1 of the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 6-8, 11-12, 14-16, and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0065446 A1 Cheng (herein “Cheng”) in view of US 2023/0411386 A1 Xie et al (herein “Xie”).
Regarding Claim 1, Cheng discloses:
A semiconductor structure (#1, see generally the embodiment of semiconductor device shown in Fig. 1, reference may be made to methods of manufacturing in Figures 2-27) comprising:
one or more transistor devices on a first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1, Fig. 1);
one or more transistor devices on a second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1), the second side (top side) being opposite the first side (bottom side); and
a dielectric isolation layer (#95, not labelled in Fig. 1, see formation of #95 in Fig. 25 and completed device in Fig. 27) separating the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) from the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure;
wherein the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) comprise first channel layers (#22A-22C, Fig. 12A-C, [0063]) and first source/drain regions (#82, Fig. 12A-C, [0064]) on a first side of the dielectric isolation layer (#95);
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) comprise second channel layers (#101, [0090], see annotated Fig. 1 below) and second source/drain regions (#103/105, [0090], see annotated Fig. 1 below) on a second side (top side) of the dielectric isolation layer (#95), the second channel layers (#101) and the second source/drain regions (#103/105) of the one or more transistors on the second side (top side) of the dielectric isolation layer (#95) being independent of the first channel layers (#22A-C) and the first source/drain regions (#82) of the one or more transistor devices on the first side (bottom side) of the semiconductor structure (#1);
Cheng does not explicitly disclose:
an interconnect structure disposed over the one or more transistor devices on the first side of the semiconductor structure;
a power delivery network disposed below the one or more transistor devices on the second side of the semiconductor structure; and
one or more contacts extending from the power delivery network and connecting to one or more of the first source/drain regions of at least one of the one or more transistor devices on the first side of the semiconductor structure.
However, in analogous art, Xie teaches:
See Fig. 23. See also [0112]-[0114].
an interconnect structure (#220, Fig. 23) disposed over the one or more transistor devices on the first side (top side) of the semiconductor structure;
a power delivery network (#250, Fig. 23, [0113]) disposed below the one or more transistor devices on the second side (bottom side) of the semiconductor structure; and
one or more contacts (#285) extending from the power delivery network (#250) and connecting to one or more of the first source/drain regions (#155, [0113]) of at least one of the one or more transistor devices on the first side (top side) of the semiconductor structure.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Xie to the device disclosed by Cheng and include a backside power delivery network for the purposes of sending electrical signals to transistor structures on both sides of the dielectric isolation layer. Cheng is silent regarding the power delivery network for the transistor structures therefore motivating a person of ordinary skill to seek out such teachings like disclosed by Xie to practice the invention of Cheng
Regarding Claim 2, Cheng in view of Xie discloses: The semiconductor structure of claim 1,
Cheng further discloses:
wherein the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure comprise nanosheet field-effect transistor devices (see [0043] and [0069]).
Regarding Claim 3, Cheng in view of Xie discloses: The semiconductor structure of claim 2,
Cheng further discloses:
wherein the first channel layers (#22A-C, Fig. 6A, [0069]) of the one or more transistor devices on the first side (bottom side) of the semiconductor structure (#1) have a first channel length (see annotated Fig. 1 above), wherein the second channel layers (#101) of the one or more transistor devices on the second side (bottom side) of the semiconductor structure (#1) have a second channel length (see annotated Fig. 1 above), the second channel length being greater than the first channel length (see annotated Fig. 1 above).
Regarding Claim 6, Cheng in view of Xie discloses: The semiconductor structure of claim 1,
Cheng further discloses:
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) are disposed on a first side (top side of nanosheet transistor structure) of a first subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1), and wherein the one or more contacts (#285, feature combined from Xie) extending from the power delivery network (#250, feature combined from Xie) disposed on the first side (top side of nanosheet transistor structure) of a second subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
Regarding Claim 7, Cheng in view of Xie discloses: The semiconductor structure of claim 6,
Cheng further discloses:
wherein the one or more contacts (#285, feature combined from Xie) connect to one or more of the first source/drain regions (#82, [0063], Fig. 27) of one or more of the transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) that are in the second subset (see annotated Fig. 1 above).
Regarding Claim 8, Cheng in view of Xie discloses: The semiconductor structure of claim 6,
Cheng further discloses:
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) are not disposed on the first side (top side of nanosheet transistor structure) of the second subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
For the purposes of examination under the broadest reasonable interpretation, the term “on” in the context of claim 8 will be interpreted as “directly on”. Under this definition, the claim reads on Fig. 12A of the drawings, wherein the transistor structure on the second side is not directly on the transistor structures on the first side, as there is a dielectric isolation layer disposed between them.
Similarly, Cheng also has a dielectric layer between the transistor structures on the second side and the first side that are isolated from each other by a dielectric layer and subsequently, the one or more transistor devices on the second side of the semiconductor structure are not disposed on the first side of the second subset of the one or more transistor devices on the first side of the semiconductor structure, thus the claim also reads on the device disclosed by Cheng.
Regarding Claim 11, Cheng discloses:
An integrated circuit (#1, see generally the embodiment of semiconductor device shown in Fig. 1, reference may be made to methods of manufacturing in Figures 2-27) comprising:
a semiconductor structure (#1, see generally the embodiment of semiconductor device shown in Fig. 1, reference may be made to methods of manufacturing in Figures 2-27) comprising:
one or more transistor devices on a first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1, Fig. 1);
one or more transistor devices on a second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1), the second side (top side) being opposite the first side (bottom side); and
a dielectric isolation layer (#95, not labelled in Fig. 1, see formation of #95 in Fig. 25 and completed device in Fig. 27) separating the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) from the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure;
wherein the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) comprise first channel layers (#22A-22C, Fig. 12A-C, [0063]) and first source/drain regions (#82, Fig. 12A-C, [0064]) on a first side of the dielectric isolation layer (#95);
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) comprise second channel layers (#101, [0090], see annotated Fig. 1 below) and second source/drain regions (#103/105, [0090], see annotated Fig. 1 below) on a second side (top side) of the dielectric isolation layer (#95), the second channel layers (#101) and the second source/drain regions (#103/105) of the one or more transistors on the second side (top side) of the dielectric isolation layer (#95) being independent of the first channel layers (#22A-C) and the first source/drain regions (#82) of the one or more transistor devices on the first side (bottom side) of the semiconductor structure (#1);
Cheng does not explicitly disclose:
an interconnect structure disposed over the one or more transistor devices on the first side of the semiconductor structure;
a power delivery network disposed below the one or more transistor devices on the second side of the semiconductor structure; and
one or more contacts extending from the power delivery network and connecting to one or more of the first source/drain regions of at least one of the one or more transistor devices on the first side of the semiconductor structure.
However, in analogous art, Xie teaches:
See Fig. 23. See also [0112]-[0114].
an interconnect structure (#220, Fig. 23) disposed over the one or more transistor devices on the first side (top side) of the semiconductor structure;
a power delivery network (#250, Fig. 23, [0113]) disposed below the one or more transistor devices on the second side (bottom side) of the semiconductor structure; and
one or more contacts (#285) extending from the power delivery network (#250) and connecting to one or more of the first source/drain regions (#155, [0113]) of at least one of the one or more transistor devices on the first side (top side) of the semiconductor structure.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Xie to the device disclosed by Cheng and include a backside power delivery network for the purposes of sending electrical signals to transistor structures on both sides of the dielectric isolation layer. Cheng is silent regarding the power delivery network for the transistor structures therefore motivating a person of ordinary skill to seek out such teachings like disclosed by Xie to practice the invention of Cheng
Regarding Claim 12, Cheng in view of Xie discloses: The semiconductor structure of claim 11,
Cheng further discloses:
wherein the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) comprise nanosheet field-effect transistor devices ([0069]).
Regarding Claim 14, Cheng discloses:
The integrated circuit of claim 11, wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) are disposed on a first side (top side of nanosheet transistor structure) of a first subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1), and wherein the one or more contacts (#285, feature combined from Xie) extending from the power delivery network (#250, feature combined from Xie) disposed on the first side (top side of nanosheet transistor structure) of a second subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
Regarding Claim 15, Cheng discloses:
The integrated circuit of claim 14, wherein the one or more contacts (#EVP, Fig. 1) connect to one or more of the first source/drain regions (#82, [0063], Fig. 27) of one or more of the transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) that are in the second subset (see annotated Fig. 1 above).
Regarding Claim 16, Cheng discloses:
A method (#1, see generally the embodiment of semiconductor device shown in Fig. 1, reference may be made to methods of manufacturing in Figures 2-27) comprising:
forming one or more transistor devices on a first side (#10, Fig. 1, bottom side) of a semiconductor structure (#1, Fig. 1);
forming one or more transistor devices on a second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1), the second side (top side) being opposite the first side (bottom side); and
forming a dielectric isolation layer (#95, not labelled in Fig. 1, see formation of #95 in Fig. 25 and completed device in Fig. 27) separating the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) from the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure;
wherein the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) comprise first channel layers (#22A-22C, Fig. 12A-C, [0063]) and first source/drain regions (#82, Fig. 12A-C, [0064]) on a first side of the dielectric isolation layer (#95);
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) comprise second channel layers (#101, [0090], see annotated Fig. 1 below) and second source/drain regions (#103/105, [0090], see annotated Fig. 1 below) on a second side (top side) of the dielectric isolation layer (#95), the second channel layers (#101) and the second source/drain regions (#103/105) of the one or more transistors on the second side (top side) of the dielectric isolation layer (#95) being independent of the first channel layers (#22A-C) and the first source/drain regions (#82) of the one or more transistor devices on the first side (bottom side) of the semiconductor structure (#1);
Cheng does not explicitly disclose:
forming an interconnect structure disposed over the one or more transistor devices on the first side of the semiconductor structure;
forming a power delivery network disposed below the one or more transistor devices on the second side of the semiconductor structure; and
forming one or more contacts extending from the power delivery network and connecting to one or more of the first source/drain regions of at least one of the one or more transistor devices on the first side of the semiconductor structure.
However, in analogous art, Xie teaches:
See Fig. 23. See also [0112]-[0114].
forming an interconnect structure (#220, Fig. 23) disposed over the one or more transistor devices on the first side (top side) of the semiconductor structure;
forming a power delivery network (#250, Fig. 23, [0113]) disposed below the one or more transistor devices on the second side (bottom side) of the semiconductor structure; and
forming one or more contacts (#285) extending from the power delivery network (#250) and connecting to one or more of the first source/drain regions (#155, [0113]) of at least one of the one or more transistor devices on the first side (top side) of the semiconductor structure.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Xie to the device disclosed by Cheng and include a backside power delivery network for the purposes of sending electrical signals to transistor structures on both sides of the dielectric isolation layer. Cheng is silent regarding the power delivery network for the transistor structures therefore motivating a person of ordinary skill to seek out such teachings like disclosed by Xie to practice the invention of Cheng
Regarding Claim 21, Cheng in view of Xie discloses: The integrated circuit of claim 11,
Cheng further discloses:
wherein the first channel layers (#22A-C, Fig. 6A, [0069]) of the one or more transistor devices on the first side (bottom side) of the semiconductor structure (#1) have a first channel length (see annotated Fig. 1 above), wherein the second channel layers (#101) of the one or more transistor devices on the second side (bottom side) of the semiconductor structure (#1) have a second channel length (see annotated Fig. 1 above), the second channel length being greater than the first channel length (see annotated Fig. 1 above).
Regarding Claim 22, Cheng in view of Xie discloses: The method of claim 16,
Cheng further discloses:
wherein the first channel layers (#22A-C, Fig. 6A, [0069]) of the one or more transistor devices on the first side (bottom side) of the semiconductor structure (#1) have a first channel length (see annotated Fig. 1 above), wherein the second channel layers (#101) of the one or more transistor devices on the second side (bottom side) of the semiconductor structure (#1) have a second channel length (see annotated Fig. 1 above), the second channel length being greater than the first channel length (see annotated Fig. 1 above).
Regarding Claim 23, Cheng in view of Xie discloses: The method of claim 16,
Cheng further discloses:
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) are disposed on a first side (top side of nanosheet transistor structure) of a first subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1), and wherein the one or more contacts (#285, feature combined from Xie) extending from the power delivery network (#250, feature combined from Xie) disposed on the first side (top side of nanosheet transistor structure) of a second subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
Regarding Claim 24, Cheng in view of Xie discloses: The method of claim 23,
Cheng further discloses:
wherein the one or more contacts (#285, feature combined from Xie) connect to one or more of the first source/drain regions (#82, [0063], Fig. 27) of one or more of the transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) that are in the second subset (see annotated Fig. 1 above).
Regarding Claim 25, Cheng in view of Xie discloses: The method of claim 23,
Cheng further discloses:
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) are not disposed on the first side (top side of nanosheet transistor structure) of the second subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
For the purposes of examination under the broadest reasonable interpretation, the term “on” in the context of claim 8 will be interpreted as “directly on”. Under this definition, the claim reads on Fig. 12A of the drawings, wherein the transistor structure on the second side is not directly on the transistor structures on the first side, as there is a dielectric isolation layer disposed between them.
Similarly, Cheng also has a dielectric layer between the transistor structures on the second side and the first side that are isolated from each other by a dielectric layer and subsequently, the one or more transistor devices on the second side of the semiconductor structure are not disposed on the first side of the second subset of the one or more transistor devices on the first side of the semiconductor structure, thus the claim also reads on the device disclosed by Cheng.
Claims 4-5, 10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0065446 A1 Cheng et al in view of US 2023/0411386 A1 Xie et al and further in view of US 2022/0013356 A1 Li et al (herein “Li”).
Regarding Claim 4, Cheng in view of Xie discloses: The semiconductor structure of claim 1.
Cheng in view of Xie does not explicitly disclose:
wherein the channel layers of the one or more transistor devices on the second side of the semiconductor structure comprise a single-crystal semiconductor material.
However, in analogous art, Li teaches:
wherein the channel layers of the TFT semiconductor structure comprise a single-crystal semiconductor material (see [0098], specifically “the various embodiments disclosed herein provide improved TFTs that may be formed in a BEOL with hybrid single-crystal silicon channel to provide TFTs with improved mobility, resistance and threshold voltage characteristics.” See also 0020] and [0021]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider substituting the material of the channel of the TFT semiconductor structure on the second side of the semiconductor device for a single crystal semiconductor material as disclosed by Li as Cheng in view of Xie is silent on the specific material used for the channel of the TFT device. Single-crystal silicon channel may provide TFTs with improved mobility, resistance and threshold voltage characteristics, which would lead to an overall more efficient device. See Li [0098].
Regarding Claim 5, Cheng in view of Xie discloses: The semiconductor structure of claim 1.
Cheng in view of Xie does not explicitly disclose:
wherein the channel layers of the one or more transistor devices on the second side of the semiconductor structure comprise single-crystal silicon.
However, in analogous art, Li teaches:
wherein the channel layers of the TFT semiconductor structure comprise single-crystal silicon (see [0098], specifically “the various embodiments disclosed herein provide improved TFTs that may be formed in a BEOL with hybrid single-crystal silicon channel to provide TFTs with improved mobility, resistance and threshold voltage characteristics.” See also 0020] and [0021]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider substituting the material of the channel of the TFT semiconductor structure on the second side of the semiconductor device for a single crystal semiconductor material as disclosed by Li, as Cheng in view of Xie is silent on the specific material used for the channel of the TFT device. Single-crystal silicon channel may provide TFTs with improved mobility, resistance and threshold voltage characteristics, which would lead to an overall more efficient device. See Li [0098].
Regarding Claim 10, Cheng in view of Xie discloses: The semiconductor structure of claim 1.
Cheng in view of Xie does not explicitly disclose:
wherein the one or more transistor devices on the second side of the semiconductor structure comprise thick gate oxide transistor devices.
However, in analogous art, Li teaches:
wherein the channel layers of the TFT semiconductor structure comprise gate oxide material (see [0031], specifically “Various embodiments are disclosed herein provide for TFTs that include hybrid crystalline oxide and single-crystal silicon (c-Si) channel layers that have reduced channel resistance and threshold voltage, and/or improved channel mobility.” See also [0032]: “FIGS. 2A-2J are vertical cross-sectional views illustrating a method of manufacturing a top-gate (front-gate) transistor 200 including a hybrid crystalline metal oxide and c-Si semiconductor channel layer 125”).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider forming the channel of the TFT semiconductor structure on the second side of the semiconductor device using a gate oxide material as disclosed by Li, as Cheng in view of Xie is silent on the specific material used for the channel of the TFT device. Utilizing a gate oxide material may provide TFTs with reduced channel resistance and threshold voltage, and/or improved channel mobility, which would lead to an overall more efficient device. See Li [0032].
Regarding Claim 13, Cheng in view of Xie discloses: The semiconductor structure of claim 11.
Cheng in view of Xie does not explicitly disclose:
wherein the channel layers of the one or more transistor devices on the second side of the semiconductor structure comprise a single-crystal semiconductor material.
However, in analogous art, Li teaches:
wherein the channel layers of the TFT semiconductor structure comprise a single-crystal semiconductor material (see [0098], specifically “the various embodiments disclosed herein provide improved TFTs that may be formed in a BEOL with hybrid single-crystal silicon channel to provide TFTs with improved mobility, resistance and threshold voltage characteristics.” See also 0020] and [0021]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider substituting the material of the channel of the TFT semiconductor structure on the second side of the semiconductor device for a single crystal semiconductor material as disclosed by Li as Cheng in view of Xie is silent on the specific material used for the channel of the TFT device. Single-crystal silicon channel may provide TFTs with improved mobility, resistance and threshold voltage characteristics, which would lead to an overall more efficient device. See Li [0098].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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