Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
The election of invention I drawn to claims 1-15 and linking claim 16 is acknowledged. Claims 17-20 are withdrawn from consideration.
Status of Claims
Claims 1-20 pending.
Claims 17-20 withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, the term “long channel transistors” in claim 9 is a relative term which renders the claim indefinite. The term “long channel transistors” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For the purposes of examination, and to remain consistent with other claimed elements in the originally filed set of claims, specifically see claim 2 as a reference, the term “long channel transistors” when applied to the transistor structure on the second side of the semiconductor device will be interpreted as having a channel length greater than the channel length of the transistor structure on the first side of the semiconductor device. In this case, looking at Fig. 12A of the drawings as a reference, the channel 110-1 of the transistor structure on the second side (top side) of the semiconductor device is wider (longer) than the channel 110-2 of the transistor structures on the first side (bottom side) of the semiconductor device, thus can be considered a long channel transistor.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-9, 11, and 14-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0065446 A1 Cheng (herein “Cheng”).
Regarding Claim 1, Cheng discloses:
A semiconductor structure (#1, see generally the embodiment of semiconductor device shown in Fig. 1, reference may be made to methods of manufacturing in Figures 2-27) comprising:
one or more transistor devices on a first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1, Fig. 1);
one or more transistor devices on a second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1), the second side (top side) being opposite the first side (bottom side); and
a dielectric isolation layer (#95, not labelled in Fig. 1, see formation of #95 in Fig. 25 and completed device in Fig. 27) separating the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) from the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure;
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) comprise channel layers (#101, Fig. 1, see [0090]) on one side of the dielectric isolation layer (#95) and source/drain regions (#103/105, [0090]) that are independent of source/drain regions (#82, [0063]) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
Regarding Claim 2, Cheng discloses:
The semiconductor structure of claim 1, wherein the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure comprise nanosheet field-effect transistor devices (see [0043] and [0069]).
Regarding Claim 3, Cheng discloses:
The semiconductor structure of claim 2, wherein the channel layers of the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) have a first channel length (see annotated Fig. 1 below) greater than a second channel length (see annotated Fig. 1 below) of nanosheet channel layers (#22, Fig. 6A, [0069]) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
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Cheng Fig. 1 – Annotated by Examiner
Regarding Claim 6, Cheng discloses:
The semiconductor structure of claim 1, wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) are disposed on a first side (top side of nanosheet transistor structure) of a first subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1), and further comprising one or more contacts (#EVP, Fig. 1) disposed on the first side (top side of nanosheet transistor structure) of a second subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
Regarding Claim 7, Cheng discloses:
The semiconductor structure of claim 6, wherein the one or more contacts (#EVP, Fig. 1) connect to one or more of the source/drain regions (#82, [0063], Fig. 27) of one or more of the transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) that are in the second subset (see annotated Fig. 1 above).
Regarding Claim 8, Cheng discloses:
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) are not disposed on the first side (top side of nanosheet transistor structure) of the second subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
For the purposes of examination under the broadest reasonable interpretation, the term “on” in the context of claim 8 will be interpreted as “directly on”. Under this definition, the claim reads on Fig. 12A of the drawings, wherein the transistor structure on the second side is not directly on the transistor structures on the first side, as there is a dielectric isolation layer disposed between them.
Similarly, Cheng also has a dielectric layer between the transistor structures on the second side and the first side that are isolated from each other by a dielectric layer and subsequently, the one or more transistor devices on the second side of the semiconductor structure are not disposed on the first side of the second subset of the one or more transistor devices on the first side of the semiconductor structure, thus the claim also reads on the device disclosed by Cheng.
Regarding Claim 9, Cheng discloses:
The semiconductor structure of claim 1, wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) comprise long channel transistors (channel of the TFT structure on the second side is longer than the channel of the FinFET channels on the first side, additionally, see 112(b) rejection of claim 9 above).
Regarding Claim 11, Cheng discloses:
An integrated circuit (#1, see generally the embodiment of semiconductor device shown in Fig. 1, reference may be made to methods of manufacturing in Figures 2-27) comprising:
one or more transistor devices on a first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1, Fig. 1);
one or more transistor devices on a second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1), the second side (top side) being opposite the first side (bottom side); and
a dielectric isolation layer (#95, not labelled in Fig. 1, see formation of #95 in Fig. 25 and completed device in Fig. 27) separating the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) from the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure;
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) comprise channel layers (#101, Fig. 1, see [0090]) on one side of the dielectric isolation layer (#95) and source/drain regions (#103/105, [0090]) that are independent of source/drain regions (#82, [0063]) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
Regarding Claim 12, Cheng discloses:
The integrated circuit of claim 11, wherein the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) comprise nanosheet field-effect transistor devices ([0069]), and wherein the channel layers of the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) have a first channel length (see annotated Fig. 1 above) greater than a second channel length (see annotated Fig. 1 above) of nanosheet channel layers (#22, Fig. 6A, [0069]) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
Regarding Claim 14, Cheng discloses:
The integrated circuit of claim 11, wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) are disposed on a first side (top side of nanosheet transistor structure) of a first subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1), and further comprising one or more contacts (#EVP, Fig. 1) disposed on the first side (top side of nanosheet transistor structure) of a second subset (see annotated Fig. 1 above) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
Regarding Claim 15, Cheng discloses:
The integrated circuit of claim 14, wherein the one or more contacts (#EVP, Fig. 1) connect to one or more of the source/drain regions (#82, [0063], Fig. 27) of one or more of the transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) that are in the second subset (see annotated Fig. 1 above).
Regarding Claim 16, Cheng discloses:
A method (see generally the embodiment of semiconductor device shown in Fig. 1, reference made to methods of manufacturing in Figures 2-27) comprising:
forming one or more transistor devices on a first side (#10, Fig. 1, bottom side) of a semiconductor structure (#1, Fig. 1);
forming one or more transistor devices on a second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1), the second side (top side) being opposite the first side (bottom side); and
forming a dielectric isolation layer (#95, not labelled in Fig. 1, see formation of #95 in Fig. 25 and completed device in Fig. 27) separating the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1) from the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure;
wherein the one or more transistor devices on the second side (#TFT, Fig. 1, top side) of the semiconductor structure (#1) comprise channel layers (#101, Fig. 1, see [0090]) on one side of the dielectric isolation layer (#95) and source/drain regions (#103/105, [0090]) that are independent of source/drain regions (#82, [0063]) of the one or more transistor devices on the first side (#10, Fig. 1, bottom side) of the semiconductor structure (#1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-5, 10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0065446 A1 Cheng et al in view of US 2022/0013356 A1 Li et al (herein “Li”).
Regarding Claim 4, Cheng discloses:
The semiconductor structure of claim 1.
Cheng does not explicitly disclose:
wherein the channel layers of the one or more transistor devices on the second side of the semiconductor structure comprise a single-crystal semiconductor material.
However, in analogous art, Li teaches:
wherein the channel layers of the TFT semiconductor structure comprise a single-crystal semiconductor material (see [0098], specifically “the various embodiments disclosed herein provide improved TFTs that may be formed in a BEOL with hybrid single-crystal silicon channel to provide TFTs with improved mobility, resistance and threshold voltage characteristics.” See also 0020] and [0021]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider substituting the material of the channel of the TFT semiconductor structure on the second side of the semiconductor device for a single crystal semiconductor material as disclosed by Li as Cheng is silent on the specific material used for the channel of the TFT device. Single-crystal silicon channel may provide TFTs with improved mobility, resistance and threshold voltage characteristics, which would lead to an overall more efficient device. See Li [0098].
Regarding Claim 5, Cheng discloses:
The semiconductor structure of claim 1.
Cheng does not explicitly disclose:
wherein the channel layers of the one or more transistor devices on the second side of the semiconductor structure comprise single-crystal silicon.
However, in analogous art, Li teaches:
wherein the channel layers of the TFT semiconductor structure comprise single-crystal silicon (see [0098], specifically “the various embodiments disclosed herein provide improved TFTs that may be formed in a BEOL with hybrid single-crystal silicon channel to provide TFTs with improved mobility, resistance and threshold voltage characteristics.” See also 0020] and [0021]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider substituting the material of the channel of the TFT semiconductor structure on the second side of the semiconductor device for a single crystal semiconductor material as disclosed by Li, as Cheng is silent on the specific material used for the channel of the TFT device. Single-crystal silicon channel may provide TFTs with improved mobility, resistance and threshold voltage characteristics, which would lead to an overall more efficient device. See Li [0098].
Regarding Claim 10, Cheng discloses:
The semiconductor structure of claim 1.
Cheng does not explicitly disclose:
wherein the one or more transistor devices on the second side of the semiconductor structure comprise thick gate oxide transistor devices.
However, in analogous art, Li teaches:
wherein the channel layers of the TFT semiconductor structure comprise gate oxide material (see [0031], specifically “Various embodiments are disclosed herein provide for TFTs that include hybrid crystalline oxide and single-crystal silicon (c-Si) channel layers that have reduced channel resistance and threshold voltage, and/or improved channel mobility.” See also [0032]: “FIGS. 2A-2J are vertical cross-sectional views illustrating a method of manufacturing a top-gate (front-gate) transistor 200 including a hybrid crystalline metal oxide and c-Si semiconductor channel layer 125”).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider forming the channel of the TFT semiconductor structure on the second side of the semiconductor device using a gate oxide material as disclosed by Li, as Cheng is silent on the specific material used for the channel of the TFT device. Utilizing a gate oxide material may provide TFTs with reduced channel resistance and threshold voltage, and/or improved channel mobility, which would lead to an overall more efficient device. See Li [0032].
Regarding Claim 13, Cheng discloses:
The semiconductor structure of claim 11.
Cheng does not explicitly disclose:
wherein the channel layers of the one or more transistor devices on the second side of the semiconductor structure comprise a single-crystal semiconductor material.
However, in analogous art, Li teaches:
wherein the channel layers of the TFT semiconductor structure comprise a single-crystal semiconductor material (see [0098], specifically “the various embodiments disclosed herein provide improved TFTs that may be formed in a BEOL with hybrid single-crystal silicon channel to provide TFTs with improved mobility, resistance and threshold voltage characteristics.” See also 0020] and [0021]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider substituting the material of the channel of the TFT semiconductor structure on the second side of the semiconductor device for a single crystal semiconductor material as disclosed by Li as Cheng is silent on the specific material used for the channel of the TFT device. Single-crystal silicon channel may provide TFTs with improved mobility, resistance and threshold voltage characteristics, which would lead to an overall more efficient device. See Li [0098].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812