DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/2025 has been entered.
Response to Arguments
Applicant’s arguments filed 11/06/2025 have been fully considered but are not persuasive. Applicant asserts that Koh et al. (US 2021/0202670 A1; hereinafter “Koh”), in view of Shin et al. (US 2018/0069128 A1; hereinafter “Shin”) fails to teach “an insulating layer on which the semiconductor layer is disposed, and the insulating layer covers the first layer, a side surface of the first sub-data line and an upper surface of the second sub-data line”. The Examiner respectfully disagrees with this assertion. As shown in Fig. 4 of Koh the active pattern 130 made of a silicon-based semiconductor material is shown on the buffer film 110 which functions as the insulating layer. Further the buffer film 110 covers the layer containing the auxiliary electrode 105 which functions as the first layer. The Examiner notes that Koh does not fully teach the limitation regarding the insulating layer covering a side surface of the first sub-data line and an upper surface of the second sub-data line as the buffer layer only covers the side surface of the auxiliary electrode 120. However, as shown in Shin in Fig. 5, the passivation layer 180 is shown covering the side edges of a first layer 170a of the metal layer 170 and the upper surface of a second layer 170b of the metal layer 170.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-10 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Koh et al. (US 2021/0202670 A1; hereinafter “Koh”), in view of Shin et al. (US 2018/0069128 A1; hereinafter Shin).
In regard to claim 1, Koh teaches a display device comprising: a substrate (a first substrate 100) including a signal wire area (an area containing auxiliary electrode 120 as shown in annotated Fig. 4 below) and a transistor area (an area containing auxiliary electrodes 106 and 105 as shown in annotated Fig. 4 below) (annotated Fig. 4 and paragraphs 72 and 75) and including a first sub-data line (auxiliary electrode 120) and a second sub-data line (auxiliary interconnection line 145) disposed on the first sub-data line (the auxiliary interconnection line 145 is shown on the auxiliary electrode 120 in Fig. 4) (Fig. 4 and paragraph 87);
a first layer (the layer containing the auxiliary electrode 105) disposed in the transistor area (the auxiliary electrode 105 is positioned in the aforementioned transistor area as shown in annotated Fig. 4 below);
a signal wire (the signal wire is comprised of the auxiliary electrode 120 and first auxiliary interconnection line 145) disposed in the signal wire area (the auxiliary electrode 120 and first auxiliary interconnection line 145 are positioned in the aforementioned transistor area as shown in annotated Fig. 4 below) (annotated Fig. 4 and paragraph 75);
a transistor disposed on the first layer and including a semiconductor layer (the source electrode 141, the drain electrode 142, the gate electrode 143, and the active pattern 130 made of a silicon-based semiconductor material constitute a transistor and are shown on the auxiliary electrode 105 in Fig. 4) (Fig. 4 and paragraphs 79 and 100);
a first electrode (a first electrode 180) electrically connected to the transistor (the drain electrode 142 of the driving transistor DT is connected to the first electrode 180) (Fig. 4 and paragraph 100); and
an emission layer (an emissive layer 200) and a second electrode disposed on the first electrode (Fig. 4 and paragraph 92),
wherein the first layer and the signal wire are disposed on a same layer on the substrate (auxiliary electrode 105 and the auxiliary electrode 120 are shown on the same substrate layer in Fig. 4), and the first layer and the signal wire have different thicknesses (as the auxiliary electrodes 105 and 120 that form the first layer and a portion of the first signal layer are patterned from the same material layer, and the second portion of the signal wire is formed from another conductive film that forms the transistor. The examiner takes official notice that the components that form the first layer and the signal wire would have different thicknesses due to the multiple layers constituting the signal wire) (Fig. 4 and paragraphs 75-76 and 99), and wherein the display device further comprises an insulating layer (an insulating layer is comprised of a buffer film 110 and a gate insulating film 140) on which the semiconductor layer is disposed (Fig. 4 and paragraphs 78 and 83), and the insulating layer covers the first layer (the buffer film 110 is shown over the auxiliary electrode 105 in Fig. 4).
However Koh doesn’t explicitly teach wherein side edges of the first sub-data line and the second sub-data line are substantially aligned, and the insulating layer covers a side surface of the first sub-data line and an upper surface of the second sub-data line.
Shin teaches a display device (a display device 10) (Fig. 5 and paragraph 97), wherein side edges of a first sub-data line (a first layer 170a of the metal layer 170) and a second sub-data line (a second layer 170b of the metal layer 170) are substantially aligned (a data line 171 may include a metal layer 170 and a blocking layer 176, and the metal layer 170 may include a first layer 170a and a second layer 170b which are all shown to be substantially aligned in Fig. 5) (Fig. 5 and paragraph 106), a side surface of the first sub-data line and an upper surface of the second sub-data line (the passivation layer 180 is shown covering the side edges of a first layer 170a of the metal layer 170 and the upper surface of a second layer 170b of the metal layer 170) (Fig. 5 and paragraph 112).
It would be obvious to one skilled in the art to combine the teachings of Koh with Shin to have side edges of the first sub-data line and the second sub-data line are substantially aligned since this layout would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Further it would have been obvious to one skilled in the art to have the insulating layer cover a side surface of the first sub-data line and an upper surface of the second sub-data line since it is well known amongst those skilled in the art that this layout prevents unwanted contact between components thereby protecting the device from unwanted shorts.
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In regard to claim 2, Koh teaches wherein the first layer is thinner than the signal wire (as the auxiliary electrodes 105 and 120 that form the first layer and a portion of the first signal layer are patterned from the same material layer, and a second portion of the signal wire is formed from another conductive film that forms the transistor. The examiner takes official notice that the layer that form the first layer would be thinner than the multiple layers that form the signal wire) (Fig. 4 and paragraphs 75-76 and 99).
In regard to claim 4, Koh teaches wherein the signal wire is a data line (interconnection lines which are directly connected to the auxiliary interconnection lines are responsible for electrical signals transferred to the pixels PX may include data lines DL1 to DLm) (Fig. 4 and paragraphs 63).
In regard to claim 5, Koh teaches wherein the first layer and the first sub-data line include a same material and are formed at the same time (the auxiliary electrode 105, 106, 107, 120 are made of a metal or a metal alloy selected from a group) (paragraph 76).
Also, the method of forming a device is not germane to the issue of patentability of the device itself. Therefore, the first layer and the first sub-data line being formed at the same time has not been given patentable weight.
In regard to claim 6, Koh teaches wherein the first layer and the first sub-data line include titanium (the auxiliary electrode 120 may contain titanium) (paragraph 76).
In regard to claim 7, Koh teaches wherein the second sub-data line includes copper (the first conductive film which forms the auxiliary interconnection line 145 may be formed from copper) (paragraphs 85-87).
In regard to claim 8, Koh teaches wherein the insulating layer is a buffer layer (a buffer layer is comprised of a buffer film 110 and a gate insulating film 140) disposed on the signal wire and the first layer (the buffer film 110 and gate insulating film 140 are shown on the auxiliary electrodes 105 and 120 in Fig. 4) (Fig. 4 and paragraph 83), and the buffer layer includes a first step caused by the first layer and a second step caused by the signal wire (the first and second steps in the buffer layer 110 and gate insulating film 140 caused by the auxiliary electrodes 105 and 120 are shown in annotated Fig. 4 below).
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In regard to claim 9, Koh teaches wherein the first step is lower than the second step (the first step is shown lower than the second step in annotated Fig. 4 above).
In regard to claim 10, Koh teaches wherein the buffer layer includes an inorganic material (the buffer film 110 is made of an inorganic material such as an oxide or a nitride) (paragraph 78).
In regard to claim 21, Koh teaches an electronic apparatus (a display device 1) (Fig. 3 and paragraph 38), comprising:
a display panel (a display panel 50) including a display area (a display area DA) and a non-display area (a non-display area NDA) (Fig. 3 and paragraphs 38 and 60);
a pad area (a pad area PA) disposed on the non-display area and including a plurality of terminals (a plurality of pads are formed in the pad area in the non-display area NDA) (Fig. 3 and paragraphs 60 and 65); and
a controller (a circuit board 70) connected to the pad area and transmitting image signals to the display panel (the circuit board 70 may include the timing controller 10 which processes the image signal RGB and the control signal CS to be suitable for the operating conditions of the display panel 50) (Fig. 3 and paragraphs 39-40 and 68),
wherein the display panel includes:
a substrate (a first substrate 100) including a signal wire area (area containing auxiliary electrode 120 as shown in annotated Fig. 4 below) and a transistor area (area containing auxiliary electrodes 106 and 105 as shown in annotated Fig. 4 below) (annotated Fig. 4 and paragraphs 72 and 75);
a first layer (the layer containing the auxiliary electrode 105) disposed in the transistor area (the auxiliary electrode 105 is positioned in the aforementioned transistor area as shown in annotated Fig. 4 below);
a signal wire (the signal wire is comprised of the auxiliary electrode 120 and first auxiliary interconnection line 145) disposed in the signal wire area and including a first sub-data line (the auxiliary electrode 120 ) and a second sub-data line (auxiliary interconnection line 145) disposed on the first sub-data line (annotated Fig. 4 and paragraph 75);
a transistor disposed on the first layer and including a semiconductor layer (the source electrode 141, the drain electrode 142, the gate electrode 143, and the active pattern 130 made of a silicon-based semiconductor material constitute a transistor and are shown on the auxiliary electrode 105 in Fig. 4) (Fig. 4 and paragraphs 79 and 100);
a first electrode (a first electrode 180) electrically connected to the transistor (the drain electrode 142 of the driving transistor DT is connected to the first electrode 180) (Fig. 4 and paragraph 100; and
an emission layer (an emissive layer 200) and a second electrode disposed on the first electrode (Fig. 4 and paragraph 92),
wherein the first layer and the signal wire are disposed on a same layer on the substrate (auxiliary electrode 105 and the auxiliary electrode 120 and first auxiliary interconnection line 145 are shown on the same substrate layer in Fig. 4), and the first layer and the signal wire have different thicknesses (as the auxiliary electrodes 105 and 120 that form the first layer and a portion of the first signal layer are patterned from the same material layer, and the 2nd portion of the signal wire is formed from another conductive film that forms the transistor. The components that form the first layer and the signal wire would have different thicknesses due to the multiple layers constituting the signal wire) (Fig. 4 and paragraphs 75-76 and 99), and wherein the display device further comprises an insulating layer (an insulating layer is comprised of a buffer film 110 and a gate insulating film 140) on which the semiconductor layer is disposed (Fig. 4 and paragraphs 78 and 83), and the insulating layer covers the first layer (the buffer film 110 is shown over the auxiliary electrode 105 in Fig. 4).
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However Koh doesn’t explicitly teach wherein side edges of the first sub-data line and the second sub-data line are substantially aligned, and the insulating layer covers a side surface of the first sub-data line and an upper surface of the second sub-data line.
Shin teaches a display device (a display device 10) (Fig. 5 and paragraph 97), wherein side edges of a first sub-data line (a first layer 170a of the metal layer 170) and a second sub-data line (a second layer 170b of the metal layer 170) are substantially aligned (a data line 171 may include a metal layer 170 and a blocking layer 176, and the metal layer 170 may include a first layer 170a and a second layer 170b which are all shown to be substantially aligned in Fig. 5) (Fig. 5 and paragraph 106), a side surface of the first sub-data line and an upper surface of the second sub-data line (the passivation layer 180 is shown covering the side edges of a first layer 170a of the metal layer 170 and the upper surface of a second layer 170b of the metal layer 170) (Fig. 5 and paragraph 112).
It would be obvious to one skilled in the art to combine the teachings of Koh with Shin to have side edges of the first sub-data line and the second sub-data line are substantially aligned since this layout would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Further it would have been obvious to one skilled in the art to have the insulating layer cover a side surface of the first sub-data line and an upper surface of the second sub-data line since it is well known amongst those skilled in the art that this layout prevents unwanted contact between components thereby protecting the device from unwanted shorts.
In regard to claim 22, Koh teaches wherein the first layer and the first sub-data line include a same material and are formed at the same time (the auxiliary electrode 105, 106, 107, 120 are made of a metal or a metal alloy selected from a group) (paragraph 76).
Also, the method of forming a device is not germane to the issue of patentability of the device itself. Therefore, the first layer and the first sub-data line being formed at the same time has not been given patentable weight.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Koh in view of Shin as applied to claim 1 above, in view of Yu et al. (US 2023/0094885 A1; hereinafter “Yu”).
In regard to claim 3 Koh doesn’t explicitly teach wherein the thickness of the first layer is equal to or less than about 500 angstroms and the thickness of the signal wire is from about 3000 to about 10000 angstroms.
Yu teaches a display device (a display panel 100) (Fig. 3 and paragraph 28), wherein the thickness of a first layer (a light shielding layer) is equal to or less than about 500 angstroms and the thickness of the signal wire (a the data line 11) is from about 3000 to about 10000 angstroms (Yu teaches a traditional light shielding layer has a thickness of 500 angstroms, and a thickness of the data line 11 is 2000-4000 angstroms) (Fig. 3 and paragraph 31).
It would’ve been obvious to one skilled in the art at the time to combine the teachings of Koh with the teachings of Yu to have the first layer equal to about 500 angstroms and the thickness of the signal wire be from about 3000 to about 10000 angstroms since it is well known in the art to have a light shielding layer be 500 angstroms and to ensure that the impedance of the data line 11 meets the requirements for transmitting data signals as taught by Yu (paragraph 31). Further it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893