DETAIL ACTION
Notice of Pre-AIA or AIA Status
1 The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is in response to the communication(s) filed 05/11/2026. There are a total of 20 claims pending in the application. Claims 32, 39, and 45 were amended; claims 1-28, 31, 33-35, 38, and 40-41 were cancelled.
INFORMATION CONCERNING IDS:
3. The information disclosure statement (IDS) submitted on 05/11/2026 is incompliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner and a copy (copies) of PTOL-1449(s) initiated and signed by the Examiner is/are attached.
IFORMATION CONCENING DRAWING:
4. Application’s drawing submitted 08/17/2022 are acceptable for examination purposes.
Response to Remarks
5. Applicant arguments have been fully considered and they are partially persuasive. In view of amendment the rejection under 35 USC § 112(b), second paragraph is withdrawn. However, the limitation:
“determining, based on the start program voltage associated with the media access operation performed with respect to the memory block, a defect risk associated with the memory block” (emphasis added)
Included in independent claims 32, 39, and 45 are not described/supported by the specification. As noted in the previous office action the only portion of claimed specification describing “start program voltage” is paragraph [0020-PGPUB] of the instant specification, which for convenience is reproduced as shown below:
“[0020] The supplemental defect management information can include information that can be analyzed to determine a risk of a defect of the memory array. The supplemental defect management information can include information pertaining to a media access operation performed with respect to the memory array. For example, the supplemental defect management information can include information related d a program operation, an erase operation, or a read operation that is performed with respect to the memory array. Examples of information related to a program operation can include dynamic (WL) start program voltage (DSV), number of programming pulses of each threshold voltage level, a check or count fail byte (CFBYTE) of each program verify level, a number of programming loops, information related to detecting a short or leakage during the program operation (e.g., a charge pump clock monitor (CPCM) count of each programming pulse, a WL short sensor reading of each program verify level), etc. Examples of information related to an erase operation can include a number of erase pulses, a CFBYTE of each erase verify level, information related to detecting a short or leakage with respect to a WL or source line during the erase operation (e.g., a CPCM count of each erase pulse, a WL short sensor reading of each erase verify level), etc. Examples of information related to a read operation can include information related to detecting a short or leakage with respect to a WL, WL ramp up time, etc. A CFBYTE threshold is generally decided based on the error correction code (ECC) capability of the memory device, and a CFBYTE number can be determined during each program/erase verify level. If the CFBYTE number for memory cells during a particular program/erase level is below the CFBYTE threshold, these memory cells can be further inhibited from further program/erase in all subsequent program/erase pulses, and the local memory controller can further cease issuing program/erase verify pulses for that particular program/erase verify level in all subsequent program/erase loops.” (Emphasis added).
There is nothing in the claimed specification that teaches or suggests, based on start program voltage associated with the media access operation performed with respect to the memory block, a defect risk of the memory block is determined. As described in paragraph 20 of applicant’s own specification, and as it’s well known in the art, when using program pulses (e.g., voltages) to program a non-volatile memory, it takes a series of program pulses to program the memory and a series of pulses to verify the memory. Contrary to the applicant arguments, the prior art of record teaches using program pulses to program and verify pulses to verify. The series program pulses include a start pulse (e.g., a start voltage) For example, Lee teaches program pulses comprising start voltage (e.g., see Fig.7 of Lee).
Page 9 of the remarks recites:
“The Specification states that the supplemental defect management
information "can include information pertaining to a media access operation performed with respect to the memory array," and that
"examples of information related to a program operation can include
dynamic (WL) start program voltage (DSV), number of programming
pulses of each threshold voltage level, a check or count fail byte
(CFBYTE) of each program verify level, a number of programming loops,
and information related to detecting a short or leakage during the program
operation " (Specification, at 10020, emphasis added.)”
Then, page 9 of the Remarks states “Accordingly, the specification expressly identifies the start program voltage…”
However, the claims were rejected under 35 USC §112(a), first paragraph because the limitation recites “determining, based on the start program voltage…, a defect risk…”
The specification recites that program operation can include start program voltage.
The specification does not describe or support that defect risk can be determined based on the start program voltage.
IFORMATION CONCENING CLAIMS:
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
6. Claims 29-30, 32, 36-37, 39, and 42- 55 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
7. The independent claim 45 has been amended to recite, in part, the limitations:
“determining, based on the start program voltage associated with the media access operation performed with respect to the memory block, a defect status of the memory block” (emphasis added).
The claimed specification does not appear to describe/support the above limitations as claimed. The independent claims 32 and 39 recite similar limitations and are rejected based on the same ground of rejection. The dependent claims 29-30, 36-37, 42-44, and 47-55 are rejected by virtue of their dependency from their respected base claim.
Conclusion
Applicant amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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