DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgment been made to the amendment received 05/26/2026. Claims 1-22 are pending in this office action. Claims 16-22 are previously withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7-9 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Gan et al (US 20210118988A1) in view of Huang et al (US 20180151759A1).
Re claim 1 Gan teaches a semiconductor memory device, comprising:
a memory array (500, fig 8) [0094] formed in a semiconductor structure (530, fig 8) [0093];
a circuit (400, fig 8) [0101] coupled to the memory array (500, fig 8) [0094], the circuit [0101] having rows and columns [0057]; and
a number of isolation trenches (894, fig 8) [0116] between column in the circuit (400, fig 8) [0101].
Gan does not teach the trenches include sidewalls that intersect along a line forming a sharp trench bottom and extend at straight taper from a top of trenches to the sharp trench bottom ,wherein the trenches are filled with a dielectric material.
Huang does teach the trenches (816, fig 8) [0031] include sidewalls (sidewalls of 816) that intersect along a line (a line from top to bottom, fig 8) forming a sharp trench bottom (bottom of 816, fig 8) and extend at straight taper from a top of trenches to the sharp trench bottom (816), wherein the trenches are filled with a dielectric material (816, SiO2, high -K dielectric) [0031].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Huang into the structure of Gan to include the trenches include sidewalls that intersect along a line forming a sharp trench bottom and extend at straight taper from a top of trenches to the sharp trench bottom ,wherein the trenches are filled with a dielectric material as claimed.
The ordinary artisan would have been motivated to modify Gan based on the teaching of Huang in the above manner for the purpose of to minimize the parasitic capacitance.
Furthermore, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d669, 149 USPQ 47 (CCPA1966).
Re claim 2 Gan in view Huang teach, the semiconductor device of claim 1, further
including a second trench (896, fig 8) [Gan, 0118] at least partially surrounding a perimeter of circuit (400, fig 8) [Gan, 0069] wherein sidewalls of the second trench (sidewalls of 896, fig 8) [Gan, 0118] do not intersect. (see fig 8).
Re claim 3 Gan in view Huang teach, the semiconductor device of claim 2, wherein a depth of the number of isolation trenches (894, fig8) [Gan, 0116] is less than a depth of the second trench (896, fig 8) [Gan, 0121].
Re claim 5 Gan in view of Huang teach, the semiconductor device of claim 1,
wherein the circuit (400, fig 8) [Gan, 0067] coupled to the memory array (500, fig 8) [Gan, 0093 is formed in a first wafer (568, fig 8) [Gan 0103] and wherein the first wafer (568, fig 8) [Gan, 0103] is coupled to a second wafer (468, fig 8) [Gan, 0084] in a stacked arrangement (see fig 8).
Re claim 7 Gan in view of Hung teach, the semiconductor device of claim 1,
wherein the circuit (400, fig 8) [Gan, 0067] is formed on pitch (see fig 8) with the memory array (500, fig 8) [Gan 0093].
Re claim 8 Gan in view of Huang teaches, the semiconductor memory device of claim 1,
Gan does not teach the number of isolation trenches have an aspect ratio of approximately 4 to 1.
Gan does teach "a top-to bottom ratio of top width to bottom width 894 can be between 1.5 microns and about 2.5 microns and a depth D can be range about 1 micron and about 6 microns" (fig 8) [0117].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Gan to include the number of isolation trenches have an aspect ratio of approximately 4 to 1 as claimed as claimed.
The ordinary artisan would have been motivated to modify Gan in the above manner for the purpose of improving electrical isolation of the device [0070].
Re claim 9 Gan teaches, the semiconductor memory device comprising:
a memory array (500, fig 8) [0094] formed in a semiconductor substrate (530, fig 8); a peripheral circuitry (400, fig 8) [0067] configured for memory operations including an erase operation [0057], the peripheral circuitry having rows and columns (fig 1) [0057]; and a number of isolation trenches (894 fig 8) [116] between columns in the peripheral circuitry (400, fig 8), wherein the number isolation trenches (894, fig 8) [0116].
Gan does not teach the trenches include tapered sidewalls that intersect along a line forming a sharp trench bottom and extend at straight taper from a top of the trenches to the sharp trench bottom, wherein the number of trenches are filed with a dielectric material.
Huang teaches the trenches (816, fig 8) [0031] include tapered sidewalls that intersect along a line forming a sharp trench bottom (bottom of 816) and extend at straight taper from a top of the trenches to the sharp trench bottom, wherein the number of trenches (816, fig 8) [0031] are filed with a dielectric material [0031].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Huang into the structure of Gan to include the trenches include tapered sidewalls that intersect along a line forming a sharp trench bottom and extend at straight taper from a top of the trenches to the sharp trench bottom, wherein the number of trenches are filed with a dielectric material as claimed.
The ordinary artisan would have been motivated to modify Gan based on the teaching of Huang in the above manner for the purpose of to minimize the parasitic capacitance.
Furthermore, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d669, 149 USPQ 47 (CCPA1966).
Re claim 12 Gan in view of Huang teach, the semiconductor memory device of claim 9, wherein the number of isolation trenches (894, fig 8) [Gan, 116] are on pitch (same vertical level) with the memory array (500, fig 8).
Re claim 13 Gan in view of Huang teach, the semiconductor memory device of claim 9, wherein the memory array (500, fig 8) [Gan, 0054] includes a NAND memory array [0055].
Re claim 14 Gan in view of Huang teach, the semiconductor memory device of claim 9, wherein the memory array includes vertical NAND memory strings [Gan, 0054, 0055].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Gan modified by Huang as applied to claims 1 and 3 further in view of Morita et al (US5473186A).
Re claim 4 Gan in view of Huang teaches, the semiconductor device of claim 3,
further including a third trench, wherein a depth of the number of isolation trenches is between the depth of the second and a depth of the third trench.
Morita teaches, a depth of the number of isolation trenches (342, fig3) [para 25] is between the depth of the second (341, fig 3) [para 25] and a depth of the third trench (343, fig 3) [para 25].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Morita into the structure of Gan and Huang to include a depth of the number of isolation trenches is between the depth of the second and a depth of the third trench as claimed.
The ordinary artisan would have been motivated to modify Morita based on the teaching of Gan and Huang in the above manner for the purpose to obtain semiconductor device with high substrate strength. [para 71].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gan modified by Huang as applied as applied to claims 1 and 5, further in view of Lin et al (US 20190172857A1).
Re claim 6 Gan in view of Huang teaches, the semiconductor memory device of claim 5,
Gan and Huang do not teach a through etch isolation at least partially surrounding a perimeter of circuit in the first wafer.
Lin does teach a through etch isolation (1310-2, fig 3) [0020] at least partially surrounding a perimeter of circuit (120, fig 3) [0020] in the first wafer (130, fig. 1) [0025].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lin into the structure of Gan and Huang to include a through etch isolation at least partially surrounding a perimeter of circuit in the first wafer as claimed.
The ordinary artisan would have been motivated to modify Gan and Huang based on the teaching of Lin in the above manner for the purpose of preventing current leakage between adjacent semiconductor components [0004].
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Gan modified by Huang as applied to claim 9, further in view of Kim et al (US 20200105348A1).
Re claim 10 Gan in view of Huang teaches, the semiconductor memory device of claim 9,
Gan and Huang do not teach the peripheral circuitry includes a row coupled to a source plate. Kim does teach the peripheral circuitry (140, fig 1) [0027] includes a row (RL, fig [0029] coupled to a source plate (11, fig 1) [0041].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kim into the structure of Gan and Huang to include the peripheral circuitry includes a row coupled to a source plate as claimed.
The ordinary artisan would have been motivated to modify Gan and Huang based on the teaching of Kim n the above manner for the purpose of improving power and signal transfer characteristic [0038].
Re claim 11 Gan in view of Huang teach, the semiconductor memory device of claim 10.
Gan and Huang do not teach the peripheral circuitry includes a row (RL, fig 1-3) coupled to data lines in the memory array.
Kim teaches, the peripheral circuitry (140, fig 1-3) [0027-0029] includes a row coupled (RL, fig 1-3) [0027-0029] to data lines in the memory array (110, fig 1-3) [0030].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kim into the structure of Gan and to include the peripheral circuitry includes a row coupled to data lines in the memory array as claimed.
The ordinary artisan would have been motivated to modify Gan and Huang based on the teaching of Kim in the above for the purpose of improving power and signal transfer characteristic [0038].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Gan modified by Huang as applied to claim 9, further in view of Smith et al (US20090278227A1).
Re claim 15 Gan in view of Huang teaches, the semiconductor memory device of claim 9,
Gan and Huang do not tech the peripheral circuitry operated at 3.5 volts or less. Smith does teach the peripheral circuitry operated at 3.5 volts or less. (1.8 -3.8 volts) [0021].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by smith into the structure of Gan and Huang to include the peripheral circuitry operated at 3.5 volts or less as claimed.
The ordinary artisan would have been motivated to modify Gan and Huang based on the teaching of Smith in the above manner for the purpose for preventing the unwanted electrical coupling between adjacent components and devices.
Response to argument
Applicant’s arguments with respect to claims 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 6/9/26
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