DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-25 are pending in the application. No claims have been amended. No claims have been canceled. Claims 11-20 have been withdrawn per the 12/17/25 restriction election (see below).
Election/Restrictions
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/17/25.
Specification
The use of terms including, but not limited to, GPS, Wi-Fi, LTE, etc., which is a trade name or a mark used in commerce, has been noted in this application. The term should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks. Examiner notes that the improper use of trade names or marks appears to only be located in paragraphs [0089 and 0090], but Examiner encourages Applicant to read through the specification in case there are other instances.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first substrate" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the phrase “the first substrate” will be interpreted to mean “the substrate”. Claims 2-10 are also rejected for being indefinite as they are dependent on rejected claim 1.
The term “approximately” in claims 2, is a relative term which renders the claim indefinite. The term “approximately” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear how the word “approximately” affects the tolerance level of the upper bound of 2µm in the above claims, if at all. No tolerance has been defined in the specification, so those skill in the art would be unsure if the upper bound is an exact boundary. For the purposes of examination, claims 2, 23, and 25 will each be interpreted to read “wherein the traces have a thickness of 2µm or less, and wherein the traces have a spacing of 2µm or less”.
The term “approximately” in claim 10 is a relative term which renders the claim indefinite. The term “approximately” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear how the word “approximately” affects the tolerance level of the upper bound of 50µm and the upper bound of 1,000µm in the above claims, if at all. No tolerance has been defined in the specification, so those skill in the art would be unsure if the bounds are an exact boundary. For the purposes of examination, claim 10 will each be interpreted to read “wherein the substrate has a thickness that is between 50µm and 1,000 µm”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 5-7, 9-10, 21-22, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 2011/0254160 A1, hereafter Tsai) in view of Rho et al. (US 2023/0307304 A1, hereafter Rho).
Regarding claim 1, Fig. 1K of Tsai teaches an electronic package, comprising:
a substrate (10, referenced in Fig. 1J, [0013]);
buildup layers (12, referenced in Fig. 1E, [0013]) over the first substrate (10) (over the bottom surface of the substrate);
a first die (22, see annotated Fig. 1K, [0017]) over the buildup layers (12) (over the bottom surface of the buildup layers);
a second die (22, see annotated Fig. 1K) over the buildup layers (12) (over the bottom surface) and adjacent to the first die, and wherein conductive routing (14/16, [0015]) in the buildup layers (12) electrically couples the first die (22) to the second die (22). While not explicitly shown in Fig. 1K, Tsai describes that die 40 may be electrically coupled to more than one of the dies 22 [0022], meaning the first and second dies 22 are electrically coupled to one another through layer 12.
Examiner's note: as applicant has not indicated a frame of reference to what "over" means, the word is being interpreted under BRI to be synonymous with the word "covers" along with Examiner indicated location.
Tsai fails to teach the substrate to comprise glass, and teaches the substrate of being formed of silicon carbide [0013]. However Rho teaches a similar packaging substrate in which glass is used. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Tsai to include a glass substrate as taught by Rho in order to have a packaging substrate that can be thinner and help to improve electrical properties of a semiconductor device [0052].
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Regarding claim 5, Tsai in view of Rho teach the electronic package of claim 1. Fig. 1K of Tsai further teaches:
a third die (40, [0022]) on an opposite surface of the substrate (10, referenced in Fig. 1J, [0013]) from the first die (22, see annotated Fig. 1K, [0017]) and the second die (22, see annotated Fig. 1K).
Regarding claim 6, Tsai in view of Rho teach the electronic package of claim 5. Fig. 1K of Tsai further teaches: wherein the third die (40, [0022]) is a memory die [0022].
Regarding claim 7, Tsai in view of Rho teach the electronic package of claim 5. Rho further teaches in Fig. 2 wherein through glass vias (TGVs) (23, [0063]) are provided through the substrate (10 of Tsai, [0013], 21 of Rho, [0063]).
Regarding claim 9, Tsai in view of Rho teach the electronic package of claim 1. Fig. 1K of Tsai further teaches: wherein the first die (22, see annotated Fig. 1k, [0017]) and the second die (22, see annotated Fig. 1K, [0017]) are compute dies (described as logic dies in [0022]).
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Regarding claim 10, Tsai in view of Rho teach the electronic package of claim 1. Tsai is silent on the thickness of the substrate; however, Rho says the substrate can have a thickness of 350µm to 700µm [0083], within the range of 50µm and 1,000µm necessitated by the current claim 10.
Regarding claim 21, Fig. 1K of Tsai teaches an electronic package, comprising:
a core (10, referenced in Fig. 1J, [0013]) with a first surface (see annotated Fig. 1K and a second surface opposite (see annotated Fig. 1K) from the first surface,
a first die (22, see annotated Fig. 1K, [0017]) and a second die (22, see annotated Fig. 1K, [0017]) attached to the core over the first surface; and
a third die (40, [0022]) attached to the core (10) over the second surface.
Tsai fails to teach wherein the core comprises glass and through glass vias (TGVs) through the core. Tsai teaches the substrate of being formed of silicon carbide with TSVs [0013]. However Rho teaches a similar packaging substrate in which glass is used. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Tsai to include a glass substrate as taught by Rho in order to have a packaging substrate that can be thinner and help to improve electrical properties of a semiconductor device [0052].
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Regarding claim 22, Tsai in view of Rho teach the electronic package of claim 21. Fig. 1K of Tsai further teaches:
buildup layers (12, referenced in Fig. 1E, [0013]) between the core (10, referenced in Fig. 1J, [0013]) and the first die (22, see annotated Fig. 1K, [0017]) and the second die (22, see annotated Fig. 1K, [0017]), wherein the buildup layers (12) comprise conductive routing (14/16, [0015]) to electrically couple the first die (22) to the second die (22). While not explicitly shown in Fig. 1K, Tsai describes that die 40 may be electrically coupled to more than one of the dies 22 [0022], meaning the first and second dies 22 are electrically coupled to one another through layer 12.
Claim(s) 2 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Rho, and further in view of Wu et al. (US 2021/0366877 A1, hereafter Wu).
Regarding claim 2, Tsai in view of Rho teach the electronic package of claim 1. Tsai in view of Rho are silent on the conductive routing includes traces with a line thickness of 2µm or less and a line spacing of 2µm or less. However, one of ordinary skill in the art would know to utilize trace line thicknesses and spacing known in the art before the effective filing date.
Wu teaches a similar buildup layer to Tsai in Fig. 18, in which the buildup layer (redistribution structure, 408, [0057]) includes metallization patterns (traces) with thicknesses and line spacings of less than 2µm. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to build the conductive routing in Tsai in view of Rho to the spacing and thickness specifications of Wu in order to improve the power integrity of the package structure, as Wu teaches in [0057].
Regarding claim 23, Tsai in view of Rho teach the electronic package of claim 22. Tsai in view of Rho are silent on the conductive routing includes traces with a line thickness of 2µm or less and a line spacing of 2µm or less. However, one of ordinary skill in the art would know to utilize trace line thicknesses and spacing known in the art before the effective filing date.
Wu teaches a similar buildup layer to Tsai in Fig. 18, in which the buildup layer (redistribution structure, 408, [0057]) includes metallization patterns (traces) with thicknesses and line spacings of less than 2µm. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to build the conductive routing in Tsai in view of Rho to the spacing and thickness specifications of Wu in order to improve the power integrity of the package structure, as Wu teaches in [0057].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Rho as applied to claim 1 above, and further in view of Sharon et al. (US 2022/0180940 A1, hereafter Sharon).
Regarding claim 3, Tsai in view of Rho teach the electronic package of claim 1. Tsai in view of Rho are silent on the first die and the second die comprise through silicon vias (TSVs). However, Tsai describes the first and second dies 22 as a plurality of different types of dies, and is silent on the die structure.
Sharon teaches in Fig. 4b, dies 302 and 304 ([0066]) to have TSVs 412 and 414 ([0069]) through them to be used to route signals through the dies [0069]. While these dies are stacked, one of ordinary skill in the art would know to use the vias of Sharon for the same purpose of routing signals through the dies in Tsai in view of Rho. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dies of Tsai in view of Rho to be dies including TSVs for signal routing within the device.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Rho and in further view of Sharon as applied to claim 3 above, and further in view of Sobieski et al. (US 10,692,847 B2, hereafter Sobieski).
Regarding claim 4, Tsai in view of Rho and in further view of Sharon teach the electronic package of claim 3. Tsai in view of Rho and in further view of Sharon fail to teach second buildup layers over the first die and the second die, wherein the TSVs are coupled to pads on a surface of the second buildup layers.
However, Fig. 2 of Sobieski teaches an interposer similar to the buildup layers in Tsai in view of Rho and in further view of Sharon which includes a first buildup layer (inorganic interposer, 204, column 3, line 14) and a second buildup layer (buildup layer substrate, 206, column 3, line 21) are over the bottom surface of first and second dies (202A and 202B, column 3, line 15). These two buildup layers utilized to create electrical coupling between dies (202A and 202B) and pads (see annotated Fig. 2) on the surface of the second buildup layers (206). While the reference elements in Fig. 2 are not explicitly described as being pads, they are in layer 208, which is there to facilitate electrical connections to a circuit board (column 3, lines 29-30), and thus would be known in the art as pads, or specifically contact pads. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tsai in view of Rho and in further view of Sharon to include a second buildup layer over the first and second dies in order to connect a higher density circuitry to a lower density circuitry, as Sobieski teaches in column 3 lines 25-32.
Examiner’s note, here the second buildup layers are over the bottom side of the first and second dies. As there is no distinct physical relationship claimed between the first and second dies and the second buildup layers, under BRI the second buildup layers are not required to be in direct physical contact with the dies. Similarly, the location of the second buildup layers just needs to be taken in reference to the dies themselves, as opposed to a specific side of the first and second dies. Thus the addition of the buildup layers as depicted in Sobieski reads on the current claim 4.
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Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Rho as applied to claim 1 above, and further in view of Liu et al. (US 2023/0063304 A1, hereafter Liu).
Regarding claim 8, Tsai in view of Rho teach the electronic package of claim 1. Tsai in view of Rho are silent a mold layer is provided around the first die and the second die.
However, Liu teaches a package in Fig. 1M in which a mold layer (EMC die frame, 760, [0067]) is formed around semiconductor dies (701, 702, and 703, [0067]). Liu states the molding (760) can be formed similarly to cavity filling material 52 ([0049]) in [0067]. This filling material is used to prevent die drift [0050]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Tsai in view of Rho to include the die frame of Liu in order to create a mold layer for preventing die shift within the device.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Rho and in further view of Liu.
Regarding claim 24, Fig. 1K of Tsai teaches an electronic system, comprising:
an electronic package, wherein the electronic package comprises:
a core (10, referenced in Fig. 1J, [0013]) with a first surface (see annotated Fig. 1K) and a second surface (see annotated Fig. 1K) opposite from the first surface;
buildup layers (12, referenced in Fig. 1E, [0013]) over the first surface of the core (10), wherein the buildup layers (12) comprise traces (14/16, [0015]);
a first die (22, see annotated Fig. 1K, [0017]) and a second die (22, see annotated Fig. 1K, [0017]) attached to the traces (14/16), wherein the traces (14/16) electrically couple the first die (22) to the second die (222) (While not explicitly shown in Fig. 1K, Tsai describes that die 40 may be electrically coupled to more than one of the dies 22 [0022], meaning the first and second dies 22 are electrically coupled to one another through layer 12.); and
a third die (40, [0022]) attached to the core over the second surface.
Tsai fails to teach wherein the core comprises glass and through glass vias (TGVs) through the core. Tsai teaches the substrate of being formed of silicon carbide with TSVs [0013]. However Rho teaches a similar packaging substrate in which glass is used. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Tsai to include a glass substrate as taught by Rho in order to have a packaging substrate that can be thinner and help to improve electrical properties of a semiconductor device [0052].
Tsai in view of Rho are silent on the electronic package being coupled to a board. However, in Fig. 1N, Liu teaches a similar electronic package to Tsai in view of Rho in which a package is coupled to a board (110, [0079]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Tsai in view of Rho to include a board as taught by Liu in order to get the expected result of a complete system where the dies have circuitry to electrically communicate with ([0001] of Liu).
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Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Rho and in further view of Liu as applied to claim 24 above, and further in view of Wu.
Regarding claim 25, Tsai in view of Rho and in further view of Liu teach the electronic package of claim 24. Tsai in view of Rho and in further view of Liu are silent on the conductive routing includes traces with a line thickness of 2µm or less and a line spacing of 2µm or less. However, one of ordinary skill in the art would know to utilize trace line thicknesses and spacing known in the art before the effective filing date.
Wu teaches a similar buildup layer to Tsai in Fig. 18, in which the buildup layer (redistribution structure, 408, [0057]) includes metallization patterns (traces) with thicknesses and line spacings of less than 2µm. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to build the conductive routing in Tsai in view of Rho to the spacing and thickness specifications of Wu in order to improve the power integrity of the package structure, as Wu teaches in [0057].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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