DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 25, 2026 has been entered.
Status of the Claims
Species 1, as shown in FIG. 1, was elected.
Amendment filed February 25, 2026 is acknowledged. New claim 14 has been added. Claims 2, 5-6 and 13 have been cancelled. Claim 1 has been amended. Non-elected Species, Claims 8-11 have been withdrawn from consideration. Claims 1, 3-4, 7-12 and 14 are pending.
Action on merits of claims 1, 3-4, 7, 12 and 14 follows.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3, 7, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over SAITO et al. (US. Pub. No. 2009/0101974) in view of KOIKE et al. (JP. Pub. No. H08167714 A) of record.
With respect to claim 1, SAITO teaches a semiconductor device substantially as claimed including:
a first semiconductor layer (2) of a first conductivity type, the first semiconductor layer (2) including an active region (DR) and a termination region (TR), the termination region surrounding the active region;
a first electrode (9) electrically connected to the first semiconductor layer (2);
a second electrode (8) electrically connected to the first semiconductor layer (2), the first semiconductor layer (2) being provided between the first electrode (9) and the second electrode (8), the second electrode (8) being provided on the active region (DR);
a second semiconductor layer (4) of a second conductivity type, the second semiconductor layer being provided between the first semiconductor layer (2) and the second electrode (8), the second semiconductor layer having a first layer thickness in a first direction (x) directed from the first electrode (9) toward the second electrode (8);
a third semiconductor layer (A) of the second conductivity type, the third semiconductor layer being provided in the termination region (TR) and surrounding the second semiconductor layer (4), the third semiconductor layer (A) being connected to the second semiconductor layer (4), the third semiconductor layer (A) having a second layer thickness in the first direction (x);
a fourth semiconductor layer (B) of the second conductivity type, the fourth semiconductor layer (B) being provided in the termination region (TR) and surrounding the second semiconductor layer (4) and the third semiconductor layer (A), the fourth semiconductor layer (B) being connected to the third semiconductor layer (A), the fourth semiconductor layer (38B) having a third layer thickness in the first direction (x); and
a fifth semiconductor layer (10) of the second conductivity type, the fifth semiconductor layer being connected to the second semiconductor layer (4),
the third semiconductor layer (A) and the fourth semiconductor layer (B) being provided between the first semiconductor layer (2) and the fifth semiconductor layer (10) in the first direction (x),
a first sum of a fourth layer thickness of the fifth semiconductor layer (10) in the first direction (x) and the second layer thickness being greater than the first layer thickness,
a second sum of the fourth layer thickness and third layer thickness,
a first part of the first semiconductor layer (2) being provided between the second semiconductor layer (4) and the third semiconductor layer (A) in a second direction (y) orthogonal to the first direction (x),
the first part of the first semiconductor layer (2) being in direct contact with the second semiconductor layer (4) and the third semiconductor layer (A), and
a second part of the first semiconductor layer (2) being provided between the third semiconductor layer (A) and the fourth semiconductor layer (B) in the second direction (y) orthogonal to the first direction (x). (See FIG. 1).
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Thus, SAITO is shown to teach all the features of the claim with the exception of explicitly disclosing the second sum of the fourth layer thickness and third layer thickness being less than the first sum.
However, KOIKE teaches a semiconductor device including:
a second semiconductor layer (3A) of a second conductivity type, the second semiconductor layer being provided between the first semiconductor layer (2) and the second electrode (9), the second semiconductor layer having a first layer thickness in a first direction (vertical) directed from the first electrode (not shown) toward the second electrode (9);
a third semiconductor layer (3B) of the second conductivity type, the third semiconductor layer being provided in the termination region and surrounding the second semiconductor layer (3A), the third semiconductor layer (3B) having a second layer thickness in the first direction;
a fourth semiconductor layer (3C) of second conductivity type, the fourth semiconductor layer (3C) being provided in termination region and surrounding second semiconductor layer (3A) and the third semiconductor layer (3B), the fourth semiconductor layer (3C) having a third layer thickness in the first direction,
wherein the second layer thickness being greater than that of the third layer thickness. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of SAITO having the second layer thickness in the first direction being greater than the third layer thickness as taught by KOIKE to increase the breakdown voltage.
In view of KOIKE, the second layer thickness being greater than the third layer thickness, thus, the second sum of the fourth layer thickness and third layer thickness of SAITO, being less than the first sum.
With respect to claim 3, the second electrode (8) of SAITO or (9) of KOIKE is electrically connected to the second semiconductor layer (4).
With respect to claim 7, in view of KOIKE, the first layer thickness of the second semiconductor layer (3A) is same as the third layer thickness of the fourth semiconductor layer (3C).
With respect to claim 12, the semiconductor device of SAITO further comprises:
a sixth semiconductor layer (1) provided between the first semiconductor layer (2) and the first electrode (9), the sixth semiconductor layer (1) including a first-conductivity-type impurity with a concentration (n+) higher than a concentration (n) of the first-conductivity-type impurity in the first semiconductor layer (2), the first electrode (9) being electrically connected to the first semiconductor layer (2) via the sixth semiconductor layer (1).
With respect to claim 14, the first part and the second part of SAITO are in direct contact with the fifth semiconductor layer (10).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over SAITO ‘974 and KOIKE ‘714 as applied to claim 3 above, and further in view of FRIEDRICHS et al. (US. Patent No. 6,936,850) of record.
SAITO, in view of KOIKE, teaches the semiconductor device as described in claim 3 above including: the second electrode (8) is electrically connected to the second semiconductor layer (4) with an Ohmic junction.
Thus, SAITO and KOIKE are shown to teach all the features of the claim with the exception of explicitly disclosing the second electrode being connected to the first semiconductor layer.
However, FRIEDRICHS teaches a semiconductor device including: a second electrode (100) being connected to first semiconductor layer (11) with a Schottky junction, and is connected to the second semiconductor layer (201) with an Ohmic junction. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of SAITO, in view of KOIKE, having the second electrode connecting to the first and second semiconductor layer as taught by FRIEDRICHS to provide for Schottky diode and Ohmic diode so that breakdown voltage and blocking capacity is increased.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ANH D MAI/ Primary Examiner, Art Unit 2893