DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-17) in the reply filed on 12/05/2025 is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/05/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 7, 9-12, 14, and 17 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chang (US 2021/0375761).
Regarding claim 1, Chang discloses a semiconductor device, comprising: n-channel field-effect transistors (NFETs) and p-channel field-effect transistors (PFETs) (Fig.1) adjacent to one another on a frontside of a wafer (50)) ([0019]) ; power rails (Fig.29A, numeral 135P ([0095]), connected to source/drain regions of the NFETs (92D) and the PFETs (92A) ([0097]), present on a backside of the wafer in a space (96) between adjacent NFETs and in a space between adjacent PFETs; and a signal line (135S), connected to a gate of the NFETs and the PFETs ([0095]; Fig.31D, numeral 102); [0107]), present on the backside of the wafer in a space between an adjacent NFET and PFET ([0108]).
Regarding claim 2, Chang discloses a signal line contact (Fig.31D, numeral 164) connecting the gate (102) to the signal line (135S).
Regarding claim 4, Chang discloses wherein the gate (102) and the signal line contact (164) comprise a same combination of materials ([0060]; [0088]).
Regarding claim 7, Chang discloses source/drain region power vias (Fig.29B; numeral 130) connecting the source/drain regions (92D) to the power rails (135P).
Regarding claim 9, Chang discloses wherein the power rails (135P) and the signal line (135S) are parallel to one another on the backside of the wafer (Fig.29B).
Regarding claim 10, Chang discloses wherein the NFETs are adjacent to one another on the frontside of the wafer, wherein the PFETs are adjacent to one another on the frontside of the wafer, and wherein a pair of the NFETs is adjacent to a pair of the PFETs on the frontside of the wafer (Fig.1; [0015]; [0019]).
Regarding claim 11, Chang discloses a semiconductor device, comprising: n-channel field-effect transistors (NFETs) and p-channel field-effect transistors (PFETs) (Fig.1; [0015]) adjacent to one another on a frontside of a wafer (50), wherein the NFETs and the PFETs each includes a stack of active layers interconnecting source/drain regions, (92) and gates (102) surrounding at least a portion of each of the active layers in a gate-all-around configuration (Fig.1); power rails (Fig.29, numeral 135P) , connected to the source/drain regions (92A); (92D), present on a backside of the wafer in a space between adjacent NFETs and in a space between adjacent PFETs ([0094]); and a signal line (135S), connected to a given one of the gates (102), present on the backside of the wafer in a space between an adjacent NFET and PFET (Fig.31D; [0108]).
Regarding claim 12, Chang discloses further comprising: a signal line contact (Fig.31D; numeral 164) connecting the given gate (102) to the signal line (135S).
Regarding claim 14, Chang discloses wherein the gates (102) and the signal line contact (164) comprise a same combination of materials ([0060]; [0088]).
Regarding claim 17, Chang discloses source/drain region power vias (Figs.29A, B; numeral 130) connecting the source/drain regions (92A); (92D) to the power rails 135P).
Allowable Subject Matter
Claims 3, 5, 6, 8, 13, 15, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest that the gate and the signal line contact share common sidewalls as required by claims 2 and 13.
The search of the prior art does not disclose or reasonably suggest that the gate and the signal line contact each comprises: a gate dielectric; at least one workfunction-setting metal disposed on the gate dielectric; and a fill metal disposed on the at least one workfunction-setting metal as required by claims 5 and 15.
The search of the prior art does not disclose or reasonably suggest wherein one or more of the source/drain region powers vias comprise: a second region present alongside the source/drain regions as required by claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891