Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) #1-3 are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Moslehi (U.S. Pat. No, 10,181,541), hereinafter referred to as "Moslehi".
Moslehi shows, with respect to claim #1, an integrated circuit structure, comprising: a front-side (fig. #17, item 20) (column 56, line 61-67, column 57, line 1-8) structure comprising a device layer (fig. #17, item 26) (column 18, line 61-67, column 19, line 1-14) comprising a first integrated circuit logic cell (column #22, line 27-38) separated from a second integrated circuit logic cell by a cell boundary (fig, #38 and fig. #44A, item 272 & 276) (column #37, line 27-38; column 56, line 61-67, column 57, line 1-8), and a metallization layer (fig. #17, item 24) immediately above the device layer (fig. #17, item 26) (column 18, line 61-67, column 19, line 1-14), wherein a track of the metallization layer (fig. #20, item 42) (column 19, line 1-67, column 20, line 1-39) is along the cell boundary (column 11, line17-26, column 13, line 27-39) from a plan view perspective; and a backside structure (fig. #18, item 34) below the device layer, wherein the backside structure provides power to the device layer (column #19, line 21-57).
Examiner notes that Moslehi fails to state explicitly that an integrated circuit structure comprising a first integrated circuit logic cell separated from a second integrated circuit logic cell by a cell boundary. However, Moslehi shows (column #22, line 27-38) components that include in the structure “integrated circuit logic”;
MPPT power optimizer; MPPT (Maximum Power Point Tracking) power optimizers contain integrated circuit (IC) logic. They are designed as smart, DC-to-DC converters that use active electronics to continuously monitor and adjust the power output of solar panels.
Moslehi discloses the claimed invention except for explicitly stating an integrated circuit logic cell. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use a MPPT to provide an integrated circuit logic, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Moslehi shows, with respect to claim #2, an integrated circuit structure wherein the backside structure (fig. #18, item 34) comprises a backside contact (fig. #18, item 32) (column #19, line 21-57).
Moslehi shows, with respect to claim #3, an integrated circuit structure wherein the backside structure comprises a backside via (column #15, line 12-33).
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Claim #4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moslehi (U.S. Pat. No, 10,181,541), hereinafter referred to as "Moslehi" as shown in the rejection of claim #1 above and in view of Huynh et al., (U.S. Pub. No. 2018/0174642), hereinafter referred to as "Huynh".
Moslehi substantially shows the claimed invention as shown in the rejection of claim #1 above.
Moslehi fails to show, with respect to claim #4, an integrated circuit structure wherein the device layer comprises a plurality of nanowire-based devices.
Huynh teaches, with respect to claim #4, an integrated circuit structure wherein the device layer comprises a plurality of nanowire-based devices (paragraph 0057-0058).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #4, to modified the invention of Moslehi as modified by the invention of Huynh, which teaches, an integrated circuit structure wherein the device layer comprises a plurality of nanowire-based devices, to incorporate a structural condition that reduces gate lengths, which can in turn enable, among other things, faster switching speeds while suffering comparatively less from detrimental impact of scaling, e.g., short channel effects, compared to planar devices, as taught by Huynh.
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Claim #5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moslehi (U.S. Pat. No, 10,181,541), hereinafter referred to as "Moslehi" as shown in the rejection of claim #1 above and in view of CHONG et al., (U.S. Pub. No. 2021/0050351), hereinafter referred to as "Chong".
Moslehi substantially shows the claimed invention as shown in the rejection of claim #1 above.
Moslehi fails to show, with respect to claim #5, an integrated circuit structure wherein the device layer comprises a plurality of fin-based devices.
Chong teaches, with respect to claim #5, an integrated circuit structure wherein the device layer comprises a plurality of fin-based devices (paragraph 0057-0058).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #5, to modified the invention of Moslehi as modified by the invention of Chong, which teaches, an integrated circuit structure wherein the device layer comprises a plurality of fin-based devices, to incorporate a structural condition that offers superior gate control, which dramatically reduces leakage current, boosts performance (speed/drive current), improves power efficiency (lower operating voltage), and enhances scalability, allowing smaller, more powerful chips with better heat management by controlling the channel from multiple sides, solving short-channel effects in modern ICs, as taught by Chong.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
05/01/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
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