DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 29, 2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0350976 A1 to Okumura (hereinafter “Okumura” – previously cited reference).
Regarding claim 1, Okumura discloses a semiconductor device comprising:
a semiconductor part including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, the second semiconductor layer being provided in the first semiconductor layer (semiconductor device comprising MISFET having n+ current spreading layer CSL 3 with a p+ embedded layer having a plurality of regions 5a-5c, 6a-6c disposed within CSL 3 as shown in Fig. 1A; paragraphs [0046]-[0047]),
the semiconductor part including a first interface of the first semiconductor layer and the second semiconductor layer at a bottom of the second semiconductor layer and a second interface of the first semiconductor layer and the second semiconductor layer at a side of the second semiconductor layer (CSL 3 and p+ embedded layer having first horizontal interface at a bottom of the p+ embedded layer and a second vertical interface as a side of the p+ embedded layer; Fig. 1A; paragraphs [0046]-[0047]),
the second semiconductor layer including a plurality of sub-layers stacked in a direction orthogonal to the first interface (p+ embedded layer having a plurality of having a plurality of regions 5a-5c, 6a-6c stacked in part vertically as shown in Fig. 1A; paragraphs [0046]-[0047]),
the second interface including interfaces of the plurality of sub-layers of the second semiconductor layer and the first semiconductor layer (second vertical interface includes interfaces of regions 5a-5c, 6a-6c with CSL 3 as shown in Fig. 1A; paragraphs [0046]-[0047]),
the second interface extending in a second direction inclined with respect to a first direction orthogonal to the first interface (second vertical interface of p+ embedded layer is in a direction at a tilt angle with respect to a vertical axis as shown in Fig. 1A; paragraphs [0046]-[0047]),
the plurality of sub-layers of the second semiconductor layer including a first sub-layer and a second sub-layer provided directly on an upper boundary of the first sub-layer, a portion of the upper boundary of the first sub-layer being noncontiguous with the first semiconductor layer (region 5b having an upper boundary in the form of a portion of an upper surface upon which region 6b is provided, where the portion of the upper surface of region 5b does not border CSL 3; Fig. 1A).
Okumura fails to disclose an entire upper boundary of the first sub-layer being noncontiguous with the first semiconductor layer.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Okumura in this manner given that the trapezoidal shape of the p+ base bottom embedded regions 5a-5c, 6a-6c of Okumura is due to the ion implantation beam being tilted, and a person of ordinary skill in the art would recognize that rectangular-shaped p+ base bottom embedded regions having vertical side edges (therefore having an entire upper boundary noncontiguous with CSL 3) could be created by simply adjusting the ion implantation beam angle which is achievable through routine process alternatives to create a slightly altered shape which is prima facie obvious under established precedent for mere alterations of shape as described in MPEP 2144.04(IV).
Regarding claim 2, Okumura discloses the device according to claim 1, wherein the second semiconductor layer has a concentration distribution in the first direction of a second-conductivity-type impurity, the concentration distribution including a concentration peak of the second-conductivity-type impurity in each sub-layer of the second semiconductor layer (p+ embedded layer having a plurality of regions 5a-5c, 6a-6c inherently has a concentration distribution with peaks; Fig. 1A; paragraphs [0046]-[0047]; claims 9 and 19).
Regarding claim 3, Okumura discloses the device according to claim 1, wherein the second interface is a plane including the second direction and a third direction orthogonal to the first direction and the second direction (second vertical interface includes a plane along a third Z-axis as shown in Fig. 1A; paragraphs [0046]-[0047]).
Regarding claim 4, Okumura discloses the device according to claim 1, wherein the semiconductor part is a hexagonal crystal structure, the first direction and the second direction are included in an M-plane of the hexagonal crystal, and an inclination angle of the second direction with respect to the first direction is equal to an inclination angle of the first interface with respect to a C-plane of the hexagonal crystal (MISFET may be hexagonal crystal structure where first and second interface directions may be in an M-plane of the structure and second interface direction is at an angle that may be in a C-plane of the structure; paragraphs [0057]-[0058], [0098]).
Regarding claim 5, Okumura discloses the device according to claim 1, wherein the semiconductor part is a hexagonal crystal structure, the first direction and the second direction being included in an M-plane of the hexagonal crystal, and an inclination angle of the second direction with respect to the first direction in the M-plane has a value obtained by adding 17 degrees to an inclination angle of the first interface with respect to a C-plane of the hexagonal crystal or by subtracting the inclination angle of the first interface from 17 degrees (MISFET may be hexagonal crystal structure where first and second interface directions may be in an M-plane of the structure capable of having an inclination angle calculated by adding 17 degrees to an inclination angle of a C-plane of the structure; paragraphs [0057]-[0058], [0061], [0069], [0098]).
Regarding claim 6, Okumura discloses the device according to claim 4, wherein the second semiconductor layer includes a plurality of pillar portions and a termination portion, the pillar portions each extending in a direction along the first interface, the pillar portions being arranged in a third direction orthogonal to the direction along the first interface and the second direction, the termination portion surrounding the plurality of pillar portions (p+ embedded layer has gate bottom protection regions 4a, 4b shaped as pillars extending horizontally and along a third Z-axis and points at which regions 4a, 4b terminate as shown in Fig. 1A; paragraphs [0046]-[0047], [0049]).
Regarding claim 7, Okumura discloses the device according to claim 6, wherein the termination portion of the second semiconductor layer includes the second interface orthogonal to the direction along the first interface, and the pillar portions of the second semiconductor layer each include another interface orthogonal to the first interface and the second interface (points at which regions 4a, 4b terminate includes second vertical interface and regions 4a, 4b have a Z-axis interface orthogonal to the first and second interfaces as shown in Fig. 1A; paragraphs [0046]-[0047], [0049]).
Regarding claim 8, Okumura discloses the device according to claim 1, wherein the second direction is parallel to a direction directed from a center point of the first interface toward a center point of a front surface of the second semiconductor layer, the front surface being on a side opposite to the first interface (second vertical interface is parallel to direction from center point of first horizontal interface to front surface of p+ embedded layer as shown in Fig. 1A; paragraphs [0046]-[0047]).
Regarding claim 13, Okumura discloses the device according to claim 1, further comprising: a gate electrode, the second semiconductor layer being located between the gate electrode and the first semiconductor layer in the direction orthogonal to the first interface (regions 4a, 4b of p+ embedded layer disposed between gate electrodes 11a, 11b and CSL 3 in a vertical direction orthogonal to the first horizontal interface; Fig. 1A; paragraph [0044]).
Response to Arguments
Applicant's arguments filed December 29, 2025 have been fully considered. Applicant submitted an amendment to claim 1, new claim 13 and associated arguments. Applicant argues that amended claim 1 (citing Examiner’s remarks in the Final Office Action of September 24, 2025) and new claim 13 are not disclosed by Okumura. Examiner agrees that amended claim 1 overcomes the previous 35 USC 102 rejection using Okumura. However, the entire ‘upper boundary’ of Okumura’s region 5b would be entirely noncontiguous with CSL 3 if regions 5b, 6b were shaped as rectangles rather than trapezoids. Mere alteration of shape from one common shape to another even more common shape for semiconductor regions would be obvious to utilize, particularly given the trapezoidal shape of the regions 5b, 6b is only present because of selected ion implantation beam tilt which can be easily altered to produce a functionally equivalent design using a simplified manufacturing process (e.g. no beam tilt). Additionally, new claim 13 is disclosed by Okumura given that p+ embedded regions 4a, 4b are disposed between gate electrodes 11a, 11b and CSL 3 in a vertical direction orthogonal to the first horizontal interface.
Conclusion
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818