Nals DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0350976 A1 to Okumura (hereinafter “Okumura” – previously cited reference).
Regarding claim 1, Okumura discloses a semiconductor device comprising:
a semiconductor part including a first semiconductor layer of a first conductivity type and a plurality of second semiconductor layers of a second conductivity type, each of the second semiconductor layer being provided in the first semiconductor layer (semiconductor device comprising MISFET having n+ current spreading layer CSL 3 with a p+ embedded layer having a plurality of regions 4a, 4b, 5b, 6b disposed within CSL 3 as shown in Fig. 1A; paragraphs [0046]-[0047]); and
a plurality of gate electrodes, with respect to each of the second semiconductor layers (gate electrodes 11a, 11b corresponding to regions 4a, 4b, 5b, 6b; Fig. 1A; paragraph [0044]),
the semiconductor part including a first interface of the first semiconductor layer and the second semiconductor layer at a bottom of the second semiconductor layer and a second interface of the first semiconductor layer and the second semiconductor layer at a side of the second semiconductor layer (CSL 3 and p+ embedded layer having first horizontal interface at a bottom of the p+ embedded layer and a second vertical interface as a side of the p+ embedded layer; Fig. 1A; paragraphs [0046]-[0047]),
the second semiconductor layer including a plurality of sub-layers stacked in a first direction orthogonal to the first interface (p+ embedded layer having a plurality of regions 4a, 4b, 5b, 6b stacked in part vertically as shown in Fig. 1A; paragraphs [0046]-[0047]),
the second interface including interfaces of the plurality of sub-layers of the second semiconductor layer and the first semiconductor layer (second vertical interface includes interfaces of regions 4a, 4b, 5b, 6b with CSL 3 as shown in Fig. 1A; paragraphs [0046]-[0047]),
the second interface extending in a second direction inclined with respect to the first direction orthogonal to the first interface (second vertical interface of p+ embedded layer is in a direction at a tilt angle with respect to a vertical axis as shown in Fig. 1A; paragraphs [0046]-[0047]),
the plurality of sub-layers of the second semiconductor layer including a first sub-layer and a second sub-layer provided directly on an upper boundary of the first sub-layer, a portion of the upper boundary of the first sub-layer being noncontiguous with the first semiconductor layer (region 5b having an upper boundary in the form of a portion of an upper surface upon which region 6b is provided, where the portion of the upper surface of region 5b does not border CSL 3; Fig. 1A),
some of the plurality of sub-layers of the second semiconductor layer being located between a corresponding one of the gate electrodes and the first semiconductor layer in the first direction orthogonal to the first interface (in the vertical direction, regions 4a, 4b located between gate electrodes 11a, 11b and CSL 3; Fig. 1A),
only the first semiconductor layer being provided between adjacent two of the second semiconductor layers in a third direction along the first interface (in the horizontal direction, only CSL 3 disposed between adjacent regions 4a, 4b, 5b, 6b; Fig. 1A).
Okumura fails to disclose an entire upper boundary of the first sub-layer being noncontiguous with the first semiconductor layer; and each of the plurality of sub-layers of the second semiconductor layer, including the first sub-layer and the second sub-layer, being located between a corresponding one of the gate electrodes and the first semiconductor layer in the first direction orthogonal to the first interface.
However, Okumura already discloses, in the vertical dimension, each of regions 4a, 4b, 5b, 6b being disposed between the lowest extent of the CSL 3 and the highest extent of the gate electrodes 11a, 11b (see Fig. 1A) which at least strongly suggests and arguably reads directly on the limitation at issue depending upon how “in the first direction orthogonal to the first interface” is interpreted with respect to the relative orientation claimed between the sublayers, gate electrodes, and first semiconductor layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Okumura in this manner given that the trapezoidal shape of the p+ base bottom embedded regions 5b, 6b of Okumura is due to the ion implantation beam being tilted, and a person of ordinary skill in the art would recognize that rectangular-shaped p+ base bottom embedded regions having vertical side edges (therefore having an entire upper boundary noncontiguous with CSL 3) could be created by simply adjusting the ion implantation beam angle which is achievable through routine process alternatives to create a slightly altered shape which is prima facie obvious under established precedent for mere alterations of shape as described in MPEP 2144.04(IV). Further, given that regions 4a, 4b of second semiconductor layer already read on the second limitation (and arguably regions 5b, 6b do as well), it would be a mere duplication of parts already disclosed (see MPEP 2144.04(VI)(B)) to provide regions 5b, 6b to be disposed laterally underneath electrodes 11a, 11b and above CSL 3 as regions 4a, 4b are and would further be obvious to do so in order to potentially provide enhanced electric field shielding of the gate oxide and improved control of avalanche current during reverse-bias/blocking conditions.
Regarding claim 2, Okumura discloses the device according to claim 1, wherein with respect to each of the second semiconductor layers, the second semiconductor layer has a concentration distribution in the first direction of a second-conductivity-type impurity, the concentration distribution including a concentration peak of the second-conductivity-type impurity in each sub-layer of the second semiconductor layer (p+ embedded layer having a plurality of regions 4a, 4b, 5b, 6b inherently has a concentration distribution with peaks; Fig. 1A; paragraphs [0046]-[0047]; claims 9 and 19).
Regarding claim 3, Okumura discloses the device according to claim 1, wherein the second interface is a plane including the second direction and a fourth direction orthogonal to the first direction and the second direction (second vertical interface includes a plane along a third Z-axis as shown in Fig. 1A; paragraphs [0046]-[0047]).
Regarding claim 4, Okumura discloses the device according to claim 1, wherein the semiconductor part is a hexagonal crystal structure, the first direction and the second direction are included in an M-plane of the hexagonal crystal, and an inclination angle of the second direction with respect to the first direction is equal to an inclination angle of the first interface with respect to a C-plane of the hexagonal crystal (MISFET may be hexagonal crystal structure where first and second interface directions may be in an M-plane of the structure and second interface direction is at an angle that may be in a C-plane of the structure; paragraphs [0057]-[0058], [0098]).
Regarding claim 5, Okumura discloses the device according to claim 1, wherein the semiconductor part is a hexagonal crystal structure, the first direction and the second direction being included in an M-plane of the hexagonal crystal, and an inclination angle of the second direction with respect to the first direction in the M-plane has a value obtained by adding 17 degrees to an inclination angle of the first interface with respect to a C-plane of the hexagonal crystal or by subtracting the inclination angle of the first interface from 17 degrees (MISFET may be hexagonal crystal structure where first and second interface directions may be in an M-plane of the structure capable of having an inclination angle calculated by adding 17 degrees to an inclination angle of a C-plane of the structure; paragraphs [0057]-[0058], [0061], [0069], [0098]).
Regarding claim 6, Okumura discloses the device according to claim 4, wherein the plurality of second semiconductor layers is formed with a layer including a plurality of pillar portions and a termination portion, the pillar portions each extending in a direction along the first interface, the pillar portions being arranged in a fourth direction, the termination portion surrounding the plurality of pillar portions (p+ embedded layer has gate bottom protection regions 4a, 4b shaped as pillars extending in a fourth direction in part along the horizontal and points at which regions 4a, 4b terminate therearound as shown in Fig. 1A; paragraphs [0046]-[0047], [0049]).
Regarding claim 7, Okumura discloses the device according to claim 6, wherein the termination portion includes an interface orthogonal to the direction along the first interface, and the pillar portions each include another interface orthogonal to the first interface and the second interface (points at which regions 4a, 4b terminate includes second vertical interface and regions 4a, 4b have a Z-axis interface orthogonal to the first and second interfaces as shown in Fig. 1A; paragraphs [0046]-[0047], [0049]).
Regarding claim 8, Okumura discloses the device according to claim 1, wherein the second direction is parallel to a direction directed from a center point of the first interface toward a center point of a front surface of the second semiconductor layer, the front surface being on a side opposite to the first interface (second vertical interface is parallel to direction from center point of first horizontal interface to front surface of p+ embedded layer as shown in Fig. 1A; paragraphs [0046]-[0047]).
Response to Arguments
Applicant's arguments filed May 26, 2026 have been fully considered. Applicant submitted substantive amendments to claim 1 and associated arguments. Examiner agrees with Applicant’s assertion that regions 5a-5c, 6a-6c are not disposed underneath gate electrodes and between the first semiconductor layer and the gate electrodes. Examiner does not agree that the regions 4a, 4b were mapped to the claimed second semiconductor layer. Rather, Examiner maintains that each of regions 4a-4b, 5a-5c, 6a-6c were mapped collectively to the second semiconductor layer. Given the amendments to claim 1, Examiner as altered the interpretation of Okumura such that the regions 4a-4b, 5b, and 6b are mapped to the second semiconductor layer which at least strongly suggests if not outright reads upon the amended limitation at issue of “each of the plurality of sub-layers of the second semiconductor layer, including the first sub-layer and the second sub-layer, being located between a corresponding one of the gate electrodes and the first semiconductor layer in the first direction orthogonal to the first interface” as outlined in the analysis above. Regardless, amended claim 1 remains obvious over Okumura. Finally, Applicant’s assertion that regions 4a, 4b serve a different functionality from regions 5b, 6b does not negate the fact that regions 4a, 4b are p+ embedded regions within CSL 3 all the same as regions 5b, 6b. Newly cited references US 2019/0181261 A1 to Okumura and US 2021/0376147 A1 to Chung et al. disclose related semiconductor sub-layer arrangements akin to that claimed in claim 1 and the associated dependent claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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