Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 7, 2025 has been entered.
Response to Arguments
In response to applicants’ amendments and arguments filed on 11/07/2025, the amendments made overcame the previous prior art rejection, but upon further search and consideration a new rejection is formulated below. It is recommended that the applicant include language of the shape of both rings, and possibly shapes relative to one another. Describing the shapes of the specific portion of the ring is helpful, but when only one shape is designated, it is fairly clear to incorporate a new teaching with said shape from another reference. When the shapes, distances, widths, are in relative size to one another, it is harder to find specific art. According to the drawings it is recommended to construct something like the following, “where the bottom ring has a t-shape with two widths, a first width and a second width where the first with is greater than the second, and the top ring has a cross-sectional shape distinct from and connected to the bottom ring such that the width of the top ring is less than the second first width of the bottom ring but greater than the width of the second width of the bottom ring.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 11-16 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al (US 20210050251 A1) in view of Sato et al (US 20230099856 A1) and in further view of Ding et al (US 20160093601 A1).
Regarding claims 1 and 11,
Hsiao et al teaches
[claim 1] a semiconductor device comprising: a first device; and a second device bonded to the first device (figure 7, paragraph 0014 and 0016, element PC1 and PC2 are the first and second devices respectively [they are called packaging containers but contain devices in them, specifically device wafers and a plurality of die regions] and are bonded together),
the first device comprising: a plurality of first metal pads provided above a semiconductor substrate, the semiconductor substrate having an approximately circular shape; a first circuit coupled to at least one of the plurality of the first metal pads (figure 7, element EC1 is provided on substrate PC1 and connected to the active regions [connected to the circuit]. Per figure 4, the induction coils [element 112] to act must be circular around an object in nature [laws of induction and magnetic field effects], and they surround the device [element 112 goes in and out of the page on either side of the semiconductor devices] implying the substrates must be a typical wafer shape which is circular in nature [if the induction coils were wrapped around a non-circular shape the magnetic field would be uneven within in the device region and would not work properly]);
the second device comprising: a plurality of second metal pads joined to the plurality of the first metal pads, respectively; a second circuit coupled to at least one of the plurality of the second metal pads (figure 7, paragraph 0016, element PC2 is electrically connected to element EC1 on a top side of it and bonded to the first metal pads directly),
[claim 11] a semiconductor device comprising: a first device; and a second device bonded to the first device (figure 7, paragraph 0014 and 0016, element PC1 and PC2 are the first and second devices respectively [they are called packaging containers but contain devices in them, specifically device wafers and a plurality of die regions] and are bonded together),
the first device comprising: a plurality of first chip regions, each of the first chip regions having a plurality of first metal pads and a first circuit coupled to at least one of the plurality of the first metal pads (figure 7, element EC1 is provided on substrate PC1 and connected to the active regions [connected to the circuit] which per paragraph 0016 can contain multiple IC’s and with multiple pads [EC1] each IC could have a plurality of pads attached),
the second device comprising: a plurality of second chip regions, each of the second chip regions having a plurality of second metal pads and a second circuit coupled to at least one of the plurality of the second metal pads, the second metal pads joined to the plurality of the first metal pads, respectively (figure 7, paragraph 0016, element PC2 is electrically connected to element EC1 on a top side of it and bonded to the first metal pads directly whereas per paragraph 0016 can contain multiple IC’s and with multiple pads [EC1] each IC could have a plurality of pads attached);
However, Hsiao et al does not specifically disclose
[claim 1] and a first metal ring provided along an outer circumference of the semiconductor substrate to surround the first circuit, and a second metal ring joined to the first metal ring,
wherein the distance from the semiconductor substrate to a bonding surface between the second metal ring and the first metal ring is the same as a distance from the semiconductor substrate to a bonding surface between the second metal pads and the first metal pads, wherein the first metal ring has a T-shaped cross-section such that a first portion of the first metal ring, in contact with the second metal ring, has a first width, and a second portion of the first metal ring has a second width, and wherein the first width is greater than the second width.
[claim 11] and a first metal ring provided along an outer circumference of a substrate to surround the plurality of the first chip regions,
and a second metal ring joined to the first metal ring, the first metal ring and the second metal ring, which are joined together, constitute a circumferential seal ring for the plurality of the first chip regions and the plurality of the second chip regions,
wherein a distance from the substrate to a bonding surface between the second metal ring and the first metal ring is the same as a distance form the substrate to a bonding surface between the second metal pads and the first metal pads, wherein the first metal ring has a T-shaped cross-section such that a first portion of the first metal ring, in contact with the second metal ring, has a first width, and a second portion of the first metal ring has a second width, and wherein the first width is greater than the second width.
However, Sato et al does teach
[claim 1] and a first metal ring provided along an outer circumference of the semiconductor substrate to surround the first circuit, and a second metal ring joined to the first metal ring (figure 4C, paragraphs 0079 and 0081, element 406 is the first and second metal ring since element 406 can either be front side or back side connected to each IC, and each IC is connected to this bonding element. When transposed onto figure 7 from Hsiao et al, it means that element 406 is present in the same plan as elements EC1 which are bonded together since element 406 is a guard ring made of metal that surrounds the IC and element EC1 is above the active region of each IC).
wherein the distance from the semiconductor substrate to a bonding surface between the second metal ring and the first metal ring is the same as a distance from the semiconductor substrate to a bonding surface between the second metal pads and the first metal pads (figure 4C, paragraphs 0079 and 0081, element 406 is the first and second metal ring since element 406 can either be front side or back side connected to each IC, and each IC is connected to this bonding element. When transposed onto figure 7 from Hsiao et al, it means that element 406 is present in the same plan as elements EC1, thus designating that the distance from the semiconductor substrate to each metal pad is the same distance from the semiconductor substrate to each metal ring).
[claim 11] and a first metal ring provided along an outer circumference of a substrate to surround the plurality of the first chip regions, and a second metal ring joined to the first metal ring, the first metal ring and the second metal ring, which are joined together, constitute a circumferential seal ring for the plurality of the first chip regions and the plurality of the second chip regions (figure 4C, paragraphs 0079 and 0081, element 406 is the first and second metal ring since element 406 can either be front side or back side connected to each IC, and each IC is connected to this bonding element. When transposed onto figure 7 from Hsiao et al, it means that element 406 is present in the same plan as elements EC1 which are bonded together since element 406 is a guard ring made of metal that surrounds the IC and element EC1 is above the active region of each IC),
wherein a distance from the substrate to a bonding surface between the second metal ring and the first metal ring is the same as a distance form the substrate to a bonding surface between the second metal pads and the first metal pads (figure 4C, paragraphs 0079 and 0081, element 406 is the first and second metal ring since element 406 can either be front side or back side connected to each IC, and each IC is connected to this bonding element. When transposed onto figure 7 from Hsiao et al, it means that element 406 is present in the same plan as elements EC1, thus designating that the distance from the semiconductor substrate to each metal pad is the same distance from the semiconductor substrate to each metal ring)
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Hsiao et al to incorporate the teachings of Sato et al in order to provide a more stable bonding junction between the two IC’s by providing a guard ring that surrounds the semiconductor IC’s (paragraphs 0004-0005 and 0081).
However, Hsiao et al as modified above does not specifically disclose
[claim 1] wherein the first metal ring has a T-shaped cross-section such that a first portion of the first metal ring, in contact with the second metal ring, has a first width, and a second portion of the first metal ring has a second width, and wherein the first width is greater than the second width.
[claim 11] wherein the first metal ring has a T-shaped cross-section such that a first portion of the first metal ring, in contact with the second metal ring, has a first width, and a second portion of the first metal ring has a second width, and wherein the first width is greater than the second width.
However, Ding et al does teach
[claim 1] wherein the first metal ring has a T-shaped cross-section such that a first portion of the first metal ring, in contact with the second metal ring, has a first width, and a second portion of the first metal ring has a second width, and wherein the first width is greater than the second width (figure 8, paragraph 0048, where element 306 and 302 comprise the first ring in contact with the second metal ring [elements 206 and 202] where it has a first width [width of element 306] and a second width [width of element 302] where the first width is greater than the second width).
[claim 11] wherein the first metal ring has a T-shaped cross-section such that a first portion of the first metal ring, in contact with the second metal ring, has a first width, and a second portion of the first metal ring has a second width, and wherein the first width is greater than the second width (figure 8, paragraph 0048, where element 306 and 302 comprise the first ring in contact with the second metal ring [elements 206 and 202] where it has a first width [width of element 306] and a second width [width of element 302] where the first width is greater than the second width).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Hsiao et al as modified to incorporate the teachings of Ding et al in order to maximize efficiency by using less material in creating a t-shape while maintaining conductivity and connection between the two substrates.
Regarding claims 2-9, 12-16, and 21
Additionally, Hsiao et al does not specifically disclose
[claim 2] the semiconductor device according to claim 1, wherein the second metal ring surrounds the second circuit.
[claim 3] the semiconductor device according to claim 1, wherein the first device includes a plurality of first chip regions, each of the first chip regions having the plurality of the first metal pads and the first circuit,
the second device includes a plurality of second chip regions, each of the second chip regions having the plurality of the second metal pads and the second circuit, the plurality of the first chip regions and the plurality of the second chip regions are bonded by the first metal pads and the second metal pads, the first metal ring corresponds to a single one of the substrate, the second metal ring corresponds to the first metal ring,
and the first metal ring and the second metal ring surround the plurality of the first chip regions and the plurality of the second chip regions.
[claim 4] the semiconductor device according to claim 1, wherein the first metal ring and the second metal ring constitute a circumferential seal ring.
[claim 5] the semiconductor device according to claim 1, wherein the first metal ring is provided at a position inwardly separated from the outer circumference of the semiconductor substrate.
[claim 6] the semiconductor device according to claim 1, wherein at least one of the first metal ring and the second metal ring has a structure of stacking a plurality of ring-shaped metal patterns in a direction crossing a substrate surface of the semiconductor substrate.
[claim 7] the semiconductor device according to claim 1, wherein the first device and the second device respectively have a first insulating layer part and a second insulating layer part at respective bonded surfaces of the first device and the second device, the first metal ring is embedded in a recess that is provided in the first insulating layer part, and the second metal ring is embedded in a recess that is provided in the second insulating layer part.
[claim 8] the semiconductor device according to claim 1, wherein the plurality of the first metal pads and the plurality of the second metal pads each contain copper.
[claim 9] the semiconductor device according to claim 1, wherein the first metal ring and the second metal ring each contain copper.
[claim 12] the semiconductor device according to claim 11, wherein the first metal ring is provided at a position inwardly separated from the outer circumference of the substrate.
[claim 13] the semiconductor device according to claim 11, wherein at least one of the first metal ring and the second metal ring has a structure of stacking a plurality of ring- shaped metal patterns in a direction crossing a substrate surface of the substrate.
[claim 14] the semiconductor device according to claim 11, wherein the first device and the second device respectively have a first insulating layer part and a second insulating layer part at respective bonded surfaces of the first device and the second device, the first metal ring is embedded in a recess that is provided in the first insulating layer part, and the second metal ring is embedded in a recess that is provided in the second insulating layer part.
[claim 15] the semiconductor device according to claim 11, wherein the plurality of the first metal pads and the plurality of the second metal pads each contain copper.
[claim 16] the semiconductor device according to claim 11, wherein the first metal ring and the second metal ring each contain copper.
[claim 21] the semiconductor device according to claim 1, wherein the first device includes a plurality of first chip regions, the first chip regions are to be diced, the second device includes a plurality of second chip regions, the second chip regions are to be diced, and the first metal ring and the second metal ring surround the plurality of the first chip regions and the plurality of the second chip regions.
However, Sato et al does teach
[claim 2] the semiconductor device according to claim 1, wherein the second metal ring surrounds the second circuit (figure 4C, paragraph 0079, element 412 corresponds to the arrays [element 320b or 320c] in figure 3B, and is conductive, goes around the second circuit [labeled active circuitry elements] as shown by a top down view of figure 4C, where the active circuit elements would be situated in the center above the metal ring)
[claim 3] the semiconductor device according to claim 1, wherein the first device includes a plurality of first chip regions, each of the first chip regions having the plurality of the first metal pads and the first circuit (figure 3B, element 302a comprise the first device, where the device can be split into multiple circuitry elements each having their unique set of metal pads designated as 312a and 312a’, where each region of the element 302a associated with the respective pads would be considered a chip region and have their own plurality of metal pads),
the second device includes a plurality of second chip regions, each of the second chip regions having the plurality of the second metal pads and the second circuit, the plurality of the first chip regions and the plurality of the second chip regions are bonded by the first metal pads and the second metal pads, the first metal ring corresponds to a single one of the substrate, the second metal ring corresponds to the first metal ring (figure 3B, elements 302b and 302c comprise the second device, where the device can be split into multiple circuitry elements each having their unique set of metal pads designated as 312b and 312c, where each region of the element 302b and 302c associated with the respective pads would be considered a chip region and have their own plurality of metal pads, and the first metal ring from figure 4A corresponds to surrounding one of the metal pads and the second metal ring is connected to the first metal ring to form a bond [per paragraphs 0079 and 0081]),
and the first metal ring and the second metal ring surround the plurality of the first chip regions and the plurality of the second chip regions (figure 4A, paragraph 0079, element 412 corresponds to the arrays [elements 320a, 320b and 320c] in figure 3B of their respective bonding layer 304a, 304b, and 304c. Each ring is conductive, goes around the respective active circuit regions of 302a, 302b, and 302c. Figure 4A is a top down view, so each element in figure 4A is present in each respective bonding layer 304a, 304b, and 304c, and element 412 the refers to the array elements 320a, 320b and 320c of each respective bonding layer).
[claim 4] the semiconductor device according to claim 1, wherein the first metal ring and the second metal ring constitute a circumferential seal ring (figure 4A, paragraph 0079, element 412 of each bonding layer [304a, 304b, and 304c] is circumferential and seals the device).
[claim 5] the semiconductor device according to claim 1, wherein the first metal ring is provided at a position inwardly separated from the outer circumference of the semiconductor substrate (figure 4A, element 412 of bonding layer 304a is inside the outer region of the semiconductor represented by the square of element 400a).
[claim 6] the semiconductor device according to claim 1, wherein at least one of the first metal ring and the second metal ring has a structure of stacking a plurality of ring-shaped metal patterns in a direction crossing a substrate surface of the semiconductor substrate (figures 3B and 4A, paragraph 0079, where the plurality of array elements each represented by elements 320a, 320b and 320c of each respective bonding layer 304a, 304b and 304c are all represented by the multiple elements 406, 412 and 410 of figure 4A, and are stacked across the surface of the substrate).
[claim 7] the semiconductor device according to claim 1, wherein the first device and the second device respectively have a first insulating layer part and a second insulating layer part at respective bonded surfaces of the first device and the second device, the first metal ring is embedded in a recess that is provided in the first insulating layer part, and the second metal ring is embedded in a recess that is provided in the second insulating layer part (paragraph 0073, figure 3B, elements 323a/b/c are all passivation layers, which is the same functionally and materially as an insulating layer, where the metal rings are embedded into the passivation layers as shown by elements 320a/b/c).
[claim 8] the semiconductor device according to claim 1, wherein the plurality of the first metal pads and the plurality of the second metal pads each contain copper (paragraphs 0005 and 0050, figures 1A and 3B where element 112 of figure 1A is the same as element 312a/b/c of figure 3B and can be made of copper according to paragraph 0005).
[claim 9] the semiconductor device according to claim 1, wherein the first metal ring and the second metal ring each contain copper (paragraph 0057, figures 1A and 3B where element 130 of figure 1A is associated with element 320a/b/c of figure 3B and is associated with element 412 of figure 4A [the metal rings on both devise], and can be made of copper).
[claim 12] the semiconductor device according to claim 11, wherein the first metal ring is provided at a position inwardly separated from the outer circumference of the substrate (figure 4A, element 412 of bonding layer 304a of figure 3B is inwardly separated from the outer circumference of the substrate of 400a)
[claim 13] the semiconductor device according to claim 11, wherein at least one of the first metal ring and the second metal ring has a structure of stacking a plurality of ring- shaped metal patterns in a direction crossing a substrate surface of the substrate (figures 3B and 4A, paragraph 0079, where the plurality of array elements each represented by elements 320a, 320b and 320c of each respective bonding layer 304a, 304b and 304c are all represented by the multiple elements 406, 412 and 410 of figure 4A, and are stacked across the surface of the substrate).
[claim 14] the semiconductor device according to claim 11, wherein the first device and the second device respectively have a first insulating layer part and a second insulating layer part at respective bonded surfaces of the first device and the second device, the first metal ring is embedded in a recess that is provided in the first insulating layer part, and the second metal ring is embedded in a recess that is provided in the second insulating layer part (figure 3B, paragraph 0074, where elements 323a/b/c are passivation layers, which is equivalent to an insulator, and the metal rings [element 412 in each bonding layer 304a, 304b and 304c] are embedded into the passivation layer and each passivation layer surface is bonded together such that the first and second device are bonded with passivation layer surfaces touching each other).
[claim 15] the semiconductor device according to claim 11, wherein the plurality of the first metal pads and the plurality of the second metal pads each contain copper (paragraphs 0005 and 0050, figures 1A and 3B where element 112 of figure 1A is the same as element 312a/b/c of figure 3B and can be made of copper according to paragraph 0005).
[claim 16] the semiconductor device according to claim 11, wherein the first metal ring and the second metal ring each contain copper (paragraph 0057, figures 1A and 3B where element 130 of figure 1A is associated with element 320a/b/c of figure 3B and is associated with element 406 of figure 4A [the metal rings on both devise], and can be made of copper).
[claim 21] the semiconductor device according to claim 1, wherein the first device includes a plurality of first chip regions, the first chip regions are to be diced, the second device includes a plurality of second chip regions, the second chip regions are to be diced, and the first metal ring and the second metal ring surround the plurality of the first chip regions and the plurality of the second chip regions (figure 4A, paragraph 0079, where the first and second chip regions [elements 302A and 304A] each can constitute a plurality of IC’s which can be diced, element 412 corresponds to the arrays [elements 320a, 320b and 320c] in figure 3B of their respective bonding layer 304a, 304b, and 304c. Each ring is conductive, goes around the respective active circuit regions of 302a, 302b, and 302c. Figure 4A is a top down view, so each element in figure 4A is present in each respective bonding layer 304a, 304b, and 304c, and element 412 the refers to the array elements 320a, 320b and 320c of each respective bonding layer).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Hsiao et al with the teachings of Sato el al in order to create a stronger, bonded device structure to maximize efficiency and minimize cost by creating seal rings surrounding IC’s and bonding the IC’s in a specific manner (paragraph 0004-0005).
Regarding claim 22,
Hsiao et al does not specifically disclose
[claim 22] The semiconductor device according to claim 1, wherein the first metal ring and the second metal ring are concentric with the semiconductor substrate, a diameter of the first metal ring is at least half a diameter of the semiconductor substrate, a diameter of the second metal ring is at least half a diameter of the semiconductor substrate.
However, Sato et al does teach
[claim 22] The semiconductor device according to claim 1, wherein the first metal ring and the second metal ring are concentric with the semiconductor substrate, a diameter of the first metal ring is at least half a diameter of the semiconductor substrate, a diameter of the second metal ring is at least half a diameter of the semiconductor substrate (figure 4A, paragraph 0079, element 412 of each bonding layer [304a, 304b, and 304c] is circumferential is concentric with the semiconductor substrate and seals the device).
However, per MPEP 2144 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Hsiao et al with the teachings of Sato et al to create concentric sealant rings to seal the IC’s to maximize efficiency (paragraph 0004-0005), and in addition to have modified the sizes of the diameters of the sealant rings to be specifically half the diameter of the substrate to maximize stability of sealing the IC’s while minimizing cost (less sealant ring material, less cost).
Claim(s) 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al (US 20210050251 A1), Sato et al (US 20230099856 A1) and Ding et al (US 20160093601 A1) in further view of Uozumi (US 20210091024 A1).
Hsiao et al as modified teaches all of the limitations of the parent claims, claims 1 and 11, but does not specifically disclose
[claim 10] the semiconductor device according to claim 1, wherein one of the first circuit and the second circuit constitutes a memory cell array including a plurality of memory cells, and the other one of the first circuit and the second circuit constitutes a plurality of transistors configured to control the memory cell array.
[claim 17] the semiconductor device according to claim 11, wherein one of the first circuit and the second circuit constitutes a memory cell array including a plurality of memory cells, and the other one of the first circuit and the second circuit constitutes a plurality of transistors configured to control the memory cell array.
However, Uozumi does teach
[claim 10] the semiconductor device according to claim 1, wherein one of the first circuit and the second circuit constitutes a memory cell array including a plurality of memory cells, and the other one of the first circuit and the second circuit constitutes a plurality of transistors configured to control the memory cell array (paragraph 0022, figure 1, where the one active circuit designated in element 3 consists of a plurality of memory cells and the other active circuit designated in element 2 consists of a controller with transistors to control said memory cells).
[claim 17] the semiconductor device according to claim 11, wherein one of the first circuit and the second circuit constitutes a memory cell array including a plurality of memory cells, and the other one of the first circuit and the second circuit constitutes a plurality of transistors configured to control the memory cell array (paragraph 0022, figure 1, where the one active circuit designated in element 3 consists of a plurality of memory cells and the other active circuit designated in element 2 consists of a controller with transistors to control said memory cells).
It would have been obvious to one of ordinary skill in the art at the time of filing ot have modified the teachings of Hsiao et al as modified in order to include the teachings of Uozumi in order to create and enable a high-density semiconductor device and effective use of the device area by bonding the die together in a vertical direction and connecting them.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818