Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/12/25 has been entered.
Applicant's amendment/arguments filed on 12/12/25 as being acknowledged and entered. By this amendment claims 1-6, 8-22 are pending and claims 15-19 are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGPub 2020/0203372) in view of Russo (US PGPub 2019/0198065).
Claim 1: Lee teaches (Fig. 3) a semiconductor memory device comprising: a first wiring (220); a second wiring (220) provided above the first wiring in a first direction; a memory pillar (VS) penetrating at least one of a portion of the first wiring or a portion of the second wiring in the first direction; a semiconductor layer (VC) provided in the memory pillar and extending in the first direction; and a contact plug (330) having a lower surface provided in the memory pillar and an upper surface above the memory pillar, the lower surface of the contact plug being in contact with the memory pillar and disposed below an upper surface of the second wiring; and a third wiring (BL) extending in a second direction intersecting the first direction and provided above the second wiring in the first direction, wherein the upper surface of the contact plug is in contact with the third wiring. The top surface of the contact plug is in electrical contact with the third wiring. Lee does not teach the contact plug being a metal contact plug. Russo teaches the contact plug being a metal contact plug (38,40) [0030]. Therefore it would have been obvious to one of ordinary skill in the art at the time the invention was made to substitute one know element (polysilicon) for another known element (metal) resulting in the predictable result of forming a deep trench contact (KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007)).
Claim 2: Lee teaches (Fig. 3) a core insulating layer (320) [0035] provided along an inner side surface of the semiconductor layer, wherein the lower surface of the contact plug is in contact with an upper surface of the core insulating layer.
Claim 20: Lee teaches (Fig. 3) the memory pillar includes a plurality of memory pillars, and the third wiring extending in the second direction across the plurality of memory pillars.
Claim 21: Russo teaches (Fig. 2) the first wiring includes a plurality of word lines provided in the first direction, the second wiring includes a drain-side select gate line, and the third wiring includes a bit line.
Claim 22: Russo teaches (Fig. 2, 16) [0074] an insulating layer (90) provided above the memory pillar and having an upper surface in contact with the third wiring, wherein the upper surface of the metal contact plug (38,92) and the upper surface of the insulating layer has a same level in the first direction. One of ordinary skill in the art would know that the other circuitry Russo is mentioning in paragraph [0074] is likely the bit lines as this is a known configuration as described in figure 2.
Claim(s) 3-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGPub 2020/0203372) in view of Russo (US PGPub 2019/0198065), as applied to claim 1 above and further in view of Lee (US PGPub 2022/0231044).
Regarding claim 3, as described above, Lee (372) and Russo substantially read on the invention as claimed, except Lee (372) and Russo do not teach a core insulating layer provided along an inner side surface of the semiconductor layer, wherein the semiconductor layer includes a first semiconductor layer (14_2) provided on an upper surface of the core insulating layer, and a second semiconductor layer (14_1) that covers side surfaces of the core insulating layer and the first semiconductor layer, and the lower surface of the contact plug is in contact (electrical) with upper surfaces of the first semiconductor layer and the second semiconductor layer. Lee (044) teaches (Fig. 1B) a core insulating layer provided along an inner side surface of the semiconductor layer, wherein the semiconductor layer includes a first semiconductor layer (14_2) provided on an upper surface of the core insulating layer, and a second semiconductor layer (14_1) that covers side surfaces of the core insulating layer and the first semiconductor layer, and the lower surface of the contact plug is in contact (electrical) with upper surfaces of the first semiconductor layer and the second semiconductor layer to improve operational reliability [ABS, 0003-0005]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Lee (372) and Russo to have had the semiconductor layers as claimed to improve operational reliability [ABS, 0003-0005] as taught by Lee (044).
Claim 4: Lee (044) teaches (Fig. 1B) a core insulating layer provided along an inner side surface of the semiconductor layer, wherein the semiconductor layer includes a first semiconductor layer provided on an upper surface of the core insulating layer, and a second semiconductor layer that covers side surfaces of the core insulating layer, the first semiconductor layer, and the contact plug, and the lower surface of the contact plug is in contact (electrical) with an upper surface of the first semiconductor layer.
Claim 5: Lee (044) teaches (Fig. 1B) a core insulating layer provided along an inner side surface of the semiconductor layer, wherein the lower surface of the contact plug is in contact with upper surfaces of the core insulating layer and the semiconductor layer. The contact plug is in electrical contact with the upper surface of the semiconductor layer.
Claim 6: Lee (044) teaches (Fig. 1B) a third wiring (19) provided above the second wiring in the first direction, wherein the contact plug is electrically connected to the third wiring.
Claim 7: Lee (044) teaches (Fig. 1B) a third wiring (19) provided above the second wiring in the first direction, wherein the upper surface of the contact plug is in contact with the third wiring.
Claim 8: Lee (044) teaches (Fig. 1B) the semiconductor layer includes a first semiconductor region and a second semiconductor region that are arranged with respect to each other in a second direction intersecting the first direction, and an upper surface of the first semiconductor region (14_1) is lower than an upper surface of the second semiconductor region (14_2).
Claim 9: Lee (044) teaches (Fig. 1B) the semiconductor layer includes a first semiconductor region and a second semiconductor region that are arranged with respect to each other in a second direction intersecting the first direction, the first semiconductor region (14_2) does not face the second wiring, and the second semiconductor region (14_1) faces the second wiring.
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Claim 10: Lee (044) teaches (Fig. 1B) in a second direction intersecting the first direction, a width of the second wiring is smaller than a width of the first wiring.
Claim 11: Lee (044) teaches (Fig. 1B) [0023, 0031] the contact plug includes tungsten.
Claim 12: Lee (044) teaches (Fig. 1B) the second wiring includes a plurality of wirings (GL_P1, GL_P2) in the first direction, and the lower surface of the contact plug is in contact with the semiconductor layer above a lower surface of a lowermost wiring among the plurality of wirings.
Claim 13: Lee (044) teaches (Fig. 1B) [0071] a portion of the semiconductor layer in contact with the contact plug does not substantially contain a dopant. Lee teaches that the second portion may or may not be doped depending on the threshold voltages required by the device.
Claim 14: Lee (044) teaches (Fig. 1B) [0071] a dopant concentration of a first portion of the semiconductor layer in contact with the contact plug and a dopant concentration of a second portion of the semiconductor layer facing the first wiring are equal to or less than a detection limit. Lee teaches that the second portion may or may not be doped depending on the threshold voltages required by the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/ Primary Examiner, Art Unit 2814
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