Status of Claims
Amended claims 1-10, 23-27, and 30 are pending.
Claims 11-22 and 28-29 are cancelled.
Response to Amendment
The amendment filed 04/06/2026 has been accepted and entered.
Response to Arguments
Applicant’s amendment to independent claim 1, and its respective dependent claims and corresponding arguments, see pages 6-7 of Applicant’s remarks filed 04/06/2026, with respect to the 35 U.S.C. 103 rejection of claim 1 has been fully considered and is persuasive. The standing rejection of claim 1 as being unpatentable over EOM in view of Matsuno does not teach all of the limitations of amended claim 1 (i.e. “a top surface of the first semiconductive layer is coplanar with a top surface of the second semiconductive layer”) and thus and its respective dependent claims.
In view of the amendment, new grounds of rejection have been applied (see below). Independent claim 1 now stands rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0152585 A1 Dae-Sung EOM in view of US 2022/0352197 A1 Matsuno et al and further in view of US 2018/0061850 A1 Mada et al.
Applicant’s amendment to independent claim 10, and its respective dependent claims and corresponding arguments, see pages 6-7 of Applicant’s remarks filed 04/06/2026, with respect to the 35 U.S.C. 103 rejection of claim 10 has been fully considered and is persuasive. The standing rejection of claim 10 as being unpatentable over EOM in view of Matsuno does not teach all of the limitations of amended claim 1 (i.e. “a top surface of the first semiconductive layer is coplanar with a top surface of the second semiconductive layer”) and thus and its respective dependent claims.
In view of the amendment, new grounds of rejection have been applied (see below). Independent claim 10 now stands rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0152585 A1 Dae-Sung EOM in view of US 2015/0279431 A1 Jian Li et al and further in view of US 2022/0352197 A1 Matsuno et al.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1-9 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0152585 A1 Dae-Sung EOM (herein “EOM”) in view of US 2022/0352197 A1 Matsuno et al (herein “Matsuno”) and further in view of US 2018/0061850 A1 Mada et al (herein “Mada”).
Regarding Claim 1, EOM discloses:
A three-dimensional (3D) memory device (#100, see generally Figs. 1A and 1B showing top down and side views of memory device), comprising:
a stack (#110) comprising a plurality of conductive layers (#103) and a plurality of dielectric layers (#102) stacked alternatingly, wherein the stack (#110) comprises a staircase structure (#104)
an insulating structure (#142) over the stack (#110) and the staircase structure (#104);
a plurality of contact structures (#141) each extending through the insulating structure (#142) and in contact with a respective conductive layer (#103) of the plurality of conductive layers (#103) in the staircase structure (#104); and
a plurality of support structures (#130, specifically support structures #131) extending through the stack in the staircase structure (#104);
a semiconductive layer (#101) under the stack (#110),
wherein each support structure (#131) is in contact with one of the plurality of contact structures (#141); and
the plurality of support structures (#131) extend into the semiconductive layer (#101).
EOM does not explicitly disclose:
a first semiconductive layer under the stack; and
a second semiconductive layer under the first semiconductive layer,
and the plurality of support structures extend through the first semiconductive layer and extend in the second semiconductive layer; and
a top surface of the first semiconductive layer is coplanar with a top surface of the second semiconductive layer.
However, in analogous art, Matsuno teaches:
See Fig. 25A and paragraph [0064].
a first semiconductive layer (#116, [0064]) under the stack (Matsuno stack comprises alternating layers #32 and #46);
a second semiconductive layer (#112, [0064]) under the first semiconductive layer (#116),
and the plurality of support structures (Matsuno support structures assigned element #22 in Fig. 25A, see formation of support pillars #22 in Fig. 10I and further shown in Fig. 13A, see also paragraphs [0021], [0097], and [0180]) extend through the first semiconductive layer (#116) and extend in the second semiconductive layer (#114).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Matsuno to the device disclosed by EOM and substitute in the multilayer semiconductor structure below the alternating stack, and form the support pillars such that they extend through the first semiconductor layer and into the second semiconductor layer. Doing so would provide structural/mechanical stability within the device, as well as increased electrical contact between the semiconductor layers. Additional note, Matsuno includes an intermediate source-level semiconductor layer #114 as a part of the multilayer semiconductor structure that the support pillars extend through which would also be substituted into EOM’s device. See paragraph [0191]: “The source contact layer 114 as initially formed may consist essentially of semiconductor atoms and dopant atoms of the second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer 114.”
EOM in view of Matsuno does not explicitly disclose:
a top surface of the first semiconductive layer is coplanar with a top surface of the second semiconductive layer.
However, in analogous art, Mada teaches:
See generally Fig. 1 showing semiconductor layers prior to completed device, and Figs. 27 and 28. See also paragraph [0091], specifically memory stack structures 55 acting as structural supports: “The support pillar structures 20 and the memory stack structures 55 provide structural support to prevent collapse of the insulating layers 32 while the backside recesses 43 are present within volumes previously occupied by the sacrificial material layers 42.”
a top surface of the first semiconductive layer (#10) is coplanar with a top surface of the second semiconductive layer (#9).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Mada to the device disclosed by EOM in view of Matsuno and form the first and second semiconductor layers such that their top surfaces are coplanar. Doing so would be a modification to form a doped semiconductor well to a portion under the support structures in order to modify the electrical characteristics of the underlying semiconductor layers, see [0049] and [0070].
Regarding Claim 2, EOM in view of Matsuno and further in view of Mada discloses: The 3D memory device of claim 1
EOM further discloses:
wherein the plurality of contact structures (#141) and the plurality of support structures (#131) comprise different materials (paragraph [0083] discloses contact structures comprise a conductive material, and paragraph [0023] discloses support structures comprise a dielectric material).
Regarding Claim 3, EOM in view of Matsuno and further in view of Mada discloses: The 3D memory device of claim 1
EOM further discloses:
wherein the plurality of contact structures (#141) and the plurality of support structures (#131) overlap in a plan view (see top down view in Fig. 1A) of the 3D memory device (#100).
Regarding Claim 4, EOM in view of Matsuno and further in view of Mada discloses: The 3D memory device of claim 3
EOM further discloses:
wherein each support structure (#131) aligns one of the plurality of contact structures (#141).
Regarding Claim 5, EOM in view of Matsuno and further in view of Mada discloses: The 3D memory device of claim 1
EOM further discloses:
wherein each contact structure (#141) further comprises a staircase contact (#103P) in contact with the respective conductive layer (#103) of the plurality of conductive layers (#103).
Regarding Claim 6, EOM in view of Matsuno and further in view of Mada discloses: The 3D memory device of claim 5
EOM further discloses:
wherein each support structure (#131) is in contact with the staircase contact (#103P) of one of the plurality of contact structures (#141).
Regarding Claim 7, EOM in view of Matsuno and further in view of Mada discloses: The 3D memory device of claim 1
EOM further discloses:
wherein the plurality of support structures (#131) comprise a dielectric material (paragraph [0023] discloses support structures comprise a dielectric material).
Regarding Claim 8, EOM in view of Matsuno and further in view of Mada discloses: The 3D memory device of claim 1
EOM in view of Matsuno and further in view of Mada does not explicitly disclose:
further comprising: a channel structure extending through the stack and in contact with the second semiconductive layer.
However, Matsuno teaches:
a channel structure (#58, Fig. 25A, see paragraph [0130]: “Material layers comprising a memory material layer and a semiconductor channel material layer can be deposited and planarized during formation of the memory opening fill structures 58 and the composite support pillar structures 22.”) extending through the stack (##32, #46) and in contact with the second semiconductive layer (#112).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Matsuno to the device disclosed by EOM in view of Matsuno and further in view of Mada and form the channel structures such that they contact the second semiconductor layer. Doing so would provide structural/mechanical stability for the channel structures, as well as increased electrical contact between the semiconductor layers and the channel structure.
Regarding Claim 9, EOM in view of Matsuno and further in view of Mada discloses: The 3D memory device of claim 8
EOM further discloses:
wherein the first semiconductive layer (#101) and the plurality of contact structures (#141) are separated by at least one of the plurality of conductive layers (#103, see Fig. 1B; the rightmost contact structure is separated from the semiconductor layer by the bottommost conductive layer AND the bottommost dielectric layer of the alternating stack).
Regarding Claim 23, EOM in view of Matsuno and further in view of Mada discloses The 3D memory device of claim 1.
Matsuno further discloses:
wherein the second semiconductive layer (#112) is polysilicon (see paragraph [0064]: “The lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon.”).
Claims 10 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0152585 A1 Dae-Sung EOM in view of US 2015/0279431 A1 Jian Li et al (herein “Li”) and further in view of US 2022/0352197 A1 Matsuno et al and further in view of US 2018/0061850 A1 Mada et al.
Regarding Claim 10, EOM discloses:
a three-dimensional (3D) memory device (#100, see generally Figs. 1A and 1B showing top down and side views of memory device) configured to store data, the 3D memory device (#100) comprising:
a stack (#110) in an insulating structure (#142) comprising a plurality of conductive layers (#103) and a plurality of dielectric layers (#102) stacked alternatingly, wherein the stack (#110) comprises a staircase structure (#104);
a plurality of contact structures (#141) each extending through the insulating structure (#142) and in contact with a respective conductive layer (#103) of the plurality of conductive layers (#103) in the staircase structure (#104); and
a plurality of support structures (#130) extending through the stack (#110) in the staircase structure (#104); and
a semiconductive layer (#101) under the stack (#110),
wherein each support structure (#130) is in contact with one of the plurality of contact structures (#141); and
the plurality of support structures (#131) extend into the semiconductive layer (#101).
EOM does not explicitly disclose:
A system comprising a 3D memory device;
a memory controller coupled to the 3D memory device and configured to control operations of the 3D memory device.
a first semiconductive layer under the stack; and
a second semiconductive layer under the first semiconductive layer,
and the plurality of support structures extend through the first semiconductive layer and extend in the second semiconductive layer; and
a top surface of the first semiconductive layer is coplanar with a top surface of the second semiconductive layer.
However, in analogous art, Li teaches:
A system (see generally Fig. 4) comprising a 3D memory device ( #444);
a memory controller (#442) coupled to the 3D memory device (#444) and configured to control operations of the 3D memory device (see paragraph [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Li to the 3D memory device disclosed by EOM and include a memory controller as a part of a larger system to use the 3D memory device with the contact structures and support structures for its intended purpose of storing data.
EOM in view of Li does not explicitly disclose:
a first semiconductive layer under the stack; and
a second semiconductive layer under the first semiconductive layer,
and the plurality of support structures extend through the first semiconductive layer and extend in the second semiconductive layer; and
a top surface of the first semiconductive layer is coplanar with a top surface of the second semiconductive layer.
However, in analogous art, Matsuno teaches:
See Fig. 25A and paragraph [0064].
a first semiconductive layer (#116, [0064]) under the stack (Matsuno stack comprises alternating layers #32 and #46); and
a second semiconductive layer (#112, [0064]) under the first semiconductive layer (#116),
and the plurality of support structures (Matsuno support structures assigned element #22 in Fig. 25A, see formation of support pillars #22 in Fig. 10I and further shown in Fig. 13A, see also paragraphs [0021], [0097], and [0180]) extend through the first semiconductive layer (#116) and extend in the second semiconductive layer (#114).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Matsuno to the device disclosed by EOM in view of Li and substitute in the multilayer semiconductor structure below the alternating stack, and form the support pillars such that they extend through the first semiconductor layer and into the second semiconductor layer. Doing so would provide structural/mechanical stability within the device, as well as increased electrical contact between the semiconductor layers. Additional note, Matsuno includes an intermediate source-level semiconductor layer #114 as a part of the multilayer semiconductor structure that the support pillars extend through which would also be substituted into EOM’s device. See paragraph [0191]: “The source contact layer 114 as initially formed may consist essentially of semiconductor atoms and dopant atoms of the second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer 114.”
EOM in view of Li and further in view of Matsuno does not explicitly disclose:
a top surface of the first semiconductive layer is coplanar with a top surface of the second semiconductive layer.
However, in analogous art, Mada teaches:
See generally Fig. 1 showing semiconductor layers prior to completed device, and Figs. 27 and 28. See also paragraph [0091], specifically memory stack structures 55 acting as structural supports: “The support pillar structures 20 and the memory stack structures 55 provide structural support to prevent collapse of the insulating layers 32 while the backside recesses 43 are present within volumes previously occupied by the sacrificial material layers 42.”
a top surface of the first semiconductive layer (#10) is coplanar with a top surface of the second semiconductive layer (#9).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Mada to the device disclosed by EOM in view of Li and further in view of Matsuno and form the first and second semiconductor layers such that their top surfaces are coplanar. Doing so would be a modification to form a doped semiconductor well to a portion under the support structures in order to modify the electrical characteristics of the underlying semiconductor layers, see [0049] and [0070].
Regarding Claim 30, EOM in view of Li and further in view of Matsuno and further in view of Mada discloses the system of claim 10.
Matsuno further discloses:
wherein the second semiconductive layer (#112) is polysilicon (see paragraph [0064]: “The lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon.”).
Claims 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0152585 A1 Dae-Sung EOM in view of US 2022/0352197 A1 Matsuno et al and further in view of US US 2018/0061850 A1 Mada et al and further in view of US 2023/0049653 A1 Lee et al (herein “Lee”).
Regarding Claim 24, EOM in view of Matsuno and further in view of Mada discloses The 3D memory device of claim 1.
EOM in view of Matsuno and further in view of Mada does not explicitly disclose:
further comprising: a plurality of stop layers each on the respective conductive layer of the plurality of conductive layers in the staircase structure.
However, in analogous art, Lee teaches:
See Fig 7.
further comprising: a plurality of stop layers (#PP) each on the respective conductive layer (#EL) of the plurality of conductive layers (#EL) in the staircase structure (#ST).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Lee to the device disclosed by EOM in view of Matsuno and further in view of Mada and include stop layers on the conductive structures/layers. Doing so would provide a conductive surface for the contact pillar to connect to electrically connect the plurality of conductive layers to the contact pillars.
Regarding Claim 25, EOM in view of Matsuno and further in view of Mada and further in view of Lee discloses The 3D memory device of claim 24.
Lee further teaches:
wherein the plurality of stop layers (#PP) comprises polysilicon.
Lee teaches the stop layer, which is formed along with the conductive layers #EL are formed from a metallic material, see paragraph [0054]: “The electrodes EL may be formed of or include at least one of, for example, metallic materials (e.g., tungsten).” Lee also discloses in paragraph [0059] that metallic materials are interchangeable with polysilicon materials, with respect to the bit pad line, specifically “The bit line pad BPLG may be formed of or include at least one of doped polysilicon or metallic materials (e.g., tungsten, aluminum, or copper).” Therefore, according to Lee’s teachings of interchangeable materials, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider substituting the polysilicon material for the metallic material for the stop layer for the purposes of providing a dedicated platform for the conductive pillars to electrically connect to the conductive layers in the alternating stack.
Regarding Claim 26, EOM in view of Matsuno and further in view of Mada and further in view of Lee discloses The 3D memory device of claim 24.
EOM in view of Matsuno and further in view of Lee does not explicitly disclose:
wherein the plurality of support structures extend through the respective conductive layer of the plurality of conductive layers in the staircase structure.
However, in analogous art, Lee teaches:
See Fig. 7.
wherein the plurality of support structures (#CR) extend through the respective conductive layer (#EL) of the plurality of conductive layers (#EL) in the staircase structure (#ST).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Lee to the device disclosed by EOM in view of Matsuno and further in view of Mada and further in view of Lee and form the support structures such that they extend through the respective conductive layers. Doing so would provide more structural stability within the alternating stack, and provide a more stable surface for the through contacts to bond to during production.
Regarding Claim 27, EOM in view of Matsuno and further in view of Mada and further in view of Lee discloses The 3D memory device of claim 26.
Lee further teaches:
wherein the plurality of support structures (#CR) are in contact with the plurality of stop layers (#PP).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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