Prosecution Insights
Last updated: April 19, 2026
Application No. 17/891,162

TRANSISTOR

Final Rejection §103
Filed
Aug 19, 2022
Examiner
PARK, SAMUEL
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Magnolia White Corporation
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
388 granted / 461 resolved
+16.2% vs TC avg
Strong +26% interview lift
Without
With
+25.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
24 currently pending
Career history
485
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
53.2%
+13.2% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
21.3%
-18.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 461 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment 1. Applicant’s amendment to the claims, filed on August 22, 2021, is acknowledged. Entry of amendment is accepted and made of record. Response to Arguments/Remarks 2. Applicant’s arguments/remarks, see pgs. 6-10, with respect to the immediate allowance of the current application have been fully considered but are not persuasive. Pertaining to the Applicant’s arguments/remarks, pgs. 6-10, directed towards the newly amended limitations of claim 1. The Examiner notes that a new combination of prior arts is presented as necessitated by the newly presented amendments – arguments directed solely to the previously presented combination of prior art(s) are now moot. Note by the Examiner 3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 4. Claims 1-2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (US 10,249,654 B1), hereinafter as Z1, in view of Yamazaki et al. (US 2022/0271167 A1), hereinafter as Y1, in view of Yamazaki et al. (US 2013/0207101 A1), hereinafter as Y2 5. Regarding Claim 1, Z1 discloses a transistor (see in particular Figs. 13-14, and Column 5 line 42 “TFT”) comprising: a gate electrode (element 55, see Column 6 line 63 “gate 55”); an oxide semiconductor layer (element 40, see Column 8 lines 34-36 “active layer 40 is … zinc oxide semiconductor”) which overlaps the gate electrode and including a central portion (see Fig. 14 central portion overlapped with the gate element 55 portion which is laterally thicker in the perspective view than top and bottom end portions) and an end portion (end portion excluding the central portion in the perspective view); an insulating layer (element 30, see Column 5 line 58 “insulating layer 30”) provided between the gate electrode and the oxide semiconductor layer (see Figs. 13-14); and a source electrode (element 51, see Column 6 lines 62-63) and a drain electrode (element 52, see Column 6 lines 62-63) each connected to the oxide semiconductor layer, wherein a length of the gate electrode overlapping the central portion is greater than a length of the gate electrode overlapping the end portion (see Fig. 14). Z1 does not explicitly disclose an oxidation degree of the end portion is lower than an oxidation degree of the central portion; the gate electrode has a circular shape. Y1 discloses an oxidation degree of the end portion is lower than an oxidation degree of the central portion (see Fig. 2 and [0095] “The region 234 functioning as the channel formation region is a higher-resistance region with a lower carrier concentration because it has a higher oxygen concentration or a lower impurity concentration than the region 236a and the region 236b”). The relative oxidation degree of the oxide semiconductor layer at a central active layer region below the gate compared to the outer areas as taught by Y1 is incorporated as a relative oxidation degree of the oxide semiconductor layer at a central active layer region below the gate compared to the outer areas of Z1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 with Z1 because the combination allows for controlling of the conductivity of the active channel formation region with respect to the other regions which are electrically connected to the source/drain electrodes (see Y1 Fig. 2 and [0095]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known oxide semiconductor layer impurity relationship, particularly of oxygen, between the active channel formation region and outer areas for another to obtain predictable results of relative conductivity control (see Y1 Fig. 2 and [0095]). Y1, Z1 do not discloses the gate electrode has a circular shape. Y2 discloses the gate electrode has a circular shape (see Fig. 16A and [0401] “The transistor 290 includes the circular gate electrode 208”). The shape of the gate electrode as taught by Y2 is incorporated as a shape of the gate electrode of Y1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y2 with Y1 because the combination allows for efficient current flow through the oxide semiconductor layer such that a transistor which has further favorable electric characteristics can be achieved (see Y2 [0401]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gate electrode shape for another in a similar device for which alternative shapes are provided as selectable to obtain predictable results (see Y2). 6. Regarding Claim 2, Y1, Z1, Y2 disclose the transistor according to claim 1, wherein the gate electrode is provided between the source electrode and the drain electrode, and the oxide semiconductor layer (see Y1 Fig. 13). 7. Regarding Claim 4, Y1, Z1, Y2 disclose the transistor according to claim 1, wherein the gate electrode has a shape (see Y1 Figs. 13-14 the gate element 55 has straight and flat portions which can be obtained by cutting a portion of a circle by a string to obtain flat and straight edges) in which a portion of a circle is cut by a string (The language, term, or phrase “a portion of the circle is cut by a string” is directed towards the process of manufacturing the gate electrode. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Pilkington 162 USPQ 145, 147; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. The applicant must show that different methods of manufacturing produce articles having inherently different characteristics, Ex parte Skinner 2 USPQ 2d 1788. As such, the language a portion of the circle is cut by a string only requires a gate electrode shape with at least surface that can be flat or wavy – capable of being formed through cutting a portion of a circle with a string – which does not distinguish the invention from the prior art, which teaches the structure as claimed.). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL PARK/Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Aug 19, 2022
Application Filed
Aug 09, 2025
Non-Final Rejection — §103
Sep 12, 2025
Interview Requested
Oct 02, 2025
Applicant Interview (Telephonic)
Oct 02, 2025
Examiner Interview Summary
Nov 04, 2025
Response Filed
Nov 15, 2025
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604460
SEMICONDUCTOR MEMORY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12598733
SEMICONDUCTOR STRUCTURE, METHOD FOR FORMING SAME AND LAYOUT STRUCTURE
2y 5m to grant Granted Apr 07, 2026
Patent 12588190
SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD FOR FABRICATING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12588295
CAPACITOR AND METHOD FOR FORMING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12564076
CHIP PACKAGE WITH FAN-OUT FEATURE AND METHOD FOR FORMING THE SAME
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+25.7%)
2y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 461 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month