DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
The preliminary amendment filed on March 21st, 2023 has been entered. Claims 2-20 have been cancelled and claim 21 has been newly added. Accordingly, claims 1 and 21 are pending in the present application in which claims 1 and 21 are in independent form.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 14/337,146, filed on July 21st, 2014.
Information Disclosure Statement
The IDS filed on November 30th, 2022 has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 9,287,229. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claimed invention of the present application is encompasses by the scope of the claimed invention of U.S. Patent No. 9,287,229, see comparison table below.
Claims of present application
Claims of U.S. Patent No. 9,287,229
21. (New). A semiconductor device, comprising: a semiconductor die comprising a die top side, a die bottom side opposite the die top side, a contact pad on the die top side, and a die sidewalls between the die top side and the die bottom side; a conductive structure electrically coupled to the contact pad on the die top side; an encapsulating resin; and a via that extends through the encapsulating resin.
1. A semiconductor device, the device comprising: a semiconductor die having a first surface, a second surface opposite to the first surface, and side surfaces between the first and second surfaces; an encapsulant encapsulating the side surfaces of the semiconductor die; a non-photosensitive protection layer covering a portion of the first surface of the semiconductor die and a first surface of the encapsulant; a contact pad on the first surface of the semiconductor die; and a redistribution layer on the non-photosensitive protection layer and the contact pad wherein: the redistribution layer comprises a linear portion and a circular pad; and a hemispherical conductive bump on the circular pad comprises a protruding part extending toward the linear portion and having a radius less than the hemispherical conductive bump.
3. The device according to claim 1, wherein a through via extends from the redistribution layer through the non-photosensitive protection layer and the encapsulant.
Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 9,818,685. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claimed invention of the present application is encompasses by the scope of the claimed invention of U.S. Patent No. 9,818,685, see comparison table below.
Claims of present application
Claims of U.S. Patent No. 9,818,685
21. (New). A semiconductor device, comprising: a semiconductor die comprising a die top side, a die bottom side opposite the die top side, a contact pad on the die top side, and a die sidewalls between the die top side and the die bottom side; a conductive structure electrically coupled to the contact pad on the die top side; an encapsulating resin; and a via that extends through the encapsulating resin.
6. A semiconductor device, the device comprising: a semiconductor die having a first surface, a second surface opposite to the first surface, and side surfaces between the first and second surfaces; a non-photosensitive protection layer covering a portion of the first surface of the semiconductor die; a contact pad on the first surface of the semiconductor die; a redistribution layer on the non-photosensitive protection layer and the contact pad, the redistribution layer comprising a linear portion and a circular contact pad; and a hemispherical conductive bump on a circular pad comprising a protruding part extending toward the linear portion, wherein the protruding part has a radius less than the hemispherical conductive bump.
7. The device according to claim 6, wherein a through via extends from the redistribution layer through the non-photosensitive protection layer.
13. The device according to claim 6, wherein an encapsulant encapsulates the redistribution layer, the non-photosensitive protection layer, and a portion of the hemispherical conductive bump.
Claims 1 and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10,199,322. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claimed invention of the present application is encompasses by the scope of the claimed invention of U.S. Patent No. 10,199,322, see comparison table below.
Claims of present application
Claims of U.S. Patent No. 10,199,322
1. (Previously Presented) A method for manufacturing a semiconductor device, the method comprising: forming a pattern in a non-photosensitive protection layer;
providing a semiconductor die with a contact pad on a first surface; bonding the semiconductor die to the non-photosensitive protection layer; encapsulating a second surface opposite to the first surface of the semiconductor die; and forming a redistribution layer on the contact pad and the non-photosensitive protection layer opposite to the first surface.
16. A method for electronic device packaging, comprising: providing an electronic device, wherein: the electronic device has a first surface, a second surface opposite to the first surface, and side surfaces between the first and second surfaces, and an insulating structure is on the first surface of the electronic device; forming a redistribution structure on the insulating structure, wherein: the redistribution structure comprises a linear portion and a bump pad, and the redistribution structure is electrically coupled to the electronic device; and forming a conductive bump on the bump pad, wherein: the conductive bump comprises a main bump and a protruding part extending toward the linear portion, and the protruding part is smaller than the main bump.
20. The method according to claim 16, comprising: encapsulating the side surfaces with an encapsulant; forming a through via to extend from the redistribution structure through the insulating structure and the encapsulant; and forming a connection member in the through via, wherein a bottom-most surface of the connection member is higher than the second surface of the electronic device.
21. (New). A semiconductor device, comprising: a semiconductor die comprising a die top side, a die bottom side opposite the die top side, a contact pad on the die top side, and a die sidewalls between the die top side and the die bottom side; a conductive structure electrically coupled to the contact pad on the die top side; an encapsulating resin; and a via that extends through the encapsulating resin.
10. A semiconductor device, comprising: an electronic device having a first surface, a second surface opposite to the first surface, and side surfaces between the first and second surfaces; an insulating structure covering a portion of the first surface of the electronic device; and a redistribution structure on the insulating structure and electrically coupled to the electronic device, wherein: the redistribution structure comprises a linear portion and a bump pad; and a conductive bump on the bump pad comprises a main bump and a protruding part extending toward the linear portion, wherein the protruding part is smaller than the main bump.
14. The semiconductor device according to claim 10, comprising a first encapsulant encapsulating the side surfaces, wherein: a through via extends from the redistribution structure through the insulating structure and the first encapsulant, and a bottom-most surface of conductive material in the through via is higher than the second surface of the electronic device.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Klein et al. (U.S. Pub. 2004/0145051).
In re claim 1, Klein discloses a method for manufacturing a semiconductor device 10, the method comprising: forming a pattern in a non-photosensitive protection layer 50 (see paragraph [0071] and figs. 1C-G and 5A-C) providing a semiconductor die 14 with a contact pad 68 on a first surface (see paragraph [0069] and figs. 5A-C); bonding the semiconductor die 14 to the non-photosensitive protection layer 50 (see paragraph [0071] and fig. 5B); encapsulating 16 a second surface opposite to the first surface of the semiconductor die 14 (see paragraphs [0050], [0060], [0081] and figs. 5A-C and 7E-F); and forming a redistribution layer (28,30,44) on the contact pad 68 and the non-photosensitive protection layer 50 opposite to the first surface (see paragraphs [0056], [0057], [0058], and figs. 5A-C and 7E-F).
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In re claim 21, Klein discloses a semiconductor device 10, comprising: a semiconductor die 14 comprising a die top side, a die bottom side opposite the die top side (see paragraph [0050] and figs. 1C-G, 5A-C, and 7E-F), a contact pad 68 on the die top side, and a die sidewalls between the die top side and the die bottom side (see paragraph [0070] and figs. 5A-C and 7E-F); a conductive structure 44 electrically coupled to the contact pad 68 on the die top side (see paragraph [0072] and fig. 5C); an encapsulating resin 16 (see paragraph [0081] and figs. 5A-C and 7E-F); and a via 52 that extends through the encapsulating resin 16 (see paragraphs [0080], [0081] and figs. 5A-C and 7E-F).
Claim(s) 1 and 21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (U.S. Pub. 2013/0200528).
In re claim 1, Lin discloses a method for manufacturing a semiconductor device, the method comprising: forming a pattern in a non-photosensitive protection layer 298 (see paragraph [0148] and figs. 13t, providing a semiconductor die 276 with a contact pad 277 on a first surface (see paragraph [0147] and figs. 12t); bonding the semiconductor die 276 to the non-photosensitive protection layer 298 (see paragraphs [0136], [0141] and fig. 13t); encapsulating 286 a second surface opposite to the first surface of the semiconductor die 276 (see paragraph [0142] and fig. 12t); and forming a redistribution layer 320 on the contact pad 277 and the non-photosensitive protection layer 298 opposite to the first surface (see paragraph [0153], and fig. 13t).
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In re claim 21, Lin discloses a semiconductor device 10, comprising: a semiconductor die 276 comprising a die top side, a die bottom side opposite the die top side (see paragraph [0136] and fig. 13t), a contact pad 277 on the die top side, and a die sidewalls between the die top side and the die bottom side (see paragraph [0147] and fig. 13t); a conductive structure 302 electrically coupled to the contact pad 277 on the die top side (see paragraph [0148] and fig. 13); an encapsulating resin 286 (see paragraph [0142] and fig. 13t); and a via 250 that extends through the encapsulating resin 286 (see paragraphs [0162] and fig. 13t).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zeng U.S. Pub. 2012/0273941 November 1, 2012.
Tsai U.S. Patent 7,670,876 March 2, 2010.
Shim et al. U.S. Pub. 2009/0152715 June 18, 2009.
Huang et al. U.S. Patent 7,253,519 August 7, 2007.
Farnworth U.S. Pub. 2005/0253261 November 17, 2005.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892