DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on March 31, 2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 31, 2026 was filed after the mailing date of the Notice of Allowance on December 31, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-6 and 16 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Chung (US 2013/0148409 A1).
Regarding claim 1, Chung teaches an antifuse (memory cell 10 and/or 15 consists of an antifuse, see Fig. 1 and ¶ [0005] and ¶ [0003]-[0004] ) comprising:
a first source/drain region (right-most source in Fig. 2(d));
a second source/drain region (second drain from the right in Fig. 2(d));
a gate (see gate in Fig. 2(d)) arranged with the first source/drain region and the second source/drain being on opposite sides of the gate from each other (Fig. 2(d) shows right-most source and second drain from the right on opposite sides of the gate);
a first fin (fin of right-most source as shown in Figs. 2(b)-2(d)) contacting and extending from the first source/drain region to a first location (where fin meets high-K dielectric as shown in Fig. 2(a)) under the gate at which first location the first fin ends (Fig. 2(a) shows the source fin ends at where the fin meets the high-K dielectric), the first fin separated from the gate by a first dielectric (high-k dielectric as shown in Fig. 2(a)); and
a second fin (fin of second drain from the right of Fig. 2(d)) contacting and extending from the second source/drain region to a second location (where fin meets high-K dielectric as shown in Fig. 2(a)) under the gate at which second location the second fin ends (¶ [0007]: “The two sides and top surface of the island are grown with gate oxide and then a MOS gate can be built across the thin island to divide the fin into source, drain, and body;” hence, Fig. 2(a) also discloses the a high-k dielectric for the drain side), the second fin separated from the gate by a second dielectric (the high-k dielectric under the second drain from the right), the second fin being offset from the first fin such that the first fin and the second fin do not intersect (Fig. 2(d) shows the two said fins offset from a distance along the length of the gate).
Regarding claim 4, the antifuse of claim 1, wherein the antifuse includes:
a third source/drain region (left-most source in Fig. 2(d)); and
a third fin (fin of left-most source as shown in Figs. 2(b)-2(d)) contacting and extending from the third source/drain region to a third location (where fin meets high-K dielectric as shown in Fig. 2(a)) under the gate at which third location the third fin ends, the third fin separated from the gate by a third dielectric (Fig. 2(a) shows the source fin ends at where the fin meets the high-K dielectric), the third fin offset from the first fin and offset from the second fin such that the third fin does not intersect the first fin and does not intersect the second fin (as shown in Fig. 2(d), the third fin does not intersect the first fin and the second fin).
Regarding claim 5, the antifuse of claim 1, wherein the first location and the second location are on a reference line (plane 2, see Fig. 2(f)) at a center of the gate (Fig. 2(f) shows plane 2 being the center of the gate).
Regarding claim 6, the antifuse of claim 1, wherein the first dielectric and the second dielectric include a common composition (high-k dielectric, see Fig. 2(a); also, ¶ [0007]: “two sides and top surface of the island are grown with gate oxide;” since Chung teaches growing the first and second dielectric, i.e., gate oxide, at the same time, then both first and second dielectrics include a common composition).
Regarding claim 16, Chung teaches a method comprising:
forming an antifuse (memory cell 10 and/or 15 consists of an antifuse, see Fig. 1 and ¶ [0005] and ¶ [0003]-[0004] ), including:
forming a first source/drain region (right-most source in Fig. 2(d));
forming a second source/drain region (second drain from the right in Fig. 2(d));
forming a gate (see gate in Fig. 2(d)) such that the gate is arranged with the first source/drain region and the second source/drain being on opposite sides of the gate from each other (Fig. 2(d) shows right-most source and second drain from the right on opposite sides of the gate);
forming a first fin (fin of right-most source as shown in Figs. 2(b)-2(d)) contacting and extending from the first source/drain region to a first location (where fin meets high-K dielectric as shown in Fig. 2(a)) under the gate at which first location the first fin ends (Fig. 2(a) shows the source fins ends at where the fin meets the high-K dielectric);
forming a first dielectric (high-k dielectric as shown in Fig. 2(a)) separating the first fin from the gate;
forming a second fin (fin of second drain from the right of Fig. 2(d)) contacting and extending from the second source/drain region to a second location (where fin meets high-K dielectric as shown in Fig. 2(a)) under the gate at which second location the second fin ends (¶ [0007]: “The two sides and top surface of the island are grown with gate oxide and then a MOS gate can be built across the thin island to divide the fin into source, drain, and body;” hence, Fig. 2(a) also discloses the a high-k dielectric for the drain side), the second fin being offset from the first fin such that the first fin and the second fin do not intersect; and forming a second dielectric separating the second fin from the gate (Fig. 2(d) shows the two said fins offset from a distance along the length of the gate).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3, 7 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2013/0148409 A1) as applied to claim 1 above, and further in view of Su (US 2022/0102366 A1).
Regarding claim 2, Chung teaches the antifuse of claim 1, but does not teach: wherein the antifuse includes a third fin contacting and extending from the first source/drain region to a third location under the gate at which third location the third fin ends, the third fin separated from the gate by a third dielectric, the third fin being parallel to the first fin.
Su, in the same field of invention, teaches an antifuse (10, see Fig. 3C; see also Fig. 1, ¶ [0001], [0017] ), wherein the antifuse includes a third fin (LN2 of ring R1) contacting and extending from the first source/drain region (SD1, see Figs. 3B & 3C) to a third location (mid-point of G1 next to LN2 of R1) under the gate (G1) at which third location the third fin ends (see Fig. 3B), the third fin separated from the gate by a third dielectric (112; note: this is the region of 112 next to LN2 of R1), the third fin being parallel to the first fin (LN1 of R1, see Fig. 3C).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Su into the device of Chung to include a third fin contacting and extending from the first source/drain region to a third location under the gate at which third location the third fin ends, the third fin separated from the gate by a third dielectric, the third fin being parallel to the first fin. The ordinary artisan would have been motivated to modify Chung in the manner set forth above for at least the purpose of increasing the contact area of the gate structure and the active region due to the curved portions (CR1, see Su Fig. 3C and ¶ [0047]) of the fin structure, for the further purpose of reducing the breakdown voltage and the power consumption of the device (¶ [0048] ).
Regarding claim 3, the antifuse of claim 2, wherein the antifuse includes a fourth fin (LN2 of ring R2, see Fig. 3C) contacting and extending from the second source/drain region (SD1 of R2, see Figs. 3B & 3C) to a fourth location (mid-point of G1 next to LN2 of R2) under the gate (G1) at which fourth location the fourth fin ends (see Fig. 3B), the fourth fin separated from the gate by a fourth dielectric (112; note: this is the region of 112 next to LN2 of R2), the fourth fin being parallel to the second fin (LN1 of R2; see Fig. 3C).
Regarding claim 7, Chung teaches the antifuse of claim 6 and further teaches the first dielectric and second dielectric to be comprised of a high-k dielectric (see Fig. 2(a)). However, Chung does not teach: wherein the common composition includes one or more of silicon oxide, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, or a combination thereof.
Su, in the same field of invention, teaches the first dielectric (112, see Fig. 3B; this is region of 112 next to fin LN1 in ring R1 in Fig. 3C) and second dielectric (112, see Fig. 3B; this is region of 112 next to fin LN1 in ring R2 in Fig. 3C) of an antifuse (10; see also Fig. 1, ¶ [0001], [0017] ), wherein their common composition includes one or more of silicon oxide, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, or a combination thereof (¶ [0035]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Su into the device of Chung to substitute the un-named high-k dielectric material that comprise of the first and second dielectric of Chung with silicon oxide, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, or a combination thereof. The ordinary artisan would have been motivated to modify Chung in the manner set forth above for at least the purpose of using said materials for the predictable result of providing electrical insulation and/or for substituting equivalent materials known in the prior art as high-k dielectrics that provide electrical insulation (Su ¶ [0035] ). See also MPEP § 2143 (I)(B).
Regarding claim 17, Chung teaches the method of claim 16, but does not teach the method to include: forming a third fin contacting and extending from the first source/drain region to a third location under the gate at which third location the third fin ends such that the third fin is parallel to the first fin; forming a third dielectric separating the third fin from the gate; forming a fourth fin contacting and extending from the second source/drain region to a fourth location under the gate at which fourth location the fourth fin ends such that the fourth fin is parallel to the second fin; and forming a fourth dielectric separating the fourth fin from the gate.
Su, in the same field of invention, teaches a method of forming an antifuse (10, see Fig. 3; see also Fig. 1, ¶ [0001], [0017] ) to include:
forming a third fin (LN2 of ring R1, see Fig 3C) contacting and extending from the first source/drain region (SD1, see Figs. 3B & 3C) to a third location (mid-point of G1 next to LN2 of R1) under the gate (G1) at which third location the third fin ends (see Fig. 3B) such that the third fin is parallel to the first fin (LN1 of R1, see Fig. 3C);
forming a third dielectric (112; note: this is the region of 112 next to LN2 of R1) separating the third fin from the gate;
forming a fourth fin (LN2 of ring R2, see Fig. 3C) contacting and extending from the second source/drain region (SD1 of R2, see Figs. 3B & 3C) to a fourth location (mid-point of G1 next to LN2 of R2) under the gate (G1) at which fourth location the fourth fin ends (see Fig. 3B) such that the fourth fin is parallel to the second fin (LN1 of R2; see Fig. 3C); and
forming a fourth dielectric (112; note: this is the region of 112 next to LN2 of R2) separating the fourth fin from the gate.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Su into the device of Chung to form a third fin, a fourth fin, a third dielectric, and a fourth dielectric in the manner described above. The ordinary artisan would have been motivated to modify Chung in the manner set forth above for at least the purpose of increasing the contact area of the gate structure and the active region due to the curved portions (CR1, see Su Fig. 3C and ¶ [0047]) of the fin structure, for the further purpose of reducing the breakdown voltage and the power consumption of the device (¶ [0048] ).
Regarding claim 18, the method of claim 17, wherein the method includes:
forming a third source/drain region (left-most source in Chung Fig. 2(d));
forming a pair of fins (fin of left-most source as shown in Figs. 2(b)-2(d); in view of Su, this fin is a pair of fins) contacting and extending from the third source/drain region to positions (where fin meets high-K dielectric as shown in Fig. 2(a)) under the gate at which the pair of fins end, the fins of the pair of fins offset from each other and from the first, second, third, and fourth fins such that the fins of the pair of fins do not intersect each of the first, second, third, and fourth fins (as shown in Fig. 2(d), the fin of the third source/drain does not intersect the first fin and the second fin and in view of Su, also does not intersect the third fin and the fourth fin); and
forming a dielectric (Fig. 2(a) shows the source fin ends at where the fin meets the high-K dielectric) separating each fin of the pair of fins from the gate.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2013/0148409 A1) as applied to claim 1 above, and further in view of another embodiment of Chung.
Regarding claim 8, Chung teaches the antifuse of claim 1 and further teaches the gate to be a made of polysilicon (¶ [0004]: “CMOS gate, fabricated in silicided polysilicon;” ¶ [0005]: “…a silicided polysilicon, the same material and fabricated at the same time as a MOS gate” ). However, Chung does not teach wherein the gate is a metal gate.
Chung, in another embodiment (Fig. 9 and ¶ [0115] ), teaches the gate to be made of either polysilicon or metal (¶ [0115]: “[A] CMOS gate can be an N type, P type, or part N and part P type of polysilicon, silicided polysilicon or silicide in one embodiment. Alternatively a CMOS gate can be a non-aluminum metal gate” ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the polysilicon composition of the gate with a metal. The ordinary artisan would have been motivated to modify Chung in the manner set forth above for at least the purpose of substituting equivalent materials known in the prior art that provide gating functions in CMOS transistors (¶ [0115] ). See also MPEP § 2143 (I)(B).
Regarding claim 9, the antifuse of claim 8, wherein the gate includes one or more of titanium nitride, tantalum nitride, tungsten, molybdenum, ruthenium, or a combination thereof (¶ [0115]: TiN, TaN ).
Claims 10, 14-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2013/0148409 A1) in view of Jung (US 2020/0160927 A1).
Regarding claim 10, Chung teaches a memory device comprising:
an antifuse (memory cell 10 and/or 15 consists of an antifuse, see Fig. 1 and ¶ [0005] and ¶ [0003]-[0004] ) including:
a first source/drain region (right-most source in Fig. 2(d));
a second source/drain region (second drain from the right in Fig. 2(d));
a gate (see gate in Fig. 2(d)) arranged with the first source/drain region and the second source/drain being on opposite sides of the gate from each other (Fig. 2(d) shows right-most source and second drain from the right on opposite sides of the gate);
a first fin (fin of right-most source as shown in Figs. 2(b)-2(d)) contacting and extending from the first source/drain region to a first location (where fin meets high-K dielectric as shown in Fig. 2(a)) under the gate at which first location the first fin ends (Fig. 2(a) shows the source fin ends at where the fin meets the high-K dielectric), the first fin separated from the gate by a first dielectric (high-k dielectric as shown in Fig. 2(a)); and
a second fin (fin of second drain from the right of Fig. 2(d)) contacting and extending from the second source/drain region to a second location (where fin meets high-K dielectric as shown in Fig. 2(a)) under the gate at which second location the second fin ends (¶ [0007]: “The two sides and top surface of the island are grown with gate oxide and then a MOS gate can be built across the thin island to divide the fin into source, drain, and body;” hence, Fig. 2(a) also discloses the a high-k dielectric for the drain side), the second fin separated from the gate by a second dielectric (the high-k dielectric under the second drain from the right), the second fin being offset from the first fin such that the first fin and the second fin do not intersect (Fig. 2(d) shows the two said fins offset from a distance along the length of the gate).
However, Chung does not teach an array of memory cells; and a block of antifuses (¶ [0004]; Fig. 10 and ¶ [0127] teaches an OTP array), the antifuses structured for repair or replacement operations of a number of memory cells of the array.
Jung, in the same field of invention, teaches a memory device (10, see Fig. 2) comprising of an array of memory cells (33) and a block of fuses (31), the fuses structured for repair or replacement operations of a number of memory cells of the array (see ¶ [0030]: “The first fuse cells… may be used as redundancy memory cells for defective memory cells”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Jung into the device of Chung to use Chung’s anti-fuse design in Jung’s memory device such that the anti-fuses are structured for repair or replacement operations of a number of memory cells of the array. The ordinary artisan would have been motivated to modify Jung in the manner set forth above for at least the purpose of improving the reliability of the memory device (Jung ¶ [0003] ) and for preventing the deletion of data stored in the fuse cells during test procedure and/or manufacturing (Jung ¶ [0100], ¶ [0076] ).
Regarding claim 14, the memory device of claim 10, wherein each of the antifuses of the block have a same structure (Jung Figs. 10 & 11 and ¶ [0062]-[0064] show the same structure for each of the fuse cell in the block of fuses ) and the block is structured with the antifuses in number being less than ten percent of a total number of memory cells of the array (as shown in Fig. 5, FA2 is just one horizontal row, whereas there are a lot more non-FA2 rows in device 120).
Regarding claim 15, the memory device of claim 10, wherein the memory device includes control circuitry (20, see Jung Fig. 2 and ¶ [0022] ) to activate an antifuse of the block of antifuses in response to a determination of a defect in the array of memory cells (Jung ¶ [0022]-[0023], ¶ [0027] : page buffer circuit 24 is used to write data into the fuse; fuse selection circuit 22 and second decoder circuit 23 is used to access specific fuse bit cells for data writing; ¶ [0030]: data written pertains to repaired defective memory cells).
Regarding claim 19, Chung teaches method of claim 16, but does not teach: wherein the method includes forming the antifuse as an antifuse of a block of antifuses in a periphery to a memory array of a memory device, the antifuses having a common structure.
Jung, in the same field of invention, teaches a method of forming the antifuse (Fig. 10 or Fig. 11 are fuse cells 400; although Jung teaches fuses, a person of ordinary skill understands that fuses and anti-fuses are both One-Time-Programmable elements) as an antifuse (400) of a block of antifuses (31, see Fig. 2) in a periphery (below 33; also see Fig. 3) to a memory array (33) of a memory device (10), the antifuses having a common structure (see FA2 in Fig. 5; ¶ [0040] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Jung into the method of Chung to form the antifuse as an antifuse of a block of antifuses in a periphery to a memory array of a memory device. The ordinary artisan would have been motivated to modify Chung in the manner set forth above for at least the purpose of increasing the yield and reliability of the memory device by using the antifuse as a redundancy memory cell for replacing defective memory cells (Jung ¶ [0003] ).
Regarding claim 20, the method of claim 19, wherein the method includes:
forming contacts (BL / WL connecting each fuse in block FA2, see Jung Fig. 5) to the antifuses of the block; and
forming fins (fins of sources and drains in Chung Fig. 2(d)) of the antifuses of the block such that the fins of each antifuse are staggered from each other (Fig. 2 (d) show the fins being staggered along the length of the gate).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2013/0148409 A1) in view of Jung (US 2020/0160927 A1) as applied to claim 10 above, and further in view of Su (US 2022/0102366 A1).
Regarding claim 11, Chung et al. teach the memory device of claim 10, but does not teach: wherein the antifuse includes: a third fin contacting and extending from the first source/drain region to a third location under the gate at which third location the third fin ends, the third fin separated from the gate by a third dielectric, the third fin being parallel to the first fin; and a fourth fin contacting and extending from the second source/drain region to a fourth location under the gate at which fourth location the fourth fin ends, the fourth fin separated from the gate by a fourth dielectric, the fourth fin being parallel to the second fin.
Su, in the same field of invention, teaches an antifuse (10, see Fig. 3; see also Fig. 1, ¶ [0001], [0017] ) wherein
a third fin (LN2 of ring R1, see Fig 3C) contacting and extending from the first source/drain region (SD1, see Figs. 3B & 3C) to a third location (mid-point of G1 next to LN2 of R1) under the gate (G1) at which third location the third fin ends (see Fig. 3B), the third fin separated from the gate by a third dielectric (112; note: this is the region of 112 next to LN2 of R1), the third fin being parallel to the first fin (LN1 of R1, see Fig. 3C); and
a fourth fin (LN2 of ring R2, see Fig. 3C) contacting and extending from the second source/drain region (SD1 of R2, see Figs. 3B & 3C) to a fourth location (mid-point of G1 next to LN2 of R2) under the gate (G1) at which fourth location the fourth fin ends (see Fig. 3B), the fourth fin separated from the gate by a fourth dielectric (112; note: this is the region of 112 next to LN2 of R2), the fourth fin being parallel to the second fin (LN1 of R2; see Fig. 3C).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Su into the device of Chung to add a third fin, a fourth fin, a third dielectric, and a fourth dielectric in the manner described above. The ordinary artisan would have been motivated to modify Chung in the manner set forth above for at least the purpose of increasing the contact area of the gate structure and the active region due to the curved portions (CR1, see Su Fig. 3C and ¶ [0047]) of the fin structure, for the further purpose of reducing the breakdown voltage and the power consumption of the device (¶ [0048] ).
Regarding claim 12, the memory device of claim 11, wherein the antifuse includes a third source/drain region (left-most source in Chung Fig. 2(d)) having a pair of fins (in view of Su the fin that extend from the left-most source is a pair of fins) contacting and extending from the third source/drain region to positions (where fin meets high-K dielectric as shown in Fig. 2(a)) under the gate at which the pair of fins end, each of the pair of fins separated from the gate by a dielectric (Fig. 2(a) shows the source fin ends at where the fin meets the high-K dielectric), the fins of the pair of fins offset from each other and from the first, second, third, and fourth fins such that the fins of the pair of fins do not intersect each of the first, second, third, and fourth fins (as shown in Fig. 2(d), the fin of the third source/drain does not intersect the first fin and the second fin and in view of Su, also does not intersect the third and fourth fin).
Regarding claim 13, Chung et al. teach the memory device of claim 10 and further teaches the first dielectric and second dielectric to be comprised of a high-k dielectric (see Chung Fig. 2(a)). However, Chung et al. does not teach: wherein the gate is a metal gate and the first dielectric and the second dielectric include one or more of silicon oxide, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, or a combination thereof.
Su, in the same field of invention, teaches a first dielectric (112, see Fig. 3B; this is region of 112 next to fin LN1 in ring R1 in Fig. 3C) and a second dielectric (112, see Fig. 3B; this is region of 112 next to fin LN1 in ring R2 in Fig. 3C) of an antifuse (10; see also Fig. 1, ¶ [0001], [0017] ), wherein their common composition includes one or more of silicon oxide, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, or a combination thereof (¶ [0035] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Su into the device of Chung to substitute the un-named high-k dielectric material that comprise of the first and second dielectric of Chung with silicon oxide, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, or a combination thereof. The ordinary artisan would have been motivated to modify Chung in the manner set forth above for at least the purpose of using said materials for the predictable result of providing electrical insulation or for substituting equivalent materials known in the prior art as high-k dielectrics that provide electrical insulation (Su ¶ [0035] ). See also MPEP § 2143 (I)(B).
Conclusion
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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