DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 12/1/25 and 12/30/25.
Applicant’s amendment to claims 1, 3 and 13 is acknowledged.
Claims 1-22 are pending and claims 19-22 are withdrawn.
Claims 1-18 are subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1:
There does not appear to be support for the following limitation:
“the number of differently-sized solder joints having more than one different second shape different from the first shape, the number of differently-sized solder joints located within a region that corresponds to edges of the connection to the IC”
Referring to fig. 1, the number of differently-sized solder joints (108) are formed on the second surface and a plan view is shown in fig. 4I.
In fig. 4I, the region (204) is the chip mounting region that is the recited “a region that corresponds to edges of the connection to the IC”. Not all the differently-sized solder joints (442, 444) are located in this region (204). Only one large cross-shaped (444) solder joint is located in region (204). There does not appear to be a disclosure that another large solder joint located in region (204) may have a different shape. The another large solder joint having a different shape is located at the substrate edge shown as solder joint (442).
Claim 13 recites similar limitations, so the same rejection applies.
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The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1:
The following limitation is indefinite:
“the number of differently-sized solder joints having more than one different second shape different from the first shape”
Referring to fig. 1 annotated above, the number of differently-sized solder joints (108) are formed on the second surface and a plan view is shown in fig. 4I.
The plan views in figs. 2-4 are for the “number of differently-sized solder joints”. There does not appear to be a plan view of “the solder joints” so in is unclear what is “the first shape”. Since it is unclear what is “the first shape” then it is indefinite that the “second shape (is) different from the first shape”.
Claim 13 recites similar limitations, so the same rejection applies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11, 13-15, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Camacho et al., US Publication No. 2012/0061814 A1 (of record) in view of Aleksov et al., US Patent No. 9,233,835 and Mohammed, et al., US Publication No. 2019/0067229 A1 (of record).
Camacho teaches:
1. A semiconductor package comprising (see fig. 4c):
a substrate (106) larger in surface area than an IC (58), the substrate having bonded thereto:
an array of solder joints (110) on a first surface (e.g. top surface) of the substrate configured for a connection to the IC, a solder joint of the array of solder joints having a first surface area and a first shape; and
a number of solder joints (112) on a second surface (e.g. bottom surface) of the substrate (106) opposite the first surface having a second surface area larger than the first surface area,…the number of solder joints (112) located within a region that corresponds to edges of the connection to the IC (58) (In fig. 4c, the solder joints 112 extend across the left edge and right edge of the IC 58.). See Camacho at para. [0001] – [0077], figs. 1-13.
Regarding claim 1:
In fig. 4c, Camacho does not have a top view of the solder joints (110) to disclose the specific shape of the solder joints.
In an analogous art, Aleksov teaches solder joints (1201, 1221, 1241) may have a circular shape, fig. 2. See Aleksov at figs. 1-2, col 2, ln 1–67, col , ln 1–45.
In fig. 4c, Camacho does not expressly teach the number of solder joints are “differently-sized solder joints” and that “the number of differently-sized solder joints having more than one different second shape different from the first shape”
In an analogous art, Mohammed teaches solder joints connecting a package to PCB at para. [0054]. The solder joints comprise:
(see figs. 8-10) a number of differently-sized solder joints (24b)…the number of differently-sized solder joints (24b) having more than one different second shape different from the first shape (e.g. Figs. 8 and 10 shows joints 24b have more than one different shape.) See Mohammed at para. [0072] – [0074], also see fig. 4, para. [0054].
One of ordinary skill in the art modifying Camacho with Mohammed would form “the number of differently-sized solder joints (e.g. different shapes of 24b in figs. 8 and 10 as taught by Mohammed) having more than one different second shape different from the first shape (e.g. circular shape as taught by Aleksov; also circular shapes 24a in figs. 8 and 10 as taught by Mohammed).
Regarding claim 2:
Camacho teaches the number of solder joints (112) each have a surface area a larger than a first surface area (e.g. of 110).
Camacho is silent regarding “three times larger”.
Mohammed further teaches the number of differently-sized solder joints (24b) each have a surface area at least three times larger than a first surface area (e.g. 24 in fig. 4; 24a in fig. 8). The larger size solder joint can result in less parasitic resistance and inductance. See Mohammed at para. [0055].
Regarding claim 3:
Camacho further teaches:
3. The semiconductor package of claim 1, wherein the semiconductor package includes an integrated circuit (IC) (58) mounted on the first surface of the substrate (106), and wherein the number of solder joints (112) are included on the second surface (e.g. bottom surface) of the substrate opposite the first surface (e.g. top surface) and opposite the IC (58), fig. 4c.
Camacho does not expressly teach “differently-sized”.
Mohammed teaches this limitation as applied to claim 1 above.
Regarding claims 4-5:
Camacho further teaches:
wherein a corner of the IC (58) is about a first distance from an edge of the substrate (106), and wherein the number…of solder joints (112) are provided at a location about the first distance from the edge of the substrate (106),
wherein the IC (58) is mounted at a first location (e.g. close to center location.) on the substrate (106), and wherein at least one of the number of…solder joints (112) are included on a second surface (e.g. bottom surface) of the substrate (106) opposite the first surface (e.g. top surface) and proximate the first location (e.g. close to center location), fig. 4c.
Camacho does not expressly teach “differently-sized”
Mohammed teaches “differently-sized” as applied to claim 1 above.
Mohammed teaches “differently sized” solder joints are the larger solder joints (24b; e.g. compared to the smaller solder joints 24a).
Mohammed does not show the location of the larger solder joints is close to a center location of the substrate.
Aleksov teaches forming larger solder joints (1201, 1221, 1241) closer to a center location of the substrate to route power and ground signals. Aleksov further teaches forming smaller solder joints to route input/output signals. See Aleksov at col 3, ln 60–67.
It would have been obvious to one of ordinary skill in the art modifying Camacho with Mohammed to form larger “differently sized” solder joints at the center location of the substrate such that “the number of differently-sized solder joints (e.g. larger solder joints) are provided at a location (e.g. close to center) about a first distance from the edge of the substrate…at least one of the number of differently-sized solder joints (e.g. larger solder joints) are…proximate the first location (close to center location)” because Aleksov teaches the larger solder joints “…are less susceptible to solder joint failure due to their location and size”. See Aleksov at col 3, ln 60–67.
Mohammed further teaches:
6. The semiconductor package of claim 1, wherein the number of differently-sized solder joints (24b) are included adjacent an edge of the substrate, fig. 8.
7. The semiconductor package of claim 6, wherein the number of differently-sized solder joints (24b) are included at a corner region of the substrate, fig. 8.
8. The semiconductor package of claim 1, wherein the more than one different second shape comprises one of an L shape, a cross shape, a triangle shape, or a square shape (e.g. see square in fig. 10).
Regarding claim 9:
Camacho further teaches:
9. The semiconductor package of claim 1, wherein the array of solder joints comprises a land grid array (LGA) structure, para. [0038].
Regarding claim 10:
Camacho further teaches:
10. The semiconductor package of claim 1, wherein the array of solder joints comprises a ball grid array (BGA) structure, para. [0038].
Regarding claim 11:
Camacho teaches conductive pads (e.g. rectangular pads directly above 112) bonded to the number of solder joints (112), wherein the conductive pads receive electrical signals, fig. 4c.
Camacho does not expressly teach “differently-sized”
Mohammed teaches this limitation as applied to claim 1 above.
Specifically, Mohammed teaches:
conductive pads (e.g. see pads in figs. 8 and 9) bonded to the number of differently-sized solder joint joints (24a, 24b), wherein the conductive pad receives conductive pads receive electrical signals (e.g. signals at para. [0017], [0094])
Regarding claim 13:
Camacho, Aleksov and Mohammed teach the limitations as applied to claim 1 above.
Camacho further teaches the added limitation:
13. An electronic device comprising:
a printed circuit board (PCB) (52) coupled to the package substrate (106), at least one of the package substrate and the PCB having bonded thereto…, fig. 4c.
Regarding claim 14:
Camacho, Aleksov and Mohammed teach the limitations as applied to claim 3 above.
Regarding claim 15:
Camacho, Aleksov and Mohammed teach the limitations as applied to claim 11 above.
Regarding claim 17:
Camacho, Aleksov and Mohammed teach the limitations as applied to claim 9 above.
Regarding claim 18:
Camacho, Aleksov and Mohammed teach the limitations as applied to claims 2 and 8 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Camacho with the teachings of Aleksov because forming larger solder joints close to a center location of the substrate means they “…are less susceptible to solder joint failure due to their location and size”. See Aleksov at col 3, ln 60–67.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Camacho with the teachings of Mohammed because solder joints having a large width will reduce parasitic resistance and inductance of the electrical path and improve electrical performance as well as will improve the thermal performance of the package and reduce the thermal resistance. See Mohammed at para. [0019] – [0020], also see para. [0055].
Claim(s) 12 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Camacho, Aleksov and Mohammed, as applied to claims 1 and 13 above, in view of Hoshino, JP 2003110060 A (of record, see attached English machine translation).
Regarding claims 12 and 16:
Camacho, Aleksov and Mohammed teach the limitations as applied to claim 11 above.
Camacho does not expressly teach:
wherein the conductive pads are dummy pads that do not receive electrical signals.
In an analogous art, Hoshino teaches:
(see fig. 10) wherein the conductive pads (19’) are dummy pads that do not receive electrical signals. See English machine translation at page 4.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Camacho with the teachings of Hoshino because a dummy land can “…improve the solder bonding strength. This measure intends to increase the area of the joint by soldering and reduce the stress applied to the unit area of the joint to prevent breakage.” See Hoshino at page 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
27 February 2026