DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Mar. 5th 2026 has been entered. Claims 1-6 and 8-17 remain pending in the application. Claims 1-6 and 8-9 are examined in this office action. Claims 10-17 are withdrawn from further consideration. Applicant’s amendments to the Claims, Drawing and Specification have overcome each and every objection and 112 rejection previously set forth in the Non-Final Office Action mailed on Dec. 11th 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 and 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "each of the memory cells comprising the transistor" in line 16. There is insufficient antecedent basis for this limitation in the claim. It is unclear here whether the multiple memory cells comprise the (same) transistor OR each memory cell comprise (one of) the transistor(s). For examination purposes, examiner has interpreted " each of the memory cells comprising (one of) the transistor" to be read as “each of the memory cells comprising the transistor”. Claim 2-6 and 8-9 would also be rejected under 35 U.S.C. 112(b) because they are dependent on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20200388712) in view of Lee et al. (US 20190164985).
Regarding claim 1, Liu teaches a semiconductor device (Abstract) comprising: an insulating layer (Annotated fig. 8, the insulating layer on the right side as the dash marked parallelogram, it is parallel to a sidewall of a gate dielectric layer 714/214; para. 0029), a transistor (FET of access devices 805, like 805-1-3; para. 0033, 0071) located on the insulating layer (the insulating layer) and a conductive structure (conductive contact lines 811-0; para. 0071),
the transistor (fig. 7-2, in an alternative view of inside, FET of triple gate access devices 705-1 as 805-1-3; para. 0067) comprising a source (source/drain 732-1; para. 0068), a channel (vertical pillar 713-1; para. 0068) and a drain (portion of polySi portion 719 as source/drain below 713-1; para. 0068) arranged in parallel (along vertical), and a gate dielectric layer (gate dielectric 714-1/214; para. 0029) along a first direction (vertical direction as 1st direction) which is parallel to the insulating layer (Annotated fig. 8, insulating layer on the right side is parallel to vertical direction), and a gate structure (gate 707-2/207; para. 0029), the gate dielectric layer (714-1) being located between the gate structure (707-2) and the channel (713-1); and
the conductive structure (fig. 7-1, conductive contact material 711 as 811-0; para. 0067) covering one sidewall (right side) of the channel (713-1) and being used for grounding (conductive contact 711/211 may be set at a ground voltage; para. 0035), and
the gate structure (707-2) being disposed around the other three sidewalls of the channel (three sidewalls of 713-1), and the gate structure (707-2) and the conductive structure (711) being isolated from each other (isolated by nitride material 725/225 to insulation of the sidewall gates; para. 0042);
a memory cell array (Annotated fig. 8, structured memory array 835; para. 0071) comprising a plurality of memory cell rows (memory cell 100 for each access device 105/805 rows along 811-0, 811-1, 811-2; para. 0030) spaced apart from each other along a second direction (2nd direction) and a plurality of memory cell columns (memory cell for 805 columns along 2nd direction along 805-?-3, 805-?-2, 805-?-1 and 805-?-0) spaced apart from each other along a third direction (3rd direction), the second direction (2nd direction) being parallel to the insulating layer (the insulating layer on the right side), the third direction (3rd direction) being perpendicular to the insulating layer (insulating layer on the right side), each of the memory cell rows (rows along 811) comprising a plurality of memory cells (cells of 805) arranged in parallel along the third direction (3rd direction), each of the memory cell columns (columns along 2nd direction) comprising a plurality of memory cells (cells of 805) arranged in parallel along the second direction (2nd direction), and each of the memory cells (cells of 805) comprising the transistor (FET of 805);
a plurality of word lines (access line 808-0, 808-1, 808-2, 808-3, 808-4, 808-5; para. 0072) spaced apart from each other along the second direction (2nd direction), respectively coupled to the gate structures (707) of a plurality of the transistors (FET of 805) included in the memory cell rows (rows along 811); and
a plurality of bit lines (digit line 820-1, 820-2, 820-3; para. 0072) spaced apart away each other along the third direction (3rd direction), respectively coupled to the drains (819) of a plurality of the transistors (FET of 805) included in the memory cell columns (columns along 2nd direction);
Liu fails to explicitly teach the memory cell arrays arranged along the first direction, and each adjacent two of the memory cell arrays are symmetric relative to a plane defined by the second direction and the third direction.
However, Lee teaches the memory cell arrays (Lee: fig. 13, first stack structure SS1, second stack structure SS2; para. 0070, similar to 835 of Liu) arranged along the first direction (Lee: second direction D2; para. 0074, similar to 2nd direction), and each adjacent two of the memory cell arrays (Lee: semiconductor patterns SP; para. 0070, similar to 805 of Liu) are symmetric (Lee: mirror-symmetric; para. 0072) relative to a plane (Lee: plane of common source line CSL; para. 0070) defined by the second direction and the third direction (Lee: first direction D1 and third direction D3; para. 0074).
Lee and Liu are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the memory cell arrays with the symmetric memory cell arrays as taught by Lee.
Doing so would realize a double side structure to improve integration and their performance and provide lower manufacturing costs (Lee: para. 0003).
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(Annotated fig. 8)
Regarding claim 2, Liu in view of Lee further teaches the semiconductor device according to claim 1,
the conductive structure (Liu: fig. 7-2, 711 as 811-0) is located between the channels (Liu: 713-1, 713-2) of two of the transistors (Liu: FET of 705-1/805-1-3, 705-2/805-2-3) arranged in parallel along the second direction (2nd direction), and is electrically connected (directly connected) with both the channels (Liu: 713-1, 713-2) of two of the transistors (Liu: FET of 705-1/805-1-3, 705-2/805-2-3) arranged in parallel along the second direction (2nd direction).
Regarding claim 3, Liu in view of Lee further teaches the semiconductor device according to claim 1,
the conductive structure (Liu: fig. 7-2, 711 as 811-0) is located at the same side of the channels (Liu: same right side of 713) of two of the transistors (Liu: FET of 805-1-3, 805-1-2) arranged in parallel along the third direction (3rd direction), and is electrically connected (Liu: connected at right side) with both the channels (Liu: 713) of the two of the transistors (Liu: FET of 805-1-3, 805-1-2) arranged in parallel along the second direction (2nd direction) which is parallel to the insulating layer.
Regarding claim 5, Liu in view of Lee further teaches the semiconductor device according to claim 1, wherein along a second direction (Liu: fig. 7-2, vertical direction) parallel to the insulating layer (Liu: the insulating layer), the channel (Liu: 713-1) comprises a first part (middle part) and a second part (top and bottom part), wherein,
in a plane (Liu: fig. 7-2, the cross section) parallel to the insulating layer (Liu: Annotated fig. 8, the cross section parallel to the insulating layer on the right side), a projection of the first part (Liu: middle part of 713-1 next to 707-2) is located in a projection of the gate structure (Liu: 707-2), and a projection of the second part (Liu: top and bottom part of 713-1) is located outside the projection of the gate structure (Liu: 707-2); and
in a third direction (Liu: 3rd direction along 711) perpendicular to the insulating layer (Liu: the insulating layer), a dimension (size) of the first part (Liu: middle part of 713-1) is smaller than (Liu: area of middle part of 713-1 is smaller than total of area of top and bottom part of 713-1) a dimension (size) of the second part (Liu: top and bottom part of 713-1).
Regarding claim 6, Liu in view of Lee further teaches the semiconductor device according to claim 1, wherein,
the transistor (Liu: fig. 7-2, FET of 705-1) is N-type (Liu: N-type FET as 713-1/213 is P+ Si; para. 0034); and
a composition material of the conductive structure (Liu: 711/211) comprises a P-type semiconductor material (Liu: P+ Si; para. 0036).
Regarding claim 8, Liu in view of Lee teaches the semiconductor device according to claim 1, including the memory cells (Liu: fig. 8, cells of 805).
Liu in view of Lee as applied to claim 1 fails to explicitly teach each of the memory cells further comprises a capacitor comprising a first electrode plate, an interelectrode dielectric layer and a second electrode plate, the first electrode plate being in contact with the source, and the interelectrode dielectric layer electrically isolating the first electrode plate and the second electrode plate.
However, Lee teaches each of the memory cells (Lee: fig. 3, 4B, memory cell of channel region CH and second impurity regions SD2; para. 0063, 0047, similar to cell of 805 of Liu) further comprises a capacitor (Lee: fig. 4B, data storage elements DS; para. 0047) comprising a first electrode plate (Lee: first electrodes EL1; para. 0047), an interelectrode dielectric layer (Lee: dielectric layer DL; para. 0047) and a second electrode plate (Lee: second electrode EL2; para. 0047), the first electrode plate (Lee: EL1) being in contact with the source (Lee: SD2), and the interelectrode dielectric layer (Lee: DL is dielectric isolating) electrically isolating the first electrode plate (Lee: EL1) and the second electrode plate (Lee: EL2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a capacitor comprising a first electrode plate, an interelectrode dielectric layer and a second electrode plate as taught by Lee.
Doing so would realize a data storage element with high integrated capacitor only use a space not occupied to improve the integration of the device (Lee: para. 0003, 0086).
Regarding claim 9, Liu in view of Lee further teaches the semiconductor device according to claim 8, wherein,
a shape of the first electrode plate (Lee: fig. 4B, EL1) comprises a cylindrical shape (Lee: cylindrical shape; para. 0048), an axial direction of the first electrode plate (Lee: axial of EL1) being parallel to the first direction (Lee: direction along channel as Liu: vertical direction) which is parallel to the insulating layer (Liu: insulating layer on the right side); and
a shape of the second electrode plate (Lee: EL2) comprises a cylindrical shape (Lee: internal cylinder; para. 0051), an axial direction of the second electrode plate (Lee: axial of EL2) is parallel to the first direction (Lee: direction along channel as Liu: vertical direction), wherein a radius of the second electrode plate (Lee: fig. 4B, radius of EL2 inside EL1) is smaller than a radius of the first electrode plate (Lee: radius of EL1).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Lee as applied to claims 1 above, and further in view of Takesako et al. (US 20190043864).
Regarding claim 4, Liu in view of Lee teaches the semiconductor device structure according to claim 1 including the gate structure (Liu: fig. 7-2, 707-2).
Liu in view of Lee fails to teach the gate structure comprises a connecting layer and a conductive layer, the connecting layer being located between the gate dielectric layer and the conductive layer, and used for increasing an adhesion between the conductive layer and the gate dielectric layer.
However, Takesako teaches the gate structure (Takesako: fig. 5G, conductive layer 23 for gate structure 25; para. 0038, similar to 707-2 of Liu) comprises a connecting layer (Takesako: first conductive layer 21; para. 0038) and a conductive layer (Takesako: second conductive layer 22; para. 0038), the connecting layer (Takesako: 21) being located between the gate dielectric layer (Takesako: gate dielectric layer 19; para. 0038) and the conductive layer (Takesako: 22), and used for increasing an adhesion (Takesako: as adhesive layer; para. 0038) between the conductive layer (Takesako: 22) and the gate dielectric layer (Takesako: 19).
Takesako, Lee and Liu are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the connecting layer being located between the gate dielectric layer and the conductive layer as taught by Takesako.
Doing so would realize an adhesive layer to improve adhesion and barrier between gate electrode and gate dielectric layer (Takesako: para. 0038).
Response to Arguments
Applicant’s arguments of prior art rejections (35 USC 102/35 USC 103) with respect to claims 1-6 and 8-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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