DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 05/18/2026, with respect to the rejection of claims 2, 11 and 15-16 under 35 U.S.C. 112(b) have been fully considered and are persuasive. The rejection of claims 2, 11 and 15-16 has been withdrawn.
Applicant’s arguments, see remarks, filed 05/18/2026, with respect to the rejection(s) of claim(s) 1-4, 6-7, 9-10 and 14-18 under 35 U.S.C. 102 and 103 with reference US-20240222215-A1 to Chen et al. have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US-20250349642-A1 to Wang et al.
Applicant's arguments filed 05/18/2026 with respect to the rejection(s) of claim(s) 1 and 11-13 under 35 U.S.C. 102 with reference US-20250349642-A1 to Wang et al have been fully considered but they are not persuasive. Fig.26 of Wang does appear to depict hybrid bonding, as chips 50A are directly bonded to substrate 120 with no solder components in between. Additionally, the primary fill structure is mapped to both of Wang’s fill structures 104 and 108, so the limitation directed to surrounding a perimeter of a die is met.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 6-7 and 9-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang at al. (US-20250349642-Al – hereinafter Wang).
Regarding claim 1, Wang teaches an integrated circuit (IC) device (Fig.26 100; ¶0029), comprising:
a substrate (Fig.26 120; ¶0057) comprising first metallization features (Fig.26 124; ¶0057) in a first dielectric material (Fig.26 122; ¶0057);
a first IC die (Fig.26 50A left; ¶0029) comprising a first surface (bottom surface) of second metallization features (Fig.26 56A left; ¶0056) in a second dielectric material (Fig.26 52A left; ¶0056) hybrid-bonded (Fig.1J depicts hybrid bonding with a direct connection) to the first metallization features (124) and the first dielectric material (122) in a first region (left region) of the substrate (120);
a second IC die (Fig.26 50A right; ¶0029) adjacent to the first IC die (50A left) and comprising a first surface (bottom surface) of third metallization features (Fig.26 56A right; ¶0056) in a third dielectric material (Fig.26 52A right; ¶0056) hybrid-bonded (Fig.1J depicts hybrid bonding with a direct connection) to the first metallization features (124) and the first dielectric material (122) in a second region (right region) of the substrate (120);
a primary fill structure (Fig.26 104 and 108; ¶0057) in contact with at least the first dielectric material (122) and having an inorganic composition (¶0034), the primary fill structure (104 and 108) surrounding a perimeter of at least the first IC die (50A left, see Fig.29) occupying a majority of a space between the first (50A left) and second (50A right) IC die and adjacent to two or more sidewall edges of at least the first IC die (50A left), but not extending over a second surface (top surface), opposite the first surface (bottom surface), of either of the first (50A left) or second (50A right) IC dies; and
a secondary fill structure (Fig.26 134; ¶0084) in contact with the substrate (120) within a first remnant of the space (Fig.24 132 left; ¶0084) between the primary fill structure (104 and 108) and the two or more sidewall edges of the first IC die (50A left), and within a second remnant (Fig.24 132 right; ¶0084) of the space between the primary fill structure (104 and 108) and the second IC die (50A right).
Regarding claim 2, Wang teaches the IC device of claim 1, wherein the secondary fill structure (134) comprises a physical seam (the centermost line within 134 can be broadly interpreted as an interface) approximately in the middle of each of the first and second remnants (132) of the space.
Regarding claim 3, Wang teaches the IC device of claim 1, wherein the secondary fill structure (134) is in contact with a sidewall of the primary fill structure (104 and 108) and in contact with a sidewall of each of the first (50A left) and second (50A right) IC dies.
Regarding claim 4, Wang teaches the IC device of claim 1, wherein:
the primary fill structure (104 and 108) has a thickness (height) substantially equal to that of the first IC die (50A left) and the majority of the space occupied by the primary fill structure (104 and 108) is at least 500 μm wide (it can be reasonably believed that 104 and 108 total at least 500μm wide; ¶0086); and
at least one of the first or second remnants (132) of the space adjacent to the primary fill structure (104 and 108) is less than 40 μm wide (¶0086).
Regarding claim 6, Wang teaches the IC device of claim 1, wherein:
the primary fill structure (104 and 108) surrounds a perimeter of at least the first IC die (50A; see Fig.29);
the secondary fill structure (134) is within a channel (132) surrounding the perimeter of the first IC die (50A left); and
the secondary fill structure (134) is substantially co-planar with the first IC die (50A left).
Regarding claim 7, Wang teaches the IC device of claim 6, wherein:
the channel (132) is a first channel (132 left);
the primary fill structure (104 and 108) surrounds a perimeter of the second IC die (50A right);
the secondary fill structure (134) is within a second channel (132 right) surrounding the perimeter of the second IC die (50A right);
the secondary fill structure (134) is substantially co-planar with the second IC die (50A right); and
the primary fill structure (104 and 108) is contiguous between the first and second channels (132).
Regarding claim 9, Wang teaches the IC device of claim 1, wherein a top surface of the primary fill structure (104 and 108) is substantially co-planar with the second surface (top surface) of at least one of the first IC die (50A left) or second IC die (50A right).
Regarding claim 10, Wang teaches the IC device of claim 9, wherein the top surface of the primary fill structure (104 and 108) is substantially co-planar with a top surface of the secondary fill structure (134).
Regarding claim 11, Wang teaches the IC device of claim 1, wherein the primary fill structure (104 and 108) has a higher silicon or metal content (primary fill structure can be silicon oxide ¶0034, secondary fill structure can be an organic resin ¶0084) than the secondary fill structure (134).
Regarding claim 12, Wang teaches the IC device of claim 11, wherein the primary fill structure (104 and 108) comprises predominantly silicon (¶0034), predominantly silicon and carbon, or predominantly a metal.
Regarding claim 13, Wang teaches the IC device of claim 11, wherein the secondary fill structure (134) comprises a greater amount of one or more of a metal, nitrogen (134 could be a polyimide, which comprises more nitrogen than silicon oxide), or oxygen than the primary fill structure (104 and 108).
Regarding claim 14, Wang teaches the IC device of claim 1, wherein the primary fill structure (104 and 108) is directly bonded to the substrate (120).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
Regarding claim 16, Wang teaches a system (Fig.37 200; ¶0112) comprising:
a host component (Fig.37 202; ¶0112); and
a composite integrated circuit (IC) device (Fig.37 100; ¶0112) package attached to the host component (202) by interconnect features comprising solder (Fig.26 126; ¶0112), the composite IC device (100) comprising:
a first IC die (Fig.26 50A left; ¶0029) comprising a first surface (bottom surface) bonded to a first region (left region) of a substrate (Fig.26 120; ¶0057);
a second IC die (Fig.26 50A right; ¶0029) adjacent to the first IC die (50A left) and comprising a first surface (bottom surface) bonded to a second region (right region) of the substrate (120);
a primary fill structure (Fig.26 104 and 108; ¶0057), the primary fill structure (104 and 108) adjacent to two or more sidewall edges of at least the first IC die (50A left) and over a third region (center region) of the substrate (120) comprising a majority of a space between the first (50A left) and second (50A right) IC dies, wherein the primary fill structure (104 and 108) is absent from over a second surface (top surface), opposite the first surface (bottom surface), of either of the first (50A left) or second (50A right) IC dies; and
a secondary fill structure (Fig.26 134; ¶0084) within a first remnant (Fig.24 132 left; ¶0084) of the space between the primary fill structure (104 and 108) and the two or more sidewall edges of the first IC die (50A left), and within a second remnant (Fig.24 132 right; ¶0084) of the space between the primary fill structure (104 and 108) and the second IC die (50A right), wherein the secondary fill structure (134) comprises a dielectric material (¶0084).
Wang does not teach wherein the primary fill structure is comprising monocrystalline silicon.
However, Wang does teach pure silicon substrates within the IC dies (¶0023), which comprise through-silicon vias (TSVs).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the primary fill structure (104 and 108) to be made of pure silicon instead of silicon oxide to arrive at the claimed invention. This modification is obvious because it is a well-known substrate option for producing TSVs to potentially connect the substrate (120) to the upper chip (Fig.26 50B; ¶0085) depicted in Figure 26.
Regarding claim 17, Wang teaches the system of claim 16, further comprising a power supply (a coupled power supply is inherent to all semiconductor devices) coupled to provide power to the composite IC die package (100) through the host component (202).
Regarding claim 18, Wang teaches the system of claim 16, wherein:
the first IC die (50A left) is a first of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry (¶0022); and
the second IC die (50A right) is a second of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry (¶0022).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Yu et al. (US-20200185330-Al – hereinafter Yu).
Regarding claim 15, Wang teaches the IC device of claim 1.
Wang does not teach the IC device further comprising one or more through vias embedded within the primary fill structure and directly bonded to interconnect features of the substrate, and wherein a top surface of the through vias are substantially co-planar with a second surface of the primary fill structure, opposite the substrate.
Yu teaches through vias (Fig.17 141; ¶0054 of Yu) that are embedded in a primary fill structure (Fig.17 143; ¶0056 of Yu) and directly bonded to an interconnect structure (Fig.17 148; ¶0058), wherein the vias (141 of Yu) are planar with the top of the primary fill structure (143 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the vias of Yu (Fig.17 of Yu) to the device taught by Chen (Fig.1J of Chen) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of connecting a substrate (like that of PM1-3 of Chen) directly to a higher chip (Fig.17 279; ¶0063 of Yu) above a first layer of chips (like that of 200 and 300 of Chen). This is depicted in Fig.17 of Yu where vias 141 couple interconnect 148 directly to chip 279 through primary fill structure 143, with the vias bypassing a lower chip (Fig.17 100; ¶0021 of Yu).
Allowable Subject Matter
Claims 25-29 are allowed.
Regarding claim 25, the most relevant prior art reference US-20250349642-A1 to Wang et al. teaches most of the limitations of claim 25, but not the limitations of “wherein the secondary fill structure has a different width between the two or more sidewall edges of the first IC die and two or more corresponding sidewall edges of the primary fill structure that face the sidewall edges of the first IC die” as recited. Therefore, claim 25 is deemed patentable over the prior art.
Claims 26-29 are allowed for depending from allowable claim 25.
Claims 5 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the most relevant prior art reference US-20250349642-A1 to Wang et al. teaches most of the limitations of claim 5, but not the limitations of “wherein a width of the first and second remnants of the space are unequal by at least 50% of the smaller of the first or second remnants” as recited. Therefore, claim 5 is deemed patentable over the prior art.
Regarding claim 8, the most relevant prior art reference US-20250349642-A1 to Wang et al. teaches most of the limitations of claim 8, but not the limitations of “wherein the secondary fill structure has a different width between the two or more sidewall edges of the first IC die and two or more corresponding sidewall edges of the primary fill structure that face the sidewall edges of the first IC die” as recited. Therefore, claim 8 is deemed patentable over the prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights