Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/08/2026 has been entered.
Claim status
Claim 10 has been canceled.
Claims 15-20 are withdrawn.
Claims 1 and 9 have been amended.
Claims 1-9, 11-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9, 11-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues both Gao and Park fail to disclose "wherein at least one of the plurality of cutting structures CS protrudes beyond a bottom surface of one of the channel structures (P1 and P2)" of independent Claims 1 and 9 of the present application.
This argument is moot as the new ground of rejection is based on a new prior art Lee et al. (US 20200343307 A1), as described below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al. (US 20220123013 A1; hereinafter “Gao”) in view of Lee et al. (US 20200343307 A1; hereinafter “Lee”).
In re claim 1, Gao discloses a semiconductor device (figs. 1, 9A-9C) comprising:
gate structure including conductive layers 12 and insulating layers 14, which are alternately stacked (¶40);
a plurality of channel structures 206 (¶55) penetrating the gate structure, the plurality of channel structures 206 being arranged in a first direction Y (e.g., a first direction has been interpreted as a horizontal direction of the base 10);
a plurality of cutting structures 910, 201, 801, 901 (¶123-126) each isolating each of the plurality of channel structures 206, respectively, into a plurality of divided channel structures 206A-206D while penetrating each of the plurality of channel structures 206, respectively; and
wherein each of the plurality of cutting structures 910, 201, 801, 901 has substantially a cross (+) shape including extension parts 201, 801, 901 extending in directions oblique to the first direction (e.g., a cross shape formed by the cutting structures 910, 201, 801, 901 in E-E’ and F-F’ direction, which is oblique to Y or G-G’ direction).
Gao does not expressly disclose a plurality of interconnection lines located over the gate structure and extending in the first direction, wherein at least one of the plurality of cutting structures protrudes beyond a bottom surface of one of the channel structures.
In the same field of endeavor, Lee discloses in figs. 1, 12-13, a semiconductor device, wherein a plurality of interconnection lines 67 located over the gate structure W1-Wn and extending in the first direction (X) (¶29), and wherein at least one of the plurality of cutting structures 148 protrudes beyond a bottom surface of one of the channel structures 143 (¶59).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Lee and form a plurality of interconnection lines located over the gate structure and extending in the first direction in Gao to connect channels to global bit lines via local bit line contacts and provide a compact layout design.
Furthermore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Lee and form at least one of the plurality of cutting structures of Gao protruding beyond a bottom surface of one of the channel structures to provide a semiconductor memory device, which is advantageous to high integration density and exhibits low power consumption, a method of operating the device, and a method of forming the device (¶4-9, 59 of Lee).
In re claim 2, Gao, as modified Lee, discloses the semiconductor device of claim 1.
Gao further discloses in figs. 1, 9A-9C, wherein each of the plurality of cutting structures 910, 201, 801, 901 extending in a vertical direction Z respectively penetrates each of the plurality of channel structures 206, and isolates each of the plurality of channel structures into a first divided channel structure 206A, a second divided channel structure 206B, a third divided channel structure 206C, and a fourth divided channel structure 206D by the extension parts 201, 801, 901 extending in the oblique directions (E-E’ and F-F’).
In re claim 3, Gao, as modified by Lee, discloses the semiconductor device of claim 2.
Gao further discloses in figs. 1, 9A-9C, wherein the first divided channel structure 206A is symmetrical to the second divided channel structure 206B adjacent thereto in the oblique direction E-E’ with respect to the cutting structure 910, 201D, 801D, 901D, and the fourth divided channel structure 206D is symmetrical to the third divided channel structure 206C adjacent thereto in the oblique direction E-E’ with respect to the cutting structure 910, 201C, 801C, 901C.
In re claim 4, Gao, as modified by Lee, discloses the semiconductor device of claim 1.
Gao further discloses in figs. 1, 9A-9C, further comprising a plurality of contacts 214A-214D respectively connected to upper surfaces of the plurality of divided channel structures 2016A-206D (¶0058).
In re claim 5, Gao, as modified by Lee, discloses the semiconductor device of claim 4, wherein the plurality of contacts (Gao: 214A-214D) electrically connect the plurality of divided channel structures (Gao: 206A-206D) and the plurality of interconnection lines (modified by Park’s interconnection lines 978) to each other (Park: figs. 1-14, 28A and Gao: 1, 9A-9C).
In re claim 6, Gao, as modified by Lee, discloses the semiconductor device of claim 4.
Gao further discloses in figs. 1, 9A-9C, wherein the plurality of contacts 214A-214D are disposed at different levels of a second direction X, the second direction being a vertical direction of the first direction Y (e.g., in a top view, contacts 214A, 214C are at different levels than 214B, 214D).
In re claim 8, Gao, as modified by Lee, discloses the semiconductor device of claim 1.
Gao further discloses in figs. 1, 9A-9C, wherein each of the channel structures 206 includes a plurality of channel layers 206A-206D isolated from each other by the cutting structure 910, 201, 801, 901.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao, as modified by Lee, as applied to claim 6 above, and further in view of Okina et al. (US 20230284443 A1; hereinafter “Okina”).
In re claim 7, Gao, as modified by Lee, discloses the semiconductor device of claim 6 outlined above, but does not expressly disclose a drain select line isolation structure extending in the second direction while penetrating at least one conductive layer disposed at an uppermost portion among the alternately stacked conductive layers.
In the same field of endeavor, Okina discloses a semiconductor device (figs. 1-12) comprising a drain select line isolation structure 72 extending in a second direction while penetrating at least one conductive layer 46 disposed at an uppermost portion among the alternately stacked conductive layers 46 (¶71, 105).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Okina into the device of Gao/Lee to isolate neighboring memory arrays.
Claim(s) 9, 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao in view of Lee and Kang et al. (US 20230189524 A1; hereinafter “Kang”).
In re claim 9, Gao discloses a semiconductor device (figs. 1, 9A-9C) comprising:
gate structure including conductive layers 12 and insulating layers 14, which are alternately stacked (¶40);
a plurality of channel structures 206 (¶55) penetrating the gate structure, the plurality of channel structures 206 being arranged in a first direction Y (e.g., a first direction has been interpreted as a horizontal direction of the base 10);
a plurality of cutting structures 910, 201, 801, 901 (¶123-126) each isolating each of the plurality of channel structures 206, respectively, into a plurality of divided channel structures 206A-206D while penetrating each of the plurality of channel structures 206, respectively; and
wherein the cutting structure 910, 201, 801, 901 includes extension parts 201, 801, 901 extending in directions oblique to the first direction Y (e.g., a cross shape formed by the cutting structures 910, 201, 801, 901 in E-E’ and F-F’ direction, which is oblique to Y or G-G’ direction).
Gao does not expressly disclose a plurality of interconnection lines located over the gate structure and extending in the first direction, wherein at least one of the plurality of cutting structures protrudes beyond a bottom surface of one of the channel structures.
In the same field of endeavor, Lee discloses in figs. 1, 12-13, a semiconductor device, wherein a plurality of interconnection lines 67 located over the gate structure W1-Wn and extending in the first direction (X) (¶29), and wherein at least one of the plurality of cutting structures 148 protrudes beyond a bottom surface of one of the channel structures 143 (¶59).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Lee and form a plurality of interconnection lines located over the gate structure and extending in the first direction in Gao to connect channels to global bit lines via local bit line contacts and provide a compact layout design.
Furthermore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Lee and form at least one of the plurality of cutting structures of Gao protruding beyond a bottom surface of one of the channel structures to provide a semiconductor memory device, which is advantageous to high integration density and exhibits low power consumption, a method of operating the device, and a method of forming the device (¶4-9, 59 of Lee).
Gao, as modified by Lee, does not expressly disclose wherein the cutting structure has substantially a Y shape.
In the same field of endeavor, Kang discloses a semiconductor device (figs. 1-7) wherein a cutting structure CS1 through the gate stack has substantially a Y shape (¶62).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kang into the device of Gao/Lee to satisfy the need of increasing the degree of integration of semiconductor memory devices and provide improved reliability (¶3-5 of Kang).
In re claim 11, Gao, as modified by Lee and Kang, discloses the semiconductor device of claim 9.
Gao further discloses in figs. 1, 9A-9C, wherein the cutting structure 910, 201, 801, 901 extending in a vertical direction Z isolates a first divided channel structure 206A, a second divided channel structure 206B, and a third divided channel structure 206C from each other by allowing the first divided channel structure 206A, the second divided channel structure 206B, and the third divided channel structure 206C to be spaced apart from each other by the extension parts 201, 801, 901 extending in the oblique directions (E-E’ and F-F’).
In re claim 12, Gao, as modified by Lee and Kang, discloses the semiconductor device of claim 11.
Gao further discloses in figs. 1, 9A-9C, wherein the first divided channel structure 206A is symmetrical to the second divided channel structure 206B adjacent thereto in the oblique direction E-E’ with respect to the cutting structure 910, 201D, 801D, 901D.
In re claim 13, Gao, as modified by Lee and Kang, discloses the semiconductor device of claim 9 outlined above. Gao does not expressly disclose wherein the cutting structure has substantially an asterisk (*) shape.
In the same field of endeavor, Park discloses a semiconductor device (fig. 28A) wherein the cutting structure has substantially an asterisk (*) shape (¶99).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Park into the device of Gao/Lee/Kang to allow the density of memory cells in the array to be increased (¶79 of Park).
In re claim 14, Gao, as modified by Lee, Kang and Park (fig. 28A), discloses the semiconductor device of claim 13, wherein the cutting structure (Gao’s cutting structure 910, 201, 801, 901 modified by the shape of Park’s cutting trench 960 shown in fig. 28A) extending in a vertical direction isolates six divided channel structures (Park: 962a through 962f) from each other by allowing the six divided channel structures to be spaced apart from each other by the extension parts (Park: 960) extending in the oblique directions.
Conclusion
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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