Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 11/11/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-9 and 11-20. Claims 15-20 remain as withdrawn. Claims 1-9 and 11-14 have been examined on the merits in this Office action.
Response to Arguments
Applicant's arguments filed 11/11/2025 have been fully considered but they are not persuasive.
Applicant asserts the secondary art, Park discloses bit lines 974 corresponding to the interconnection lines. However, the arrangement between the bit lines 974 and the trenches 960 differs from that of the present application. Referring to FIGs. 27A and 27B of Park, above, while the trench 960 is formed in a cross (+) shape, the bit line 974 is arranged either parallel or perpendicular to the trench 960, and Park does not disclose any bit line arranged obliquely with respect to the cross-shaped trench 960. Accordingly, neither Gao nor Park discloses or suggests the features of Independent Claim 1 of the present application.
Examiner respectfully disagrees.
Applicant argued adding Park’s figures 26A-27B, that Park does not teach any bit line arranged obliquely with respect to the cross-shaped trench 960.
However, as described in the 08/11/2025 Non-Final Office action, Examiner relied on fig. 28A of Park to teach the plurality of interconnection lines 978. As describe in the rejection of claim 1 below, Park does disclose the plurality of interconnection lines 978 located over the gate structure WL-WL31 and extending in the first direction (i.e., a horizontal direction of the base 10) (¶78). In fig. 28A, the plurality of interconnection lines 978 extend in east-west direction. Park also discloses in fig. 28A, the plurality of interconnection lines 978 are arranged obliquely with respect to the trenches 960 (here, four obliquely trenches 960 have been mapped to the cutting structure).
Therefore, Gao as modified by Park discloses the features of Independent Claim 1 of the present application and the previously applied rejection of claims 1-8 have been maintained below.
Applicant further asserts:
Neither Gao nor Park discloses or suggests any cutting structure having a Y-shaped configuration. Meanwhile, the Y-shaped cutting structure CS1 disclosed in Kang merely serves to define memory block units, and there is no disclosure in Kang that the vertical channel structure VS is divided by the Y-shaped cutting structure CS1.
Therefore, since the cutting structure CS1 in Kang is limited to separating
memory block units, the combination of Gao, Park, and Kang fails to disclose or suggest the features of amended Independent Claim 9 of the present application.
Examiner respectfully disagrees.
Primary art, Gao teaches in figs. 1, 9A-9C, the vertical channel structure 206 is divided by the cutting structure 910, 201, 801, 901. Secondary art, kang has been relied on for the shape of the cutting structure CS1. Thus, the combination of Gao with Park and Kang would teach the claimed invention of claim 9 as explained below.
Furthermore, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The previously applied rejection of claims 9, 11-14 have been maintained below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al. (US 20220123013 A1; hereinafter “Gao”) in view of Park et al. (US 20160099254 A1; hereinafter “Park”).
In re claim 1, Gao discloses a semiconductor device (figs. 1, 9A-9C) comprising:
gate structure including conductive layers 12 and insulating layers 14, which are alternately stacked (¶40);
a plurality of channel structures 206 (¶55) penetrating the gate structure, the plurality of channel structures 206 being arranged in a first direction Y (e.g., a first direction has been interpreted as a horizontal direction of the base 10);
a plurality of cutting structures 910, 201, 801, 901 (¶123-126) each isolating each of the plurality of channel structures 206, respectively, into a plurality of divided channel structures 206A-206D while penetrating each of the plurality of channel structures 206, respectively; and
wherein each of the plurality of cutting structures 910, 201, 801, 901 has substantially a cross (+) shape including extension parts 201, 801, 901 extending in directions oblique to the first direction (e.g., a cross shape formed by the cutting structures 910, 201, 801, 901 in E-E’ and F-F’ direction, which is oblique to Y or G-G’ direction).
Gao does not expressly disclose a plurality of interconnection lines located over the gate structure 12, 14 and extending in the first direction Y.
In the same field of endeavor, Park discloses a semiconductor device (figs. 1-14, 28A) a plurality of interconnection lines 978 located over the gate structure WL-WL31 and extending in the first direction (i.e., a horizontal direction of the base 10) (¶78).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kang into the device of Gao to connect channels to global bit lines via local bit line contacts and provide a compact layout design.
In re claim 2, Gao, as modified by Park, discloses the semiconductor device of claim 1.
Gao further discloses in figs. 1, 9A-9C, wherein each of the plurality of cutting structures 910, 201, 801, 901 extending in a vertical direction Z respectively penetrates each of the plurality of channel structures 206, and isolates each of the plurality of channel structures into a first divided channel structure 206A, a second divided channel structure 206B, a third divided channel structure 206C, and a fourth divided channel structure 206D by the extension parts 201, 801, 901 extending in the oblique directions (E-E’ and F-F’).
In re claim 3, Gao, as modified by Park, discloses the semiconductor device of claim 2.
Gao further discloses in figs. 1, 9A-9C, wherein the first divided channel structure 206A is symmetrical to the second divided channel structure 206B adjacent thereto in the oblique direction E-E’ with respect to the cutting structure 910, 201D, 801D, 901D, and the fourth divided channel structure 206D is symmetrical to the third divided channel structure 206C adjacent thereto in the oblique direction E-E’ with respect to the cutting structure 910, 201C, 801C, 901C.
In re claim 4, Gao, as modified by Park, discloses the semiconductor device of claim 1.
Gao further discloses in figs. 1, 9A-9C, further comprising a plurality of contacts 214A-214D respectively connected to upper surfaces of the plurality of divided channel structures 2016A-206D (¶0058).
In re claim 5, Gao, as modified by Park, discloses the semiconductor device of claim 4, wherein the plurality of contacts (Gao: 214A-214D) electrically connect the plurality of divided channel structures (Gao: 206A-206D) and the plurality of interconnection lines (modified by Park’s interconnection lines 978) to each other (Park: figs. 1-14, 28A and Gao: 1, 9A-9C).
In re claim 6, Gao, as modified by Park, discloses the semiconductor device of claim 4.
Gao further discloses in figs. 1, 9A-9C, wherein the plurality of contacts 214A-214D are disposed at different levels of a second direction X, the second direction being a vertical direction of the first direction Y (e.g., in a top view, contacts 214A, 214C are at different levels than 214B, 214D).
In re claim 8, Gao, as modified by Park, discloses the semiconductor device of claim 1.
Gao further discloses in figs. 1, 9A-9C, wherein each of the channel structures 206 includes a plurality of channel layers 206A-206D isolated from each other by the cutting structure 910, 201, 801, 901.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao, as modified by Park, as applied to claim 6 above, and further in view of Okina et al. (US 20230284443 A1; hereinafter “Okina”).
In re claim 7, Gao, as modified by Park, discloses the semiconductor device of claim 6 outlined above, but does not expressly disclose a drain select line isolation structure extending in the second direction while penetrating at least one conductive layer disposed at an uppermost portion among the alternately stacked conductive layers.
In the same field of endeavor, Okina discloses a semiconductor device (figs. 1-12) comprising a drain select line isolation structure 72 extending in a second direction while penetrating at least one conductive layer 46 disposed at an uppermost portion among the alternately stacked conductive layers 46 (¶71, 105).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Okina into the device of Gao/Park to isolate neighboring memory arrays.
Claim(s) 9, 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao, as modified by Park, as applied to claim 9 above, and further in view of Kang et al. (US 20230189524 A1; hereinafter “Kang”).
In re claim 9, Gao discloses a semiconductor device (figs. 1, 9A-9C) comprising:
gate structure including conductive layers 12 and insulating layers 14, which are alternately stacked (¶40);
a plurality of channel structures 206 (¶55) penetrating the gate structure, the plurality of channel structures 206 being arranged in a first direction Y (e.g., a first direction has been interpreted as a horizontal direction of the base 10);
a plurality of cutting structures 910, 201, 801, 901 (¶123-126) each isolating each of the plurality of channel structures 206, respectively, into a plurality of divided channel structures 206A-206D while penetrating each of the plurality of channel structures 206, respectively; and
wherein the cutting structure 910, 201, 801, 901 includes extension parts 201, 801, 901 extending in directions oblique to the first direction Y (e.g., a cross shape formed by the cutting structures 910, 201, 801, 901 in E-E’ and F-F’ direction, which is oblique to Y or G-G’ direction).
Gao does not expressly disclose a plurality of interconnection lines located over the gate structure 12, 14 and extending in the first direction Y.
In the same field of endeavor, Park discloses a semiconductor device (figs. 1-14, 28A) a plurality of interconnection lines 978 located over the gate structure WL-WL31 and extending in the first direction (i.e., a horizontal direction of the base 10) (¶78).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kang into the device of Gao to connect channels to global bit lines via local bit line contacts and provide a compact layout design.
Gao, as modified by Park, does not expressly disclose wherein the cutting structure has substantially a Y shape.
In the same field of endeavor, Kang discloses a semiconductor device (figs. 1-7) wherein a cutting structure CS1 through the gate stack has substantially a Y shape (¶62).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kang into the device of Gao/Park to satisfy the need of increasing the degree of integration of semiconductor memory devices and provide improved reliability (¶3-5 of Kang).
In re claim 11, Gao, as modified by Park and Kang, discloses the semiconductor device of claim 9.
Gao further discloses in figs. 1, 9A-9C, wherein the cutting structure 910, 201, 801, 901 extending in a vertical direction Z isolates a first divided channel structure 206A, a second divided channel structure 206B, and a third divided channel structure 206C from each other by allowing the first divided channel structure 206A, the second divided channel structure 206B, and the third divided channel structure 206C to be spaced apart from each other by the extension parts 201, 801, 901 extending in the oblique directions (E-E’ and F-F’).
In re claim 12, Gao, as modified by Park and Kang, discloses the semiconductor device of claim 11.
Gao further discloses in figs. 1, 9A-9C, wherein the first divided channel structure 206A is symmetrical to the second divided channel structure 206B adjacent thereto in the oblique direction E-E’ with respect to the cutting structure 910, 201D, 801D, 901D.
In re claim 13, Gao, as modified by Park and Kang, discloses the semiconductor device of claim 9 outlined above. Gao does not expressly disclose wherein the cutting structure has substantially an asterisk (*) shape.
In the same field of endeavor, Park discloses a semiconductor device (fig. 28A) wherein the cutting structure has substantially an asterisk (*) shape (¶99).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kang into the device of Gao to allow the density of memory cells in the array to be increased (¶79 of Park).
In re claim 14, Gao, as modified by Park (fig. 28A) and Kang, discloses the semiconductor device of claim 13, wherein the cutting structure (Gao’s cutting structure 910, 201, 801, 901 modified by the shape of Park’s cutting trench 960 shown in fig. 28A) extending in a vertical direction isolates six divided channel structures (Park: 962a through 962f) from each other by allowing the six divided channel structures to be spaced apart from each other by the extension parts (Park: 960) extending in the oblique directions.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893