DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Group I in the reply filed on Nov. 25 th 2025 is acknowledged. Claims 1- 18 are examined in this office action. Claims 19 - 25 are withdrawn from further consideration. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-4, 12, 14 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20190244947) in view of Kitayama et al. (US 20170213766) and Hsu et al. (US 20190139896). Regarding claim 1 , Yu teaches an integrated circuit (IC) device (Abstract), comprising: a first IC die (fig. 9, first package 503; para. 0052) directly bonded to a first region (left region) of a host substrate (first carrier substrate 601, adhesive layer 603 and polymer layer 605; para. 0053); a second IC die (second package 505; para. 0052) directly bonded to a second region (right region) of the host substrate (601, 603, 605); and a fill (encapsulant 801; para. 0064) within a space (space between 503, 505) between the first and second IC dies. Yu fails to explicitly teach each of the first IC die and second IC die comprises at least one of: a corner, distal from the host substrate, having a radius of curvature exceeding 50 μ m ; or an edge sidewall with a slope that is at least 10° from normal to a plane of the host substrate. However, Kitayama teaches each of the first IC die and second IC die ( Kitayama : fig. 16, semiconductor chip CHP1; para. 0076, similar to 503, 505 of Yu) comprises at least one of: a corner ( Kitayama : corner above angle θ; para. 0076), distal from the host substrate, having a radius of curvature exceeding 50 μ m ; or an edge sidewall ( Kitayama : edge sidewalls of CHP1) with a slope ( Kitayama : slope of angle θ; para. 0076) that is 5° to 65° ( Kitayama : 25° to 85°; para. 0076), which overlaps the angle range at least 10° from normal to a plane (horizontal plane) of the host substrate. Kitayama and Yu are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the edge sidewall with a slope range from 5° to 65° to at least 10° from normal to a plane of the host substrate. Doing so would realize a trapezoidal chip to improve yield of the semiconductor device ( Kitayama : para. 0010). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). In addition, Yu in view of Kitayama fails to explicitly teach the fill comprising at least a first inorganic material. However, Hsu teaches the fill (Hsu: fig. 1C, encapsulant 20; para. 0025, similar to 801 of Yu) comprising at least a first inorganic material (Hsu: silicon oxide besides resin; para. 0025). Hsu, Kitayama and Yu are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the fill comprising at least a first inorganic material as taught by Hsu. Doing so would realize the fill with an alternative well known material with low cost (Hsu: para. 0025). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin , 125 USPQ 416. Regarding claim 2 , Yu in view of Kitayama and Hsu teaches the IC device of claim 1 including the host substrate (Yu: fig. 9, 601, 603, 605). Yu in view of Kitayama and Hsu as applied to claim 1 above fails to explicitly teach the corner has a radius of curvature exceeding 100 μ m or the edge sidewall has a slope that is at least 20° from normal to the plane of the host substrate. However, Kitayama teaches the corner ( Kitayama : fig. 16, corner above angle θ; para. 0076) has a radius of curvature exceeding 100 μ m or the edge sidewall ( Kitayama : edge sidewalls of CHP1) has a slope ( Kitayama : slope of angle θ; para. 0076) that is 5° to 65° ( Kitayama : 25° to 85°; para. 0076), which overlaps the angle range at least 20° from normal to the plane (horizontal plane) of the host substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the edge sidewall with a slope range from 5° to 65° to at least 20° from normal to a plane of the host substrate. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 3 , Yu in view of Kitayama and Hsu teaches the IC device of claim 1, wherein each of the first IC die and second IC die ( Kitayama : fig. 16, CHP1, similar to 503, 505 of Yu) has a trapezoidal cross-section ( Kitayama : CHP1 has a trapezoidal shape). Regarding claim 4 , Yu in view of Kitayama and Hsu teaches The IC device of claim 1 including the first IC die and second IC die (Yu: fig. 9, 503, 505). Yu in view of Kitayama and Hsu as applied to claim 1 above fails to explicitly teach a sidewall with a slope at least 30° from normal to the plane of the host substrate. However, Kitayama teaches a sidewall ( Kitayama : fig. 16, sidewalls of CHP1) with a slope ( Kitayama : slope of angle θ; para. 0076) that is 5° to 65° ( Kitayama : 25° to 85°; para. 0076), which overlaps the angle range at least 30° from normal to the plane (horizontal plane) of the host substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the edge sidewall with a slope range from 5° to 65° to at least 30° from normal to a plane of the host substrate. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 12 , Yu in view of Kitayama and Hsu teaches the IC device of claim 1, wherein the first inorganic material (Hsu: fig. 1C, 20) comprises predominantly silicon and oxygen (Hsu: silicon oxide; para. 0025). Regarding claim 14 , Yu in view of Kitayama and Hsu teaches the IC device of claim 1, wherein: a surface of the fill (Yu: fig. 10, top surface of 801) is substantially co-planar with a surface (top surface) of at least one of the first or second IC dies (Yu: 503 and 505); and a third IC die, a passive interconnect structure (Yu: redistribution structure 1000; para. 0069), or a purely structural member is bonded to a top surface of the fill (Yu: top surface of 801). Regarding claim 15 , Yu teaches a system (Abstract) comprising: a host component (fig. 13 upside down, third package 1301; para. 0091); and a composite integrated circuit (IC) device (device of first package 503, second package 505 and polymer layer 605; para. 0052, 0053) attached to the host component (1301), the composite IC device comprising: a host substrate (605); a first IC (503) bonded to a first region (left region) of a host substrate (605); a second IC die (505) bonded to a second region (right region) of the host substrate (605), a fill (encapsulant 801; para. 0064) within a space (space between 503, 505) between the first and second IC dies; and a third IC die, a passive interconnect structure (redistribution structure 1000; para. 0069), or a purely structural member bonded to a top surface of the fill (top surface of 801). Yu fails to explicitly teach each of the first IC die and second IC die comprises at least one of: a corner, distal from the host substrate, having a radius of curvature exceeding 50 m; or an edge sidewall with a slope that is at least 10° from normal to a plane of the host substrate. However, Kitayama teaches each of the first IC die and second IC die ( Kitayama : fig. 16, semiconductor chip CHP1; para. 0076, similar to 503, 505 of Yu) comprises at least one of: a corner ( Kitayama : corner above angle θ; para. 0076), distal from the host substrate, having a radius of curvature exceeding 50 m; or an edge sidewall ( Kitayama : edge sidewalls of CHP1) with a slope ( Kitayama : slope of angle θ; para. 0076) that is 5° to 65° ( Kitayama : 25° to 85°; para. 0076), which overlaps the angle range at least 10° from normal to a plane (horizontal plane) of the host substrate. Kitayama and Yu are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the edge sidewall with a slope range from 5° to 65° to at least 10° from normal to a plane of the host substrate. Doing so would realize a trapezoidal chip to improve yield of the semiconductor device ( Kitayama : para. 0010). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). In addition, Yu in view of Kitayama fails to explicitly teach the fill comprising at least a first inorganic material. However, Hsu teaches the fill (Hsu: fig. 1C, encapsulant 20; para. 0025, similar to 801 of Yu) comprising at least a first inorganic material (Hsu: silicon oxide besides resin; para. 0025). Hsu, Kitayama and Yu are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the fill comprising at least a first inorganic material as taught by Hsu. Doing so would realize the fill with alternative well known material with low cost (Hsu: para. 0025). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin , 125 USPQ 416. Regarding claim 16 , Yu in view of Kitayama and Hsu teaches the system of claim 15, further comprising: a power supply (Yu: fig. 13, second TIVs 607; para. 0059) coupled to provide power (Yu: connected to external DC power supply; para. 0059) to the composite IC device (Yu: 605, 503, 505) through the host component (Yu: 1301). Regarding claim 17 , Yu in view of Kitayama and Hsu teaches the system of claim 15, wherein the host substrate (Yu: fig. 13, 605) is coupled to the host component (Yu: 1301) through a plurality of first solder interconnects (Yu: fourth external connections 1303; para. 0091). Regarding claim 18 , Yu in view of Kitayama and Hsu teaches the system of claim 15, wherein: the first IC die (fig. 13, 503 has first semiconductor device 101; para. 0024) is a first of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry (memory device, logic device, power device; para. 0024); and the second IC die (505 has second semiconductor device 103; para. 0024) is a second of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry (memory device, logic device, power device; para. 0024). Claim(s) 5-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Kitayama and Hsu as applied to claim 1 above, and further in view of Hatanaka et al. (US 20130250527). Regarding claim 5 , Yu in view of Kitayama and Hsu teaches the IC device of claim 1 including the first IC die and second IC die (Yu: fig. 9, 503, 505). Yu in view of Kitayama and Hsu fails to explicitly teach a barrier layer between the fill and each of the first IC die and second IC die, wherein the barrier layer has a thickness less than 5 μm . However, Hatanaka teaches a barrier layer (Hatanaka: fig. 1B, inorganic insulating layer 5; para. 0020) between the fill (Hatanaka: resin layer 4; para. 0020, similar to 801 of Yu) and each of the first IC die and second IC die (Hatanaka: chip component 2; para. 0020, similar to 503, 505 of Yu), wherein the barrier layer (Hatanaka: 5) has a thickness around 1 μm or more (Hatanaka: 1 μm or more; para. 0076), which overlaps the thickness range less than 5 μm . Hatanaka, Hsu, Kitayama and Yu are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a barrier layer and modified the thickness range from 1 μm or more to less than 5 μm . Doing so would realize a layer to prevent invasion of water vapor and resin into the space of connects and suppress deterioration of the characteristics (Hatanaka: para. 0007, 0043). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 6 , Yu in view of Kitayama , Hsu and Hatanaka teaches the IC device of claim 5 including the barrier layer (Hatanaka: fig. 1B, 5). Yu in view of Kitayama , Hsu and Hatanaka as applied to claim 5 above fails to explicitly teach the barrier layer has a thickness less than 1 μm . However, Hatanaka teaches the barrier layer (Hatanaka: fig. 1B, 5) has a thickness 1 μm or more (Hatanaka: 1 μm or more; para. 0076), which abuts the thickness range less than 1 μm . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness range from 1 μm or more to less than 1 μm . Doing so would realize a thinner layer to reduce material usage and cost . Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 7 , Yu in view of Kitayama , Hsu and Hatanaka teaches the IC device of claim 5, wherein the barrier layer (Hatanaka: fig. 1B, 5) comprises a material (Hatanaka: ceramic material such as alumina; para. 0044) that has modulus of toughness (ceramic alumina is harder than silicon oxide) exceeding that of the first inorganic material (Hsu: silicon oxide; para. 0025). Regarding claim 8 , Yu in view of Kitayama , Hsu and Hatanaka teaches the IC device of claim 5, wherein the barrier layer (Hatanaka: fig. 1B, 5) comprises a material (Hatanaka: 5 includes resin 8; para. 0074) with an organic composition (Hatanaka: organic resin 8; para. 0073). Regarding claim 9 , Yu in view of Kitayama , Hsu and Hatanaka teaches the IC device of claim 8, wherein the barrier layer (Hatanaka: fig. 1B, 5) comprises polyimide (Hatanaka: polyimide resin; para. 0073). Regarding claim 10 , Yu in view of Kitayama , Hsu and Hatanaka teaches the IC device of claim 5, wherein the barrier layer (Hatanaka: fig. 1B, 5) comprises a material (Hatanaka: 5 includes first inorganic particles 7; para. 0074) with an inorganic composition (Hatanaka: first inorganic particles 7; para. 0074). Regarding claim 11 , Yu in view of Kitayama , Hsu and Hatanaka teaches the IC device of claim 10, wherein the barrier layer (Hatanaka: fig. 1B, 5) comprises two or more of silicon, carbon, or nitrogen (Hatanaka: 5 includes 7 with silica SiO2 and resin 8 with carbon; para. 0072, 0073). Regarding claim 13 , Yu in view of Kitayama and Hsu teaches the IC device of claim 1 including the first IC die and second IC die (Yu: fig. 9, 503, 505). Yu in view of Kitayama and Hsu fails to explicitly teach the first inorganic material is spaced apart from at least the corner of each of the first IC die and the second IC die by a void. However, Hatanaka teaches the first inorganic material (Hatanaka: fig. 1B, resin layer 4; para. 0020, similar to 801 of Yu) is spaced apart from at least the corner of each of the first IC die and the second IC die (Hatanaka: at least the corner of chip component 2; para. 0020, similar to 503, 505 of Yu) by a void (Hatanaka: voids G3 in inorganic insulating layer 5; para. 0020). Hatanaka, Hsu, Kitayama and Yu are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first inorganic material is spaced apart from at least the corner of each of the first IC die and the second IC die by a void from a barrier layer. Doing so would realize a layer to prevent invasion of water vapor and resin into the space of connects and suppress deterioration of the characteristics (Hatanaka: para. 0007, 0043). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT ZHIJUN XU whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3447 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Thursday 9am-5pm ET . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZHIJUN XU/ Examiner, Art Unit 2818 /BRIAN TURNER/ Examiner, Art Unit 2818