DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Apr. 23rd 2026 has been entered. Claims 1-18 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7 and 12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 7, the original disclosure only discuss that fill material preferably has a lower content of nitrogen and/or carbon than barrier layer in para. 69 of Specification, which is opposite to this limitation of "the barrier layer has a lower content of nitrogen or carbon than the fill". Therefore, this limitation is new matter. Claim 12 would also be rejected under 35 U.S.C. 112(a) because they are dependent on claim 7.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a first IC die comprising a device layer between a die substrate and first metallization layers" in line 2 and "a second IC die comprising a device layer between a die substrate and second metallization layers" in line 5. There is insufficient antecedent basis for this limitation in the claim. Claim 1 includes a device layer and a die substrate in both a first IC die and a second IC die and it is unclear whether same or separate elements is referring to. For examination purposes, examiner has interpreted "a first IC die comprising a device layer between a die substrate and first metallization layers" to be read as "a first IC die comprising a first device layer between a first die substrate and first metallization layers"; "a second IC die comprising a device layer between a die substrate and second metallization layers" to be read as "a second IC die comprising a second device layer between a second die substrate and first metallization layers". Claims 2-14 would also be rejected under 35 U.S.C. 112(b) because they are dependent on claim 1.
Claim 15 recites the limitation "a first IC die comprising a device layer between a die substrate and first metallization layers" in line 6 and "a second IC die comprising a device layer between a die substrate and second metallization layers" in line 10. There is insufficient antecedent basis for this limitation in the claim. Claim 15 includes a device layer and a die substrate in both a first IC die and a second IC die and it is unclear whether same or separate elements is referring to. For examination purposes, examiner has interpreted "a first IC die comprising a device layer between a die substrate and first metallization layers" to be read as "a first IC die comprising a first device layer between a first die substrate and first metallization layers"; "a second IC die comprising a device layer between a die substrate and second metallization layers" to be read as "a second IC die comprising a second device layer between a second die substrate and first metallization layers". Claims 16-18 would also be rejected under 35 U.S.C. 112(b) because they are dependent on claim 15.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20190244947) in view of Gomes et al. (US 20200258852), Kitayama et al. (US 20170213766) and Hsu et al. (US 20190139896).
Regarding claim 1, Yu teaches an integrated circuit (IC) device (Abstract), comprising:
a first IC die (fig. 9, first package 503; para. 0052) comprising a die substrate (first wafer 200; para. 0035) and first metallization layers (layer of first TIVs 401 in 503; para. 0050) within an insulator (dielectric material 501; para. 0050), wherein metallization features (401) within an uppermost level of the first metallization layers (uppermost level of 401 in 503) are directly bonded to a first region (left region) of a host substrate (first carrier substrate 601, adhesive layer 603 and polymer layer 605; para. 0053);
a second IC die (second package 505; para. 0052) comprising a die substrate (second substrate 201; para. 0035) and second metallization layers (layer of 401 in 505) within an insulator (501), wherein metallization features (401) within an uppermost level of the second metallization layers (uppermost level of 401 in 505) are directly bonded to a second region (right region) of the host substrate (601, 603, 605); and
wherein each of the first IC die (503) and second IC die (505) comprises an edge sidewall portion (edge sidewall of 503, 505), proximal to the host substrate (601, 603, 605), with a first slope (vertical slope) relative to a plane of the host substrate (601, 603, 605);
a fill (encapsulant 801; para. 0064) within a space (space between 503, 505) between the first and second IC dies.
Yu fails to explicitly teach a device layer between the die substrate and first metallization layers;
a device layer between the die substrate and second metallization layers;
the edge sidewall portion extending through the device layer.
However, Gomes teaches a device layer (Gomes: fig. 4, device layer 414; para. 0035) between the die substrate (Gomes: semiconductor substrate 412; para. 0035, similar to 200 of Yu) and first metallization layers (Gomes: metallization layers 416; para. 0035, similar to layer of 401 of Yu);
a device layer (Gomes: 414 in another die) between the die substrate (Gomes: 412) and second metallization layers (Gomes: 416 in another die);
the edge sidewall portion (Gomes: sidewall of IC die 410; para. 0035) extending through the device layer (Gomes: 414).
Gomes and Yu are considered to be analogous to the claimed invention because they are in the same field of integrated circuit devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a device layer as taught by Gomes.
Doing so would realize a device layer on the semiconductor substrate to include more devices to increase function (para. 0036).
Yu in view of Gomes fails to explicitly teach each of the first IC die and second IC die comprises:
a corner, spaced apart from the host substrate by the edge sidewall portion, having a radius of curvature exceeding 50 μm; or
a chamfer, spaced apart from the host substrate by the edge sidewall portion, and with a second slope relative to the plane of the host substrate that is at least 10° more than the first slope; and the fill extending over the corner or chamfer of each of the first and second IC dies.
However, Kitayama teaches each of the first IC die and second IC die (Kitayama: fig. 20, semiconductor chip CHP2; para. 0101, similar to 503, 505 of Yu) comprises:
a corner, spaced apart from the host substrate by the edge sidewall portion, having a radius of curvature exceeding 50 μm; or
a chamfer (Kitayama: bottom chamfer part), spaced apart from the host substrate (Kitayama: source electrode SE; para. 0089, similar to part couple to 601 of Yu) by the edge sidewall portion (Kitayama: vertical-shape portion VER2; para. 0101), and with a second slope (Kitayama: slope of angle θ of slant portion SLP2; para. 0101) relative to the plane (horizontal plane) of the host substrate that is 5° to 65° from vertical (Kitayama: from 25° to 85°; para. 0076), which overlaps at least 10° more than the first slope (Kitayama: vertical slope of VER2); and the fill (Kitayama: fig. 18, sealing member MR; para. 0090, similar to 801 of Yu) extending over the corner or chamfer (bottom chamfer part) of each of the first and second IC dies (Kitayama: CHP2).
Kitayama, Gomes and Yu are considered to be analogous to the claimed invention because they are in the same field of integrated circuit devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the sidewall with a slope range from 5° to 65° to at least 10° more than the vertical slope.
Doing so would realize a trapezoidal chip to improve yield of the semiconductor device (Kitayama: para. 0010). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
In addition, Yu in view of Gomes and Kitayama fails to explicitly teach the fill comprising at least a first inorganic material.
However, Hsu teaches the fill (Hsu: fig. 1C, encapsulant 20; para. 0025, similar to 801 of Yu) comprising at least a first inorganic material (Hsu: silicon oxide besides resin; para. 0025).
Hsu, Kitayama, Gomes and Yu are considered to be analogous to the claimed invention because they are in the same field of integrated circuit devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the fill comprising at least a first inorganic material as taught by Hsu.
Doing so would realize the fill with an alternative well known material with low cost (Hsu: para. 0025). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 2, Yu in view of Gomes, Kitayama and Hsu teaches the IC device of claim 1 including the host substrate (Yu: fig. 9, 601, 603, 605).
Yu in view of Gomes, Kitayama and Hsu as applied to claim 1 above fails to explicitly teach the corner has a radius of curvature exceeding 100 μm or the chamfer has a slope that is at least 10° from normal to the plane of the host substrate.
However, Kitayama teaches the corner has a radius of curvature exceeding 100 μm or the chamfer (Kitayama: fig. 20, bottom chamfer part) has a slope (Kitayama: slope of angle θ; para. 0076) that is 5° to 65° (Kitayama: from 25° to 85°; para. 0076), which overlaps the angle range at least 10° from normal to the plane (horizontal plane) of the host substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the slope range from 5° to 65° to at least 10° from normal to a plane of the host substrate.
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 3, Yu in view of Gomes, Kitayama and Hsu teaches the IC device of claim 1, wherein the first slope (Yu: fig. 9, vertical slope) is +/-5° (0° within +/-5°) from normal to the plane (horizontal plane) of the host substrate the host substrate (Yu: 601, 603, 605).
Yu in view of Gomes, Kitayama and Hsu as applied to claim 1 above fails to explicitly teach the second slope is at least 20° from normal to the plane of the host substrate.
However, Kitayama teaches the second slope (Kitayama: slope of angle θ) that is 5° to 65° (Kitayama: from 25° to 85°; para. 0076), which overlaps the angle range at least 20° from normal to the plane of the host substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the second slope range from 5° to 65° to at least 20° from normal to a plane of the host substrate.
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 4, Yu in view of Gomes, Kitayama and Hsu teaches The IC device of claim 1 including the chamfer (Kitayama: fig. 20, bottom chamfer part).
Yu in view of Gomes, Kitayama and Hsu as applied to claim 1 above fails to explicitly teach a slope at least 30° from normal to the plane of the host substrate.
However, Kitayama teaches a slope (Kitayama: fig. 20, slope of angle θ; para. 0076) that is 5° to 65° (Kitayama: from 25° to 85°; para. 0076), which overlaps the angle range at least 30° from normal to the plane (horizontal plane) of the host substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the slope range from 5° to 65° to at least 30° from normal to a plane of the host substrate.
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 14, Yu in view of Gomes, Kitayama and Hsu teaches the IC device of claim 1, wherein:
a surface of the first inorganic material layer (Yu: fig. 10, top surface of 801 and Hsu: silicon oxide) is substantially co-planar with a surface (top surface) of at least one of the first or second IC dies (Yu: 503 and 505); and
a third IC die, a passive interconnect structure (Yu: redistribution structure 1000; para. 0069), or a purely structural member is bonded to a top surface of the first inorganic material layer (Yu: top surface of 801 and Hsu: silicon oxide).
Regarding claim 15, Yu teaches a system (Abstract) comprising:
a host component (fig. 13 upside down, third package 1301; para. 0091); and
a composite integrated circuit (IC) device (device of first package 503, second package 505 and polymer layer 605; para. 0052, 0053) attached to the host component (1301), the composite IC device comprising:
a host substrate (605);
a first IC (503) comprising a die substrate (first wafer 200; para. 0035) and first metallization layers (layer of first TIVs 401 in 503; para. 0050) within an insulator (dielectric material 501; para. 0050), wherein metallization features (401) within an uppermost level of the first metallization layers (uppermost level of 401 in 503) are bonded to a first region (left region) of a host substrate (605);
a second IC die (505) comprising a die substrate (second substrate 201; para. 0035) and second metallization layers (layer of 401 in 505) within an insulator (501), wherein metallization features (401) within an uppermost level of the second metallization layers (uppermost level of 401 in 505) are bonded to a second region (right region) of the host substrate (605),
wherein each of the first IC die (503) and second IC die (505) comprise an edge sidewall portion (edge sidewall of 503, 505), proximal to the host substrate (601, 603, 605), with a first slope (vertical slope) +/-5° (0° within +/-5°) from normal to the plane (horizontal plane) of the host substrate the host substrate (601, 603, 605);
a fill (encapsulant 801; para. 0064) within a space (space between 503, 505) between the first and second IC dies; and
a third IC die, a passive interconnect structure (redistribution structure 1000; para. 0069), or a purely structural member bonded to a top surface of the fill (top surface of 801).
Yu fails to explicitly teach a device layer between the die substrate and first metallization layers;
a device layer between the die substrate and second metallization layers;
the edge sidewall portion extending through the device layer.
However, Gomes teaches a device layer (Gomes: fig. 4, device layer 414; para. 0035) between the die substrate (Gomes: semiconductor substrate 412; para. 0035, similar to 200 of Yu) and first metallization layers (Gomes: metallization layers 416; para. 0035, similar to layer of 401 of Yu);
a device layer (Gomes: 414 in another die) between the die substrate (Gomes: 412) and second metallization layers (Gomes: 416 in another die);
the edge sidewall portion (Gomes: sidewall of IC die 410; para. 0035) extending through the device layer (Gomes: 414).
Gomes and Yu are considered to be analogous to the claimed invention because they are in the same field of integrated circuit devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a device layer as taught by Gomes.
Doing so would realize a device layer on the semiconductor substrate to include more devices to increase function (para. 0036).
Yu in view of Gomes fails to explicitly teach each of the first IC die and second IC die comprises:
a chamfer, spaced apart from the host substrate by the edge sidewall portion, and with a slope that is at least 10° from normal to a plane of the host substrate.
However, Kitayama teaches each of the first IC die and second IC die (Kitayama: fig. 20, semiconductor chip CHP2; para. 0101, similar to 503, 505 of Yu) comprises:
a chamfer (Kitayama: bottom chamfer part), spaced apart from the host substrate (Kitayama: source electrode SE; para. 0089, similar to part couple to 601 of Yu) by the edge sidewall portion (Kitayama: vertical-shape portion VER2; para. 0101), and with a slope (Kitayama: slope of angle θ of slant portion SLP2; para. 0101) that is 5° to 65° (Kitayama: from 25° to 85°; para. 0076), which overlaps at least 10° from normal to a plane (horizontal plane) of the host substrate.
Kitayama, Gomes and Yu are considered to be analogous to the claimed invention because they are in the same field of integrated circuit devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the edge sidewall with a slope range from 5° to 65° to at least 10° from normal to a plane of the host substrate.
Doing so would realize a trapezoidal chip to improve yield of the semiconductor device (Kitayama: para. 0010). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
In addition, Yu in view of Gomes and Kitayama fails to explicitly teach the fill is an inorganic material.
However, Hsu teaches the fill (Hsu: fig. 1C, encapsulant 20; para. 0025, similar to 801 of Yu) is an inorganic material (Hsu: silicon oxide besides resin; para. 0025).
Hsu, Gomes, Kitayama and Yu are considered to be analogous to the claimed invention because they are in the same field of integrated circuit devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the fill is an inorganic material as taught by Hsu.
Doing so would realize the fill with alternative well known material with low cost (Hsu: para. 0025). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 16, Yu in view of Gomes, Kitayama and Hsu teaches the system of claim 15, further comprising:
a power supply (Yu: fig. 13, second TIVs 607; para. 0059) coupled to provide power (Yu: connected to external DC power supply; para. 0059) to the composite IC device (Yu: 605, 503, 505) through the host component (Yu: 1301).
Regarding claim 17, Yu in view of Gomes, Kitayama and Hsu teaches the system of claim 15, wherein the host substrate (Yu: fig. 13, 605) is coupled to the host component (Yu: 1301) through a plurality of first solder interconnects (Yu: fourth external connections 1303; para. 0091).
Regarding claim 18, Yu in view of Gomes, Kitayama and Hsu teaches the system of claim 15, wherein:
the first IC die (Yu: fig. 13, 503 has first semiconductor device 101; para. 0024) comprises a first of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry (Yu: memory device, logic device, power device; para. 0024); and
the second IC die (Yu: 505 has second semiconductor device 103; para. 0024) comprises a second of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry (Yu: memory device, logic device, power device; para. 0024).
Claims 5-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Gomes, Kitayama and Hsu as applied to claim 1 above, and further in view of Hatanaka et al. (US 20130250527).
Regarding claim 5, Yu in view of Gomes, Kitayama and Hsu teaches the IC device of claim 1 including the first IC die and second IC die (Yu: fig. 9, 503, 505).
Yu in view of Gomes, Kitayama and Hsu fails to explicitly teach a barrier layer between the fill and each of the first IC die and second IC die.
However, Hatanaka teaches a barrier layer (Hatanaka: fig. 1B, inorganic insulating layer 5; para. 0020) between the fill (Hatanaka: resin layer 4; para. 0020, similar to 801 of Yu) and each of the first IC die and second IC die (Hatanaka: chip component 2; para. 0020, similar to 503, 505 of Yu).
Hatanaka, Hsu, Kitayama, Gomes and Yu are considered to be analogous to the claimed invention because they are in the same field of integrated circuit devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a barrier layer.
Doing so would realize a layer to prevent invasion of water vapor and resin into the space of connects and suppress deterioration of the characteristics (Hatanaka: para. 0007, 0043).
Regarding claim 6, Yu in view of Gomes, Kitayama, Hsu and Hatanaka teaches the IC device of claim 5 including the barrier layer (Hatanaka: fig. 1B, 5).
Yu in view of Gomes, Kitayama, Hsu and Hatanaka as applied to claim 5 above fails to explicitly teach the barrier layer has a thickness less than 1 μm.
However, Hatanaka teaches the barrier layer (Hatanaka: fig. 1B, 5) has a thickness 1 μm or more (Hatanaka: 1 μm or more; para. 0076), which abuts the thickness range less than 1 μm.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness range from 1 μm or more to less than 1 μm.
Doing so would realize a thinner layer to reduce material usage and cost. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 7, Yu in view of Gomes, Kitayama, Hsu and Hatanaka teaches the IC device of claim 5, wherein the fill (Hsu: fig. 1C, 20) comprises silicon and oxygen (Hsu: silicon oxide with resin) and the barrier layer (Hatanaka: 5 with alumina) has a lower content of nitrogen or carbon (Hsu: lower Carbon because of resin in 20) than the fill (Hsu: 20).
Regarding claim 8, Yu in view of Gomes, Kitayama, Hsu and Hatanaka teaches the IC device of claim 5, wherein the barrier layer (Hatanaka: fig. 1B, 5) comprises a material (Hatanaka: 5 includes resin 8; para. 0074) has an organic composition (Hatanaka: organic resin 8; para. 0073).
Regarding claim 9, Yu in view of Gomes, Kitayama, Hsu and Hatanaka teaches the IC device of claim 8, wherein the barrier layer (Hatanaka: fig. 1B, 5) is polyimide (Hatanaka: polyimide resin; para. 0073).
Regarding claim 10, Yu in view of Gomes, Kitayama, Hsu and Hatanaka teaches the IC device of claim 5, wherein the barrier layer (Hatanaka: fig. 1B, 5) comprises a material (Hatanaka: 5 includes first inorganic particles 7; para. 0074) has an inorganic composition (Hatanaka: first inorganic particles 7; para. 0074).
Regarding claim 11, Yu in view of Gomes, Kitayama, Hsu and Hatanaka teaches the IC device of claim 10, wherein the barrier layer (Hatanaka: fig. 1B, 5) comprises two or more of silicon, carbon, or nitrogen (Hatanaka: 5 includes 7 with silica SiO2 and resin 8 with carbon; para. 0072, 0073).
Regarding claim 12, Yu in view of Gomes, Kitayama Hsu and Hatanaka teaches the IC device of claim 7, wherein the first inorganic material layer (Hsu: fig. 1C, 20) is predominantly silicon and oxygen (Hsu: silicon oxide; para. 0025).
Regarding claim 13, Yu in view of Gomes, Kitayama and Hsu teaches the IC device of claim 1 including the first IC die and second IC die (Yu: fig. 9, 503, 505).
Yu in view of Gomes, Kitayama and Hsu fails to explicitly teach the first inorganic material is spaced apart from at least a portion of each of the first IC die and the second IC die by a void.
However, Hatanaka teaches the first inorganic material (Hatanaka: fig. 1B, resin layer 4; para. 0020, similar to 801 of Yu) is spaced apart from at least a portion of each of the first IC die and the second IC die (Hatanaka: a portion of chip component 2; para. 0020, similar to 503, 505 of Yu) by a void (Hatanaka: voids G3 in inorganic insulating layer 5; para. 0020).
Hatanaka, Hsu, Kitayama, Gomes and Yu are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first inorganic material is spaced apart from at least the corner of each of the first IC die and the second IC die by a void from a barrier layer.
Doing so would realize a layer to prevent invasion of water vapor and resin into the space of connects and suppress deterioration of the characteristics (Hatanaka: para. 0007, 0043).
Response to Arguments
Applicant’s arguments with respect to claims 1-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
Prosecution Insights