DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 has been considered but are
moot in view of new grounds of rejection.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-7, 12-14 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Miyahara et al. (US 2009/0311839 A1), hereafter “Miyahara”, in view of Takeuchi et al. (US 5744826 A), hereafter “Takeuchi”, and further in view of Suzuki et al. (US 2009/0200559 A1), hereafter “Suzuki”.
As to claim 1, Miyahara teaches a semiconductor device, comprising:
a first electrode (⁋ [0056], 13, Fig. 8B);
a first semiconductor layer (⁋⁋ [0046], [0047], 1+2, Fig. 8B) connected to the first electrode, the first semiconductor layer including silicon carbide (⁋ [0046]), the first semiconductor layer being of a first conductivity type (⁋⁋ [0046], [0047], “n-type”);
a second semiconductor layer (⁋ [0048], 3) located on the first semiconductor layer, the second semiconductor layer including silicon carbide (⁋ [0048], “formed in a surface portion of the drift layer 2”), the second semiconductor layer being of a second conductivity type (⁋ [0049], “P type”);
a third semiconductor layer (⁋ [0048], 4) located on a portion of the second semiconductor layer, the third semiconductor layer including silicon carbide, the third semiconductor layer being of the first conductivity type (⁋ [0048], “n-type”);
a second electrode (⁋ [0055], 11) connected to the second and third semiconductor layers;
a third electrode (⁋ [0052], 9) located among the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer;
an insulating film (⁋⁋ [0052], 8, Fig. 7) located between the third electrode (9) and the second semiconductor layer (3) and between the third electrode (9) and the third semiconductor layer (4), in a first direction (x) perpendicular to a second direction (z) from the first electrode (13) to the second electrode (11); and
a fourth semiconductor layer (⁋ [0046], 7, Fig. 15) located between the insulating film and the first semiconductor layer and between the insulating film and the second semiconductor layer, the fourth semiconductor layer contacting the insulating film and including silicon carbide, an impurity concentration of the fourth semiconductor layer (⁋ [0051], 1x1016 cm-3) being less than an impurity concentration of the first semiconductor layer (⁋ [0046], 1x1019 cm-3) and an impurity concentration of the second semiconductor layer (⁋ [0049], 5x1016 cm-3 ), wherein
the third electrode extends in a third direction (y, Fig. 7) perpendicular to the first direction (x) and the second direction (z),
a length of the third electrode (9) in the third direction (y) is longer than a length of the third electrode in the first direction (x) (as shown in Fig. 7).
Miyahara fails to teach the fourth semiconductor layer covers an end portion of the third electrode in the third direction, and the semiconductor device has, in a view in the second direction, a cell region in which a plurality of transistor sub-regions, each of which extends in the first direction, are arranged in the third direction with an interval and a termination region that surrounds the cell region and in which no transistor sub-region is provided, the end portion of the third electrode in the third direction is located in the termination region.
Takeuchi teaches a similar semiconductor device with a trench gate (Col. 8, Lines 6-8, 10, Fig. 18), an insulating film (Col. 8, Lines 4-6, 9) and a semiconductor layer (Col. 8, Lines 4-6, 8). The semiconductor layer is shown to cover an end portion of the gate electrode (Fig. 18) in a similar direction as the third direction of Miyahara.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the configuration of the end portion as taught by Takeuchi into the semiconductor device of Miyahara to create a uniform electrical characteristic to complete the gate electrode and help provide control of the current from the source to the drain of the vertical transistor.
Miyahara in view of Takeuchi fails to teach the semiconductor device has, in a view in the second direction, a cell region in which a plurality of transistor sub-regions, each of which extends in the first direction, are arranged in the third direction with an interval and a termination region that surrounds the cell region and in which no transistor sub-region is provided, the end portion of the third electrode in the third direction is located in the termination region.
Suzuki teaches a similar semiconductor device with a view of a cell section and peripheral region (Fig. 28, ⁋ [0201]) in a similar second direction as the second direction of Miyahara, a cell region (see annotated Fig. 28 below) containing a plurality of transistor sub-regions (annotated Fig. 28 and Fig. 30B, ⁋ [0201] “In the cell section Sa, a plurality of MOSFETs are formed”) extending in a similar first direction (annotated Fig. 28) as the first direction of Miyahara, arranged in a similar third direction (annotated Fig. 28) as the third direction of Miyahara, in intervals, a termination region (region located directly outside of the cell region in annotated Fig. 28) that surrounds the cell region in which no transistor sub-region is provided, and the end portion of an electrode (Fig. 29, 309, ⁋ [0207]) is located in the termination region (see 306 in annotated Fig. 28, ⁋ [0207] “ a gate electrode 309 is formed so as to fill the trench 306”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the structure of the cell section and peripheral region as taught by Suzuki with the device of Miyahara and Takeuchi to allow for a device with a reduced on-resistance as taught by Suzuki (⁋ [0202]).
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As to claim 5, Miyahara teaches wherein
the second semiconductor layer includes:
a lower layer (⁋ [0093], 30, Fig. 8B) contacting the first semiconductor layer; and
an upper layer (3) contacting the third semiconductor layer (4), and
an impurity concentration of the upper layer (⁋ [0049]) is less than an impurity concentration of the lower layer (⁋ [0093]) (Within the given range of both layers, the impurity concentration of upper layer 3 can fall below the impurity concentration of lower layer 30).
As to claim 6, Miyahara teaches wherein
the first semiconductor layer (1+2) includes:
a first layer (1) contacting the first electrode (13);
a second layer (2) located on the first layer, an impurity concentration of the second layer (⁋ [0047]) being less than an impurity concentration of the first layer (⁋ [0046]); and
a third layer (⁋ [0093], 30) located on the second layer, the third layer contacting the second (3) and fourth (7) semiconductor layers, an impurity concentration of the third layer (⁋ [0093]) being greater than the impurity concentration of the second layer (⁋ [0047]).
As to claim 7, Miyahara teaches wherein the fourth semiconductor layer is of the first conductivity type (⁋ [0051]).
As to claim 12, Miyahara teaches wherein
the fourth semiconductor layer (7, Fig. 8B) is located also between the insulating film (8) and the third semiconductor layer (4), and
the third semiconductor layer (4) is separated from the insulating film (8).
As to claim 13, Miyahara teaches wherein
the first semiconductor layer includes:
a first layer (⁋⁋ [0046], [0047], 1, Fig. 8B) contacting the first electrode (10); and
a second layer (2) located on the first layer, an impurity concentration of the second layer (⁋ [0047]) being less than an impurity concentration of the first layer (⁋ [0046]), and
the impurity concentration of the second layer is not less than 1x1015 cm-3 and not more than 3x1016 cm-3 (⁋ [0047]; 3x1015 cm-3 to 7x1015 cm-3)
As to claim 14, Miyahara teaches wherein
the impurity concentration of the second semiconductor layer is not less than 5x1016 cm-3 and not more than 1x1019 cm-3 (⁋ [0049]).
As to claim 16, Miyahara does not teach the claimed range.
On the other hand, the Examiner notes Applicant has not specified a criticality to the range.
Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions or variable are critical. "The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. . . . In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range." In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
As to claim 17, Miyahara teaches wherein
a thickness of the fourth semiconductor layer is not less than 10 nm and not more than 100 nm (⁋ [0051], 0.1 µm is equivalent to 100nm).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
As to claim 18, Miyahara teaches wherein the insulating film (8) is provided between the third electrode (9) and the fourth semiconductor layer (7) in the third direction (y) (⁋ [0092, Fig. 8A and 8B show an x-z plane at two different locations in the y direction in Fig. 7, “FIG. 8A shows a cross section of the MOSFET taken along line VIIIA-VIIIA in FIG. 7”, “FIG. 8B shows a cross section of the MOSFET taken along line VIIIB-VIIIB in FIG. 7”).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Miyahara, Takeuchi, Suzuki, and further in view of Hatta et al. (WO 2020188686 A1), US 2022/0102503 A1 used as translation, hereafter “Hatta”.
As to claim 2, Miyahara in view of Takeuchi and Suzuki fail to disclose further comprising: a fifth semiconductor layer located between the first electrode and the third electrode, the fifth semiconductor layer contacting the first and fourth semiconductor layers, the fifth semiconductor layer being of the second conductivity type, an impurity concentration of the fifth semiconductor layer being greater than the impurity concentration of the second semiconductor layer.
Hatta teaches a fifth semiconductor layer (⁋ [0090], 13, Fig. 12) located between the first electrode (⁋ [0048], 11, Fig. 12) and the third electrode (9),
the fifth semiconductor layer contacting first (⁋ [0044], 1+2, Fig. 12) and fourth (⁋ [0046], 16, Fig. 12) semiconductor layers,
the fifth semiconductor layer being of the second conductivity type (⁋⁋ [0043], [0092], P type),
an impurity concentration of the fifth semiconductor layer being greater than the impurity concentration of the second semiconductor layer. Wherein at the highest of the range of the second semiconductor of Miyahara (⁋ [0094], 3, 2x1019 cm-3) is less than the highest of the range of Hatta’s fifth semiconductor (⁋ [0092], 1x1020 cm-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the fifth semiconductor layer as taught by Hatta into the silicon carbide device as taught by Miyaraha in view of Takeuchi and Suzuki in order yield the expected results of shortening the charger carriers path, suppressing the increase in potential and ultimately improving the reliability of the gate insulating film (⁋ [0096]).
As to claim 3, Hatta teaches wherein an impurity concentration of the fifth semiconductor layer is not less than 5x1018 cm-3 and not more than 2x1019 cm-3. (⁋ [0094])
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
As to claim 4, Miyahara teaches further comprising;
a plurality of connection layers (⁋ [0054], 10, Fig. 7) arranged along a direction in which the third electrode (9) extends,
the plurality of connection layers contacting the fifth (via the combination of Miyahara and Hatta’s fifth semiconductor layer) and second semiconductor layers (3),
the plurality of connection layers being of the second conductivity type (⁋ [0054], P type).
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Miyahara, Takeuchi, Suzuki, and further in view of Ohse et al. (US 2018/0175147 A1), hereafter “Ohse”.
As to claim 8, Miyahara in view of Takeuchi and Suzuki fail to disclose wherein the fourth semiconductor layer is of the second conductivity type.
Ohse teaches a similar silicon carbide semiconductor with a low-concentration thin film (⁋ [0043], 14, Fig. 1) of the second conductivity type (S2, p -type).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the p-type conductivity taught by Ohse into the silicon carbide semiconductor device taught by Miyahara in view of Takeuchi and Suzuki to ensure the channel surface impurity concentration may be reduced; additionally, the channel region resistance increases, enabling decreases in the threshold voltage to be prevented (⁋ [0044]).
As to claim 9, Miyahara in view of Takeuchi and Suzuki fail to disclose wherein
the fourth semiconductor layer includes:
a lower portion contacting the first semiconductor layer, the lower portion being of the first conductivity type; and
an upper portion contacting the second semiconductor layer, the upper portion being of the second conductivity type.
Ohse teaches a similar silicon carbide semiconductor with a low-concentration thin film (⁋ [0043], 14, Fig. 1) with a lower portion (S3) contacting the first semiconductor layer (⁋ [0039], 5) of the first conductivity type (n-type), and an upper portion (S2) contacting the second semiconductor layer (⁋ [0039], 6) of the second conductivity type (p-type).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the dual conductivity types taught by Ohse into the silicon carbide semiconductor device taught by Miyahara in view of Takeuchi and Suzuki to ensure the channel surface impurity concentration may be reduced; additionally, the channel region resistance increases, enabling decreases in the threshold voltage to be prevented (⁋ [0044]).
As to claim 10, Miyahara in view of Takeuchi and Suzuki fail to disclose wherein
the fourth semiconductor layer includes:
a lower portion contacting the first semiconductor layer, the lower portion being of the second conductivity type; and
an upper portion contacting the second semiconductor layer, the upper portion being of the first conductivity type.
Ohse teaches a similar silicon carbide semiconductor with a low-concentration thin film (⁋ [0043], 14, Fig. 1) with a lower portion (S2) contacting the first semiconductor layer (⁋ [0039], 5) of the second conductivity type (p-type), and an upper portion (S1) contacting the second semiconductor layer (⁋ [0039], 6) of the first conductivity type (n-type).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the p-type conductivity taught by Ohse into the silicon carbide semiconductor device taught by Miyahara in view of Takeuchi and Suzuki to ensure the channel surface impurity concentration may be reduced; additionally, the channel region resistance increases, enabling decreases in the threshold voltage to be prevented (⁋ [0044]).
As to claim 11, Miyahara in view of Takeuchi and Suzuki fail to disclose wherein
the third semiconductor layer contacts the insulating film and the fourth semiconductor layer, and the fourth semiconductor layer is separated from the second electrode.
Ohse teaches a similar silicon carbide semiconductor with a third semiconductor layer (⁋ [0039], 7, Fig. 1) contacting the insulating film (⁋ [0039], 9, Fig. 1) and the fourth semiconductor layer (⁋ [0043], 14, Fig. 1) and the fourth semiconductor layer separated from the second electrode (⁋ [0039], 12, Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the insulating film, electrode, and semiconductor layers structure as taught by Ohse into the silicon carbide semiconductor device of Miyahara in view of Takeuchi and Suzuki in order to acts as an interfacial barrier that helps control the flow of current.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Miyahara, Takeuchi, Suzuki, and further in view of Kaji et al. (US 2020/0203482 A1), hereafter “Kaji”.
As to claim 15, Miyahara in view of Takeuchi and Suzuki fail to teach wherein an impurity concentration of the third semiconductor layer is not less than 5x1016 cm-3 and not more than 5x1017 cm-3.
Kaji teaches a similar silicon carbide semiconductor with a third semiconductor layer or source region (⁋ [0043], 8a, Fig. 1) that contains an impurity concentration within the given range.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the impurity concentration as taught by Kaji within the silicon carbide semiconductor device as taught by Miyahara in view of Takeuchi and Suzuki to yield a saturation current value at a time of load short circuit to be reduced (⁋ [0028]).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893