Prosecution Insights
Prosecution Insights
Tech Center 2800 • Art Units: 2800 2829 2893
This examiner grants 92% of resolved cases
Carnell Hunter III has a high allowance rate of 91.7 percent across 72 resolved cases. Working in Art Unit 2800, this examiner grants the vast majority of applications he reviews. The 91.7 percent allowance rate indicates a very high probability of success for applicants in Tech Center 2800.
Interviews appear to be beneficial, providing an interview lift of 15.3 percent. This 15.3 percent lift can help secure an allowance in cases that might otherwise face delays or rejections. The median days to allowance for these cases is 1258. This 1258-day timeline provides a specific expectation for the duration of the process from filing to grant. With an allowance rate of 91.7 percent, the primary challenge for practitioners may be managing the 1258-day timeline rather than the likelihood of the grant itself. The 72 resolved cases suggest a consistent pattern of high allowance.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18456261 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME | Final Rejection | SAMSUNG ELECTRONICS CO., LTD. |
| 17887007 | DISPLAY DEVICE INCLUDING A LIGHT CONTROL LAYER AND MANUFACTURING METHOD OF THE SAME | Non-Final OA | Samsung Display Co., Ltd. |
| 18458848 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME AND DISPLAY APPARATUS COMPRISING THE SAME | Non-Final OA | LG Display Co., Ltd. |
| 18068886 | TRANSPARENT TOUCH DISPLAY DEVICE | Non-Final OA | LG Display Co., Ltd. |
| 18458087 | SEMICONDUCTOR DEVICE | Non-Final OA | Toshiba Electronic Devices & Storage Corporation |
| 18066159 | STRUCTURE WITH CONDUCTIVE FEATURE FOR DIRECT BONDING AND METHOD OF FORMING SAME | Final Rejection | ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. |
| 18395906 | DISPLAY DEVICE | Non-Final OA | Japan Display Inc. |
| 18760532 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE | Non-Final OA | IDEMITSU KOSAN CO., LTD. |
| 18788409 | SEMICONDUCTOR DEVICES WITH THRESHOLD VOLTAGE MODULATION LAYER | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18781323 | SEMICONDUCTOR STRUCTURE HAVING SELF-ALIGNED CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SEMICONDUCTOR STRUCTURE | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18408487 | SEMICONDUCTOR DEVICE, MEMORY STRUCTURE AND METHOD OF FORMING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18516431 | CLEANING PROCESS FOR SOURCE/DRAIN EPITAXIAL STRUCTURES | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18733611 | Diode and Method of Manufacturing Same | Non-Final OA | Microchip Technology Incorporated |
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