Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-8, 15-20 in the reply filed on 11/3/25 is acknowledged. Claims 9-14 are withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention.
Information Disclosure Statement
The information disclosure statements filed 3/24/25; 2/5/24; 6/2/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 9/8/22 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 15-18 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by CHOU et al. (CN 205039151U).
Referring to figures 1-22, CHOU et al. a composite chiplet comprising:
a first integrated circuit (IC) component at a first level (3);
a second IC component at a second level (18);
a first layer of a first insulator material (10) at the first level, wherein the first layer extends around the first IC component (3, see figure 1);
a first conductive via (6) which extends through the first layer and is electrically coupled to circuitry (18) at the second level; and
a first annular structure (5, see figure 8) which extends through the first layer and which surrounds the first conductive via (6) in the first layer, wherein a cavity region is in the first annular structure; or
the first annular structure comprises a second material, wherein a first modulus of elasticity of the first insulator material is greater than a second modulus of elasticity of the second material (5, see figure 8).
Regarding to claim 2, the first conductive via is one of multiple conductive vias (6) which extend through the first layer; the first annular structure is one of multiple annular structures which each extend through the first layer (10) and which each surround a respective one of the multiple conductive vias in the first layer; and for each one of the multiple annular structures: a respective cavity region is in the annular structure; the annular structure comprises the second material (see figure 1).
Regarding to claim 3, wherein each of the multiple annular structures (5) surrounds only a respective one of the multiple conductive vias (6, see figures 1, 8).
Regarding to claim 4, the first annular structure comprises the second material, and wherein the second material comprises a polymer (5, see figures 1, 8).
Regarding to claim 5, the first annular structure comprises the second material, and wherein the second material comprises a low-k porous dielectric (5, see figures 1, 8).
Regarding to claim 6, the first annular structure comprises the second material, and wherein the second of elasticity is in a range of 0.1 GigaPascals (GPa) to 10 GPa (5, see figures 1, 8).
Regarding to claim 15, a system comprising:
a microprocessor; and a memory coupled to the microprocessor, wherein at least one of the memory or the microprocessor (see figures 1, 22) comprises circuitry on a composite chiplet comprising:
a first integrated circuit (IC) component at a first level (3);
a second IC component at a second level (18);
a first layer of a first insulator material (10) at the first level, wherein the first layer extends around the first IC component (3, see figure 1);
a first conductive via (6) which extends through the first layer and is electrically coupled to circuitry at the second level; and
a first annular structure (5, see figure 8) which extends through the first layer and which surrounds the first conductive via in the first layer, wherein a cavity region is in the first annular structure; or
the first annular structure comprises a second material, wherein a first modulus of elasticity of the first insulator material is greater than a second modulus of elasticity of the second material (5, see figure 8).
Regarding to claim 16, the first conductive via is one of multiple conductive vias (6) which extend through the first layer; the first annular structure is one of multiple annular structures which each extend through the first layer (10) and which each surround a respective one of the multiple conductive vias in the first layer; and for each one of the multiple annular structures: a respective cavity region is in the annular structure; the annular structure comprises the second material (see figure 1).
Regarding to claim 17, the first annular structure comprises the second material, and wherein the second material comprises a polymer (5, see figures 1, 8).
Regarding to claim 18, the first annular structure comprises the second material, and wherein the second material comprises a low-k porous dielectric (5, see figures 1, 8).
Allowable Subject Matter
Claims 7-8, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the prior art teaches or suggests a structural support layer over the second level, wherein multiple dummy vias extend through the structural support layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893