Prosecution Insights
Last updated: October 01, 2026
Application No. 17/891,727

INTEGRATED CONFORMAL THERMAL HEAT SPREADER FOR MULTICHIP COMPOSITE DEVICES

Non-Final OA §103
Filed
Aug 19, 2022
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
652 granted / 722 resolved
+22.3% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
82 currently pending
Career history
804
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
68.2%
+28.2% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
6.2%
-33.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 722 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-17 in the reply filed on 01/13/26 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang(USPGPUB DOCUMENT: 2022/0344233, hereinafter Chang) in view of Wan (USPGPUB DOCUMENT: 2020/0312741, hereinafter Wan). Re claim 1 Chang discloses in Fig 2 a multichip composite device, comprising: a first region of a bottom surface of an integrated circuit (IC) die hybrid bonded(since 202/206/208 are bonded by blend or mixture of material(s), this may be interpreted as hybrid bonded)[0026] to a first region of a top surface of a base die(204), wherein a bottom surface of the base die(204), opposite the top surface of the base die(204), is to interconnect to a substrate(interposer/device by way of 216)[0028]; a conformal layer(220) on a top surface of the IC die(202/innermost left208/right208), opposite the bottom surface of the IC die(202/innermost left208/right208), and on a sidewall surface of the IC die(202/innermost left208/right208), the sidewall surface extending between the top surface and the bottom surface of the IC die(202/innermost left208/right208); an inorganic dielectric material[0027] on a portion the conformal layer(220), over a second region of the top surface of the base die(204), and laterally adjacent the sidewall surface of the IC die(202/innermost left208/right208), wherein the conformal layer(220) comprises a greater thermal conductivity[0030] than the inorganic dielectric material[0027]; Chang does not discloses a structural member coupled to the conformal layer(220). Wan discloses a structural member(117)[0038] coupled to the conformal layer(116/119). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Wan to the teachings of Chang in order to have advanced thermal management architectures at the package level [0002, Wan]. Re claim 2 Chang and Wan disclose the multichip composite device of claim 1, wherein the conformal layer(220) is over the second region of the top surface of the base die(204) and in contact with a metal[0030] pad coupled to the base die(204). Re claim 3 Chang and Wan disclose the multichip composite device of claim 1, wherein the conformal layer(220) is on a second inorganic dielectric material[0027] and one or more through dielectric vias(105 of Wan) (TDVs) embedded in the second inorganic dielectric material[0027], wherein the second inorganic dielectric material[0027] and the one or more TDVs are laterally adjacent the base die(204). Re claim 4 Chang and Wan disclose the multichip composite device of claim 1, wherein the conformal layer(220) comprises a metal[0030]. Re claim 5 Chang and Wan disclose the multichip composite device of claim 4, wherein the metal[0030] comprises one or more of copper, aluminum, silver, or gold. Re claim 6 Chang and Wan disclose the multichip composite device of claim 1, wherein the conformal layer(220) comprises one or more of diamond, graphene, graphite, or a compound of boron and nitrogen. Re claim 7 Chang and Wan disclose the multichip composite device of claim 1, wherein the structural member(117)[0038 of Wan] is directly on the conformal layer(220). Re claim 8 Chang and Wan disclose the multichip composite device of claim 1, wherein the conformal layer(220) comprises a metal[0030] and a second metal[0030] layer is in contact with the conformal layer(220) and in contact with the structural member(117)[0038 of Wan]. Re claim 9 Chang and Wan disclose the multichip composite device of claim 8, wherein the second metal[0030] layer is between the structural member(117)[0038 of Wan] and the inorganic dielectric material[0027]. Re claim 10 Chang and Wan disclose the multichip composite device of claim 8, wherein a second dielectric material laterally adjacent to the second metal[0030] layer is in contact with the inorganic dielectric material[0027] and in contact with the inorganic dielectric material[0027]. Re claim 11 Chang discloses in Fig 2 a multichip composite device, comprising: a base die(204) comprising a bottom surface to interconnect to a substrate(interposer/device by way of 216)[0028]; a stack of one or more integrated circuit (IC) dies over a first region of a top surface of the base die(204), opposite the bottom surface of the base die(204); a conformal layer(220) on a top surface of an uppermost one of the one or more IC dies(202/innermost left208/right208) and on a sidewall surface of the uppermost one of the IC dies(202/innermost left208/right208); an inorganic dielectric material[0027] on a portion of the conformal layer(220), the inorganic dielectric material[0027] over a second region of the top surface of the base die(204), and laterally adjacent the sidewall surface of the uppermost IC die(202/innermost left208/right208), wherein the conformal layer(220) comprises a greater thermal conductivity[0030] than the inorganic dielectric material[0027]; Chang does not discloses a structural member over the conformal layer(220). Wan discloses a structural member(117)[0038 of Wan] over the conformal layer(116/119). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Wan to the teachings of Chang in order to have advanced thermal management architectures at the package level [0002, Wan]. Re claim 12 Chang and Wan disclose the multichip composite device of claim 11, wherein the one or more IC dies(202/innermost left208/right208) comprise the uppermost IC die(202/innermost left208/right208) hybrid bonded(since 202/206/208 are bonded by blend or mixture of material(s), this may be interpreted as hybrid bonded)[0026] to a second IC die(202/innermost left208/right208) one of the one or more IC dies(202/innermost left208/right208), and wherein the conformal layer(220) extends between the inorganic dielectric material[0027] and a second inorganic dielectric material[0027] laterally adjacent to the second IC die(202/innermost left208/right208). Re claim 13 Chang and Wan disclose the multichip composite device of claim 12, wherein the second IC die(202/innermost left208/right208) is hybrid bonded(since 202/206/208 are bonded by blend or mixture of material(s), this may be interpreted as hybrid bonded)[0026] to the first region of the top surface of the base die(204), and a second conformal layer(220) is on a sidewall of the second IC die(202/innermost left208/right208) and over the second region of the top surface of the base die(204). Re claim 14 Chang and Wan disclose the multichip composite device of claim 13, wherein the second conformal layer(220) is on a third inorganic dielectric material[0027] and one or more through dielectric vias(105 of Wan) (TDVs) embedded in the third inorganic dielectric material[0027], wherein the third inorganic dielectric material[0027] and the one or more TDVs are laterally adjacent the base die(204). Re claim 15 Chang and Wan disclose the multichip composite device of claim 11, wherein the conformal layer(220) comprises one or more of diamond, graphene, graphite, or a compound of boron and nitrogen. 16Re claim Chang and Wan disclose the multichip composite device of claim 11, wherein the conformal layer(220) comprises a metal[0030]. Re claim 17 Chang and Wan disclose the multichip composite device of claim 16, wherein the structural member(117)[0038 of Wan] is directly on the metal[0030] of the conformal layer(220) or a second metal[0030] layer is in contact with the metal[0030] of the conformal layer(220) and in contact with the structural member(117)[0038 of Wan]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Aug 19, 2022
Application Filed
Mar 20, 2023
Response after Non-Final Action
Apr 08, 2026
Non-Final Rejection mailed — §103
Jul 08, 2026
Response after Non-Final Action
Jul 08, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.0%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 722 resolved cases by this examiner. Grant probability derived from career allowance rate.

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