Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on November 25, 2025, regarding the application filed August 19, 2022. Applicant’s amendment to the claims, filed on November 25, 2025, has been entered into the record. This Office Action is made with all the suggested amendments being fully considered.
Election/Restrictions
Applicant’s election without traverse of Invention I, corresponding to claims 1-11, in the reply filed on November 25, 2025 is acknowledged. Claims 12-22 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized.
Claims 1-22 are pending, with claims 12-22 currently withdrawn from consideration.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 2, 2023; February 5, 2024; and November 25, 2025 have been placed in the application file and are being considered by the examiner.
Drawings
The drawings filed with the application on August 19, 2022 are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3-5, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al., US 2021/0096311 A1 (hereinafter Yu) in view of Wan et al., US 2020/0312741 A1 (hereinafter Wan) and further in view of Chen et al., US 2019/0103390 A1 (hereinafter Chen).
Regarding claim 1, Yu discloses: A multichip composite device, comprising: an integrated circuit die (Yu, FIG. 18, left processing die 242, [0014-0016; 0043) hybrid bonded to a first region of a first surface (Yu, FIG. 18 shows processing die 242 [the integrated circuit die] bonded to upper surface of interconnect structure 120 in the region shown as the left side of individual sites 201 [the first region], [0031; 0043]; “the electronic die is hybrid bonded to the interconnect structure,” [0056]), wherein a second surface (Yu, FIG. 18, lower surface of interconnect structure 120), is to interconnect to a substrate (Yu, FIG. 18 shows lower surface of interconnect structure 120 [analogous to the second surface of the base die] interconnected to substrate 260 by means of conductive connectors 134 and vias 112); an inorganic dielectric material (Yu, dielectric material 126, silicon oxide, i.e., silicon dioxide, [0033]) laterally adjacent the integrated circuit die (Yu, see FIG. 18) and over a second region of the first surface (Yu, FIG. 18 shows dielectric material 126 [the inorganic dielectric material] over region 266 [the second region] of interconnect structure 120); and a dummy die (Yu, FIG. 18, dummy die 252, [0047-0049]) coupled to a third region of the first surface (Yu, FIG. 18 shows dummy die 252 [the dummy die] coupled to the upper surface of interconnect structure 120 in the right side of individual sites 201 [the third region] laterally adjacent to processing die 242 [the integrated circuit die]),
Although Yu does not explicitly disclose “a base die”, a person having ordinary skill in the art would recognize that the structure shown in Yu, FIG. 7 and associated text, is analogous to a base die because this structure, comprising interconnect structure 120, photonic routing structure 110, substrate 102C, photodetectors 106A, and modulators 106B, includes active circuitry formed by growing epitaxial material on silicon in order to provide electronic functionality when in operation (see Yu, [0019-0021]). Additionally, Chen, in the same field of endeavor, teaches an integrated circuit die (Chen, FIG. 3, second semiconductor device 200, [0077]) hybrid bonded (Chen, [0078-0080]) to a first region of a first surface of a base die (Chen, FIG. 3 shows second semiconductor device 200 [the integrated circuit die] hybrid bonded to a first region of upper surface of first semiconductor device 100 [the base die]; “the combination of the first semiconductor device 100 [the base die] and the second semiconductor device 200 [the integrated circuit die] can be utilized to form a chip stack,” [0077]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu with the teachings of Chen, arriving at Applicant’s claimed structural arrangement with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Chen, to integrate chips at the device level resulting in shorter routing paths, thereby improving performance and reliability (Chen, [0253]).
Although Yu teaches that the inorganic dielectric material comprises silicon dioxide (Applicant’s specification indicates that silicon dioxide is known to have “thermal conductivity of about 1.3 W/m-K,” [0040]), Yu is silent regarding: wherein the dummy die comprises a greater thermal conductivity than the inorganic dielectric material.
However, Wan, in the same field of endeavor teaches: wherein the dummy die comprises a greater thermal conductivity than the inorganic dielectric material (Wan, FIG. 4H shows TEC (thermoelectric) module 108 [analogous to dummy die 252 of Yu] adjacent to IC device 107 [analogous to processing die 242 of Yu]; (note that Applicant’s definition of the term “dummy die” includes a thermoelectric cooling die, [0031])). Wan teaches that the TEC module provides improved heat transfer, capable of transferring heat away from materials with thermal conductivity up to approximately 400 W/mK (Wan, see [0036-0037], i.e., thermal conductivity greater than the inorganic dielectric material.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu with the teachings of Wan, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Wan, to reduce thermal stress caused by bursts of computational processing, thereby improving device performance and reliability.
Regarding claim 2, Yu in view of Wan and further in view of Chen teaches: The multichip composite device of claim 1, wherein the dummy die (Yu, FIG. 18, dummy die 252, [0047-0049]; Wan, FIG. 4H, TEC module 108, [0046-0047]) comprises one of silicon (Wan, [0047]), diamond, a compound of silicon and carbon, a composite of silicon and diamond, or a composite of silicon and copper.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Yu in view of Wan include one or more of Applicant’s claimed alternative elements, for example: silicon.
Regarding claim 3, Yu in view of Wan teaches: The multichip composite device of claim 1, further comprising: a structural member over the dummy die (Wan, FIG. 4H, shows thermal solution 117 [the structural member] over TEC module 108 [the dummy die], [0038; 0054]); and a bonding layer between the structural member and the dummy die (Wan, FIG. 4H, thermal interface material 116, [0039]),
Yu in view of Wan is silent regarding: wherein the bonding layer has a thickness of not more than 1 micron and the bonding layer comprises silicon and one of oxygen, nitrogen, or carbon.
However, Chen, in the same field of endeavor teaches a method for hybrid bonding: wherein the bonding layer (Chen, FIG. 1A, first wafer bond layer 121, “used for hybrid bonding or fusion bonding (also referred to as oxide-to-oxide bonding),” [0062]) has a thickness of not more than 1 micron (Chen, FIG. 1A, first wafer bond layer 121 [the bonding layer] has thickness between 1 nm and 1,000 nm, i.e., not more than 1 micron, [0062]) and the bonding layer comprises silicon and one of oxygen, nitrogen, or carbon (Chen, “the first wafer bond layer 121 [the bonding layer] is formed of a silicon-containing dielectric material such as silicon oxide, silicon nitride, or the like,” i.e., the bonding layer comprises silicon and one of oxygen or nitrogen, [0062]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu in view of Wan with the teachings of Chen, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Chen, to provide a suitable bonding layer for hybrid bonding, thereby improving manufacturing efficiency while also reducing device thickness and improving device performance and reliability.
Regarding claim 4, Yu in view of Wan and further in view of Chen teaches: The multichip composite device of claim 3, wherein the bonding layer further comprises metal vias (Chen, FIG. 8 shows through fill vias 501 [metal vias] extending through the bonding layer at the interfaces of first semiconductor device 100 and third semiconductor device 300 and fourth semiconductor device 700, [0095]), and wherein the structural member is hybrid bonded to the dummy die (Chen, “the fourth semiconductor device 700 [analogous to the thermal solution 117 taught by Wan, i.e., the structural member] is bonded directly to both the through fill vias 501 [metal vias] as well as the first fill material 401 [of third semiconductor device 300, analogous to the dummy die] using, e.g., a hybrid bond [the bonding layer],” [0095]).
Regarding claim 5, Yu in view of Wan and further in view of Chen teaches: The multichip composite device of claim 3, wherein top surfaces of the integrated circuit die and the dummy die are substantially co-planar (Wan, FIG. 4H shows top surface of IC device 107 [the integrated circuit die] and top surface of TEC module 108 [the dummy die] are substantially co-planar) and the bonding layer extends over the top surfaces of the integrated circuit die and the dummy die (Wan, FIG. 4H shows thermal interface material 116 [the bonding layer] extending over the top surfaces of IC device 107 [the integrated circuit die] and TEC module 108 [the dummy die]).
Regarding claim 9, Yu in view of Wan and further in view of Chen teaches: The multichip composite device of claim 1, wherein the dummy die (Yu, FIG. 18, dummy die 252, [0047-0049]; Wan, FIG. 4H, TEC module 108, [0046-0047]) comprises a thermoelectric cooling device adjacent the base die (Wan, FIG. 4H shows TEC module 108 [the thermoelectric cooling device] adjacent to IC device 107 [the base die]; (note that Applicant’s definition of the term “dummy die” includes a thermoelectric cooling die, [0031])).
Regarding claim 10, Yu in view of Wan and further in view of Chen teaches: The multichip composite device of claim 9, wherein the base die comprises a photonic element (Yu, FIG. 18, photonic components 106, “the photonic components 106 facilitate the input/output (I/O) of optical signals to and from the optical network 104,” [0013]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Wan and further in view of Chen and further in view of Kim et al., US 2013/0139524 A1 (hereinafter Kim).
Regarding claim 6, Yu in view of Wan and further in view of Chen teaches: The multichip composite device of claim 1, further comprising: a second integrated circuit die (Yu, FIG. 18, left memory die 250, [0014-0015; 0047) hybrid bonded to the integrated circuit die (Yu, FIG. 18, [0031]) and opposite the integrated circuit die from the base die (Yu, FIG. 18 shows left memory die 250 [the second integrated circuit die] hybrid bonded to upper surface of left processing die 242 [the integrated circuit die] which is bonded to upper surface of interconnect structure 120 [analogous to the base die], i.e., opposite the integrated circuit die from the base die),
Yu in view of Wan and further in view of Chen is silent regarding: wherein a thickness of the dummy die is not less than a sum of a thickness of the integrated circuit die and a thickness of the second integrated circuit die.
However, Kim, in the same field of endeavor, teaches: wherein a thickness of the dummy die (Kim, FIG. 7C, thickness of TEC 10 [the dummy die] shown as distance between upper surface of board 90 and lower surface of heat sink 70, [0164]) is not less than a sum of a thickness of the integrated circuit die and a thickness of the second integrated circuit die (Kim, FIG. 7C shows TEC 10 [the dummy die] having a thickness not less than the sum of the thickness of the adjacent stacked integrated circuit dies comprising POP 80, i.e., not less than a sum of a thickness of the integrated circuit die and a thickness of the second integrated circuit die, [0164]). Kim teaches that this structural arrangement minimizes heat generated by the TEC to the stacked integrated circuit dies comprising the POP, (Kim, [0164]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu in view of Wan with the teachings of Kim, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kim, to better control heat transfer within the device package, thereby improving device performance and reliability.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Wan and further in view of Chen and further in view of Valavala et al., US 2020/0105639 A1 (hereinafter Valavala).
Regarding claim 7, Yu in view of Wan and further in view of Chen teaches nearly every element of claim 7 but is silent regarding: wherein the dummy die comprises a substrate layer and a heat transfer layer on the substrate layer, wherein the heat transfer layer is adjacent the base die, the heat transfer layer having a thickness less than the substrate layer and a thermal conductivity greater than the substrate layer.
However, Valavala, in the same field of endeavor, teaches a cooling solution including a dummy die adjacent to stacked integrated circuit dice, wherein the dummy die (Valavala, FIG. 1D, the dummy die is shown as the structure including all components shown in FIG. 1D, and is analogous to Wan, FIG. 4H, TEC module 108, [0046-0047]) comprises a substrate layer (Valavala, FIG. 1D, dummy die 118, [0037-0038]) and a heat transfer layer on the substrate layer (Valavala, FIG. 1D, cold side electrode 124, [0037-0038]), wherein the heat transfer layer is adjacent the base die (the structure resulting from the combination of Yu in view of Wan and further in view of Valavala would be similar to that shown in Wan, FIG. 4H, with the dummy die adjacent to the base die), the heat transfer layer having a thickness less than the substrate layer (Valavala, see FIG. 1D, thickness of cold side electrode 124 [the heat transfer layer] is less than 100 microns, thickness of dummy die 118 [the substrate layer] is 100-200 microns, [0049-0050]) and a thermal conductivity greater than the substrate layer (Valavala, FIG. 1D, cold side electrode 124 [the heat transfer layer], copper, [0037]; thermal conductivity of copper is approximately 400 W/mK (Wan, [0036]); dummy die 118 [the substrate layer], silicon, [0037]; thermal conductivity of silicon is approximately 120 W/mK (Applicant’s specification, [0040])).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu in view of Wan with the teachings of Valavala, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Valavala, to provide a package structure with means for pumping heat from a device to improve cooling, thereby improving performance and reliability.
Regarding claim 8, Yu in view of Wan and further in view of Chen and further in view of Valavala teaches: The multichip composite device of claim 7, wherein the substrate layer comprises silicon (Valavala, FIG. 1D, “dummy die 118 [the substrate layer] may comprise silicon,” [0037]) and the heat transfer layer (Valavala, FIG. 1D, cold side electrode 124) comprises one of diamond, copper (Valavala, FIG. 1D, cold side electrode 124 [the heat transfer layer], “copper or copper alloys,” [0037]), a compound of boron and nitrogen, a composite of boron and arsenic, a compound of silicon and carbon, or a compound of aluminum and nitrogen.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Yu in view of Wan and further in view of Valavala include one or more of Applicant’s claimed alternative elements, for example: copper.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Wan and further in view of Chen, as applied to claim 9 above, and further in view of Estes et al., U.S. Pat. No. 6,570,362 B1 (hereinafter Estes).
Regarding claim 11, Yu in view of Wan and further in view of Chen teaches nearly every element of claim 11 but is silent regarding: wherein the dummy die comprises one of a phase change material or one or more microchannels to allow flow of a cooling fluid therein adjacent the thermoelectric cooling device.
However, Estes, in the same field of endeavor, teaches a thermoelectric module with phase change material (Estes, FIG. 1, thermoelectric module 106 [the thermoelectric cooling device] shown with phase change material (PCM) module 108 [the phase change material]). Estes teaches that the phase change material module enhances the temperature differential at the thermoelectric module, resulting in improved cooling.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu in view of Wan with the teachings of Estes, arriving at Applicant’s claimed dummy die comprising a thermoelectric cooling device and phase change material adjacent the base die with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Estes, to improve heat dissipation of the device, thereby improving device performance and reliability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899