DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 04, 2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 5, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2012/0261720 A1 to Puglisi et al. (“Puglisi”) in view of U.S. Patent Application Publication No. 2013/0146889 A1 to Makiyama (“Makiyama”). As to claim 1, although Puglisi discloses a nitride-based high electron mobility transistor comprising: a substrate (41); a first semiconductor layer (42”) and a second semiconductor layer (43) sequentially formed on the substrate (41); a source electrode (44S) and a drain electrode (44D) formed on the second semiconductor layer (43); a first insulating film (45’) formed on the second semiconductor layer (43) and at least partially on the source electrode (44S) and the drain electrode (44D) and having an opening (49) between the source electrode (44S) and the drain electrode (44D); a dielectric (46A, 46B, 47A, 47B) formed on the first insulating film (45’) to surround the opening (49) of the first insulating film (45’), the dielectric (46A, 46B, 47A, 47B) having an inner sidewall and an outer sidewall; a second insulating film (48) formed on the inner sidewall and the outer sidewall of the dielectric (46A, 46B, 47A, 47B); and a gate electrode (44G) formed on the dielectric (46A, 46B, 47A, 47B) to fill the opening (49) of the first insulating film (45’) and inside the inner sidewall of the dielectric (46A, 46B, 47A, 47B), wherein a width of the inner sidewall at a bottom end of the dielectric (46A, 46B, 47A, 47B) is smaller than a width of the inner sidewall at a top end of the dielectric (46A, 46B, 47A, 47B) (See Fig. 4, ¶ 0025, ¶ 0173-¶ 0193) (Notes: the second insulating film is formed above and covers/overlaps the inner and outer sidewalls of the dielectric to be on the inner and outer sidewalls of the dielectric), Puglisi does not further disclose the opening exposing an upper surface of the second semiconductor layer; and the gate electrode formed to fill the opening so that the gate electrode is in contact with the upper surface of the second semiconductor layer. However, Makiyama does disclose the opening (33, 34) exposing an upper surface of the second semiconductor layer (12c); and the gate electrode (13) formed to fill the opening (33, 34) so that the gate electrode (13) is in contact with the upper surface of the second semiconductor layer (12c) (See Fig. 2, Fig. 7, Fig. 9, Fig. 10, Fig. 11, ¶ 0032-¶ 0035, ¶ 0071, ¶ 0088-¶ 0096) (Notes: the upper surface is relative to a lower surface). In view of the teachings of Puglisi and Makiyama, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Puglisi to have the opening exposing an upper surface of the second semiconductor layer; and the gate electrode formed to fill the opening so that the gate electrode is in contact with the upper surface of the second semiconductor layer because a parasitic capacitance, an electric field intensity, and an expansion of a depletion layer in the vicinity of the gate electrode are lowered and reduced such that the current collapse is suppressed while obtaining high gain. Further, the transistor can also be operated in an enhancement mode (See Puglisi ¶ 0025 and Makiyama ¶ 0035, ¶ 0089-¶ 0096). As to claim 2, Puglisi further discloses wherein the dielectric (46A, 46B, 47A, 47B) comprises: a first dielectric (46) formed on the first insulating film (45’) to surround the opening (49) of the first insulating film (45’); and a second dielectric (47) formed on the first dielectric (46), wherein a width of an inner sidewall of the first dielectric (46) is smaller than a width of an inner sidewall of the second dielectric (47) (See Fig. 4) As to claim 3, Puglisi further discloses wherein the second insulating film (48) is formed on an inner sidewall of the opening (49) of the first insulating film (45’), and inner and outer sidewalls of the first dielectric (46) and the second dielectric (47) (See Fig. 4, ¶ 0189). As to claim 5, Puglisi discloses further comprising: an insertion layer (42’) disposed between the first semiconductor layer (42”) and the second semiconductor layer (43) (See Fig. 4, ¶ 0181). As to claim 8, Puglisi further discloses wherein a width of the inner sidewall of the first dielectric (46) is equal to or greater than a width of the inner sidewall of the opening (49) (See Fig. 4). As to claim 9, Puglisi further discloses wherein a height (perpendicular right height FIG. 4C) of the second dielectric (47) is equal to or smaller than a height of the first dielectric (46) (See Fig. 4).
Claim(s) 1-3, 5, 7-9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0049526 A1 to Chu et al. (“Chu”) in view of U.S. Patent Application Publication No. 2013/0146889 A1 to Makiyama (“Makiyama”). As to claim 1, although Chu discloses a nitride-based high electron mobility transistor comprising: a substrate (10); a first semiconductor layer (11) and a second semiconductor layer (12) sequentially formed on the substrate (10); a source electrode (14) and a drain electrode (15) formed on the second semiconductor layer (12); a first insulating film (21) formed on the second semiconductor layer (12) and at least partially on the source electrode (14) and the drain electrode (15) and having an opening (at 49) between the source electrode (14) and the drain electrode (15); a dielectric (23, 31) formed on the first insulating film (21) to surround the opening (at 49) of the first insulating film (21), the dielectric (23, 31) having an inner sidewall and an outer sidewall; a second insulating film (33) formed on the inner sidewall and the outer sidewall of the dielectric (23, 31); and a gate electrode (49) formed on the dielectric (23, 31) to fill the opening (at 49) of the first insulating film (21) and inside the inner sidewall of the dielectric (23, 31), wherein a width of the inner sidewall at a bottom end of the dielectric (23, 31) is smaller than a width of the inner sidewall at a top end of the dielectric (23, 31) (See Fig. 13, ¶ 0003, ¶ 0024, ¶ 0025, ¶ 0029, ¶ 0031, ¶ 0032, ¶ 0037, ¶ 0038, ¶ 0039, ¶ 0049, ¶ 0057, ¶ 0058) (Notes: the second insulating film is formed above to be supported by the inner and outer sidewalls of the dielectric as “on” is used as a function word to indicate a source of attachment or support by Merriam-Webster.com), Chu does not further disclose the opening exposing an upper surface of the second semiconductor layer; and the gate electrode formed to fill the opening so that the gate electrode is in contact with the upper surface of the second semiconductor layer. However, Makiyama does disclose the opening (33, 34) exposing an upper surface of the second semiconductor layer (12c); and the gate electrode (13) formed to fill the opening (33, 34) so that the gate electrode (13) is in contact with the upper surface of the second semiconductor layer (12c) (See Fig. 2, Fig. 7, Fig. 9, Fig. 10, Fig. 11, ¶ 0032-¶ 0035, ¶ 0071, ¶ 0088-¶ 0096) (Notes: the upper surface is relative to a lower surface). In view of the teachings of Chu and Makiyama, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Chu to have the opening exposing an upper surface of the second semiconductor layer; and the gate electrode formed to fill the opening so that the gate electrode is in contact with the upper surface of the second semiconductor layer because an HEMT is formed rather than a MIS type. Further, an electric field intensity and an expansion of a depletion layer in the vicinity of the gate electrode are lowered and reduced such that the current collapse is suppressed while obtaining higher gain and breakdown voltage. Lastly,, the transistor can also be operated in an enhancement mode (See Chu ¶ 0003, ¶ 0024, ¶ 0025 and Makiyama ¶ 0035, ¶ 0089-¶ 0096). As to claim 2, Chu further discloses wherein the dielectric (23, 31) comprises: a first dielectric (23) formed on the first insulating film (21) to surround the opening (at 49) of the first insulating film (21); and a second dielectric (31) formed on the first dielectric (23), wherein a width of an inner sidewall of the first dielectric (23) is smaller than a width of an inner sidewall of the second dielectric (31) (See Fig. 13). As to claim 3, Chu further discloses wherein the second insulating film (33) is formed on an inner sidewall of the opening (at 49) of the first insulating film (21), and inner and outer sidewalls of the first dielectric (23) and the second dielectric (31) (See Fig. 13). As to claim 5, Chu discloses further comprising: an insertion layer (19) disposed between the first semiconductor layer (11) and the second semiconductor layer (12) (See Fig. 13). As to claim 7, Chu further discloses wherein the opening (at 49) is formed to be closer to the source electrode (14) than the drain electrode (15) (See Fig. 13). As to claim 8, Chu further discloses wherein a width of the inner sidewall of the first dielectric (23) is equal to or greater than a width of the inner sidewall of the opening (at 49) (See Fig. 13). As to claim 9, Chu further discloses wherein a height of the second dielectric (31) is equal to or smaller than a height of the first dielectric (23) (See Fig. 13). As to claim 12, Chu further discloses wherein the gate electrode (49) comprises at least two steps on its outer surface respectively supported by the second dielectric (31) and the first dielectric (23) (See Fig. 13).
Claim(s) 6 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0049526 A1 to Chu et al. (“Chu”) and U.S. Patent Application Publication No. 2013/0146889 A1 to Makiyama (“Makiyama”) as applied to claims 1 and 2 above, and further in view of U.S. Patent Application Publication No. 2022/0208992 A1 to Chou et al. (“Chou”). The teachings of Chu and Makiyama have been discussed above. As to claim 6, Chu in view of Chou further discloses wherein the first insulating film (21/110) is made into a multilayer film containing silicon nitride (Si3N4), silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), or a combination thereof (See Chu ¶ 0037 and Chou ¶ 0027) because the multilayer film provides a certain thickness to serve as the etch stop layer, where the dielectric materials are known to provide a certain etch selectivity. As to claim 10, Chu in view of Chou further discloses wherein the first dielectric (23) and the second dielectric (31) are made of hydrogen silsesquioxane (HSQ) (See Chu ¶ 0038, ¶ 0049 and Chou ¶ 0027) where hydrogen silsesquioxane (HSQ), silicon oxide, silicon nitride, etc. are known dielectric materials to provide a certain etch selectivity relative to another material. As to claim 11, Chu in view of Chou further discloses wherein the second insulating film (33/110) is made into a multilayer film containing silicon nitride (Si3N4), silicon dioxide (SiO2), silicon oxynitride (SiOxNx), or a combination thereof (See Chu ¶ 0049 and Chou ¶ 0027) because the multilayer film of known dielectric materials serves as a passivation to protect the transistor.
Allowable Subject Matter
Claim 4 is allowed.
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot
in view of the new ground(s) of rejection.
Conclusion
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/DAVID CHEN/Primary Examiner, Art Unit 2815