DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The election of claims 1-18 dated 12/15/25 is noted. The species restriction of dated 10/16/25 has been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 4-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US pub 20210020601).
With respect to claim 1, Chen et al. teach an integrated circuit (IC) device, comprising (see figs. 1-4D, particularly figs. 1E and 1H, and associated text):
a first IC die (left 200) bonded to a first region of a host substrate 102, wherein a first edge the first IC die has a first sidewall (vertical) slope relative to a plane of the host substrate;
a second IC die (righ 200) bonded to a second region of the host substrate, wherein the second IC die comprises a second edge (vertical) adjacent to the first edge of the first IC die; and
a fill (F-1, F-2) within a space between the first and second IC dies, wherein the fill comprises two or more layers (F-1,F-2) of inorganic material (see para 39 and 42), and wherein an interface between a first of the layers and a second of the layers has a second sidewall slope that is smaller than the first sidewall slope.
With respect to claim 4, Chen et al. teach the first layer comprises predominantly silicon and oxygen. See para 39 and 42.
With respect to claim 5, Chen et al. teach first and second layers have substantially the same composition (silicon oxide). See para 39 and 42.
With respect to claim 6, Chen et al. teach the first layer has a first composition (silicon oxide) and the second layer has a second composition (silicon nitride), different than the first composition. See para 39 and 42.
With respect to claim 7, Chen et al. teach the second layer (silicon nitride) has higher nitrogen content than the first layer (silicon oxide). See para 39 and 42.
With respect to claim 8, Chen et al. teach the second layer comprises silicon and at least one of oxygen and nitrogen (silicon oxide or silicon nitride). See para 39 and 42.
With respect to claim 9, Chen et al. teach the fill comprises an interface layer BL between the first layer and the host substrate, and wherein the interface layer has a different composition (silicon nitride) than the first layer (silicon oxide). See para 39 and 42.
With respect to claim 10, Chen et al. teach the interface layer has a greater nitrogen content and greater thickness conformality than the first layer. See fig. 1E and associated text.
With respect to claim 11, Chen et al. teach one or both of the first IC die and the second IC die is a die within a multi-die stack or within a multi-chip composite structure comprising a base die (the parts right under the dies) and one or more top dies gap-filled with an inorganic dielectric material. See fig. 1E and associated text.
With respect to claim 12, Chen et al. teach the first edge is a perimeter edge of the first IC die; the second edge is a perimeter edge of the second IC die; a first portion of the first layer surrounds the first and second edges; and the second layer is within a recess that surrounds the first portion of the first layer. See fig. 1E and associated text.
With respect to claim 13, Chen et al. teach a surface of the fill is substantially co-planar with a surface of at least one of the first or second IC dies; and a structural member is bonded to the surface of the fill and bonded to the surface of at least one of the first or second IC die. See fig. 1H and associated text.
With respect to claim 14, Chen et al. teach a surface of the fill is substantially co-planar with a surface of at least one of the first or second IC dies; and a structural member 302 is bonded to the surface of the fill and bonded to the surface of at least one of the first or second IC die. See fig. 1H and associated text.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US pub 20210020601).
With respect to claim 2, Chen et al. teach the there is a difference between the first and second sidewall slopes but fail to teach the range for the difference.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value or range for the difference of the slopes between first and second sidewalls through routine experimentation and optimization to obtain optimal or desired device performance because there is no evidence indicating that the claimed range is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP 2144.05.
With respect to claim 3, Chen et al. teach the first sidewall slope is at least 90 degrees but fail to teach the second sidewall slope is less than 80 degrees.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value or range for the second sidewall slope through routine experimentation and optimization to obtain optimal or desired device performance because there is no evidence indicating that the claimed range is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP 2144.05.
With respect to claim 14, Chen et al. teach the structural member is an interconnect structure but fail to teach the structural member is a monocrystalline silicon based IC.
However, the bonding a silicon based IC to another IC for the purpose of increasing device density is well-known to one of ordinary skill in the art of making semiconductor devices.
Claim(s) 15 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US pub 20210020601).
With respect to claim 15, Chen et al. teach a system, comprising (see figs. 1-4D, particularly figs. 1E and 1H, and associated text):
a host component 102; a composite integrated circuit (IC) die package (left 200 and right 200) attached to the host component, the composite IC device comprising:
a host substrate (substrate of dies);
a first IC die (left 200) bonded to a first region of the host substrate, wherein a first edge the first IC die has a first sidewall slope relative to a plane of the host substrate;
a second IC die (right 200) bonded to a second region of the host substrate, wherein the second IC die comprises a second edge adjacent to the first edge of the first IC die;
a fill (F-1 and F-2) within a space between the first and second IC dies, wherein the fill comprises two or more layers (F-1 and F-2) of inorganic material, and wherein an interface between a first of the layers and a second of the layers has a second sidewall slope that is less than the first sidewall slope; and
a structural member 302 is bonded to the surface of the fill and bonded to the surface of at least one of the first or second IC die.
With respect to claim 18, Chen et al. teach the first IC die is a first of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry, clock generator circuitry, memory circuitry, or input/output buffer circuitry; and the second IC die is a second of a microprocessor core circuitry, wireless radio circuitry, floating point gate array (FPGA) circuitry, power management circuitry, active repeater circuitry,clock generator circuitry, memory circuitry, or input/output buffer circuitry. See para 20.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US pub 20210020601).
With respect to claim 16, Chen et al. teach a power supply is provided to the ICs but fail the power supply is provided through the host component.
However, the provision of power supply to the IC through a host component is well-known to one of ordinary skill in the art of making semiconductor devices.
With respect to claim 17, Chen et al. teach the host substrate (substrate of the ICE) is coupled to the host component 102 through a plurality of interconnects but fail to teach the interconnect is solders
However, the interconnection between a host structure and a component substrate is well-known to one of ordinary skill in the art of making semiconductor devices.
Examiner’s Cited References
The cited references generally show the similar or related structure having a filling material having a multiple layer structure having an interface between layers having a slope between ICs having shapes as presently claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897