Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-10, 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Leung et al. (US Pub # 2002/0015344).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Leung et al. teach an apparatus comprising: a memory controller including, a memory channel interface (see Fig. 2-3, paragraph 0025-0030, Unit 104 is controller, data lines are interfacing channel), configured to be coupled to a mating memory channel interface on a memory device having a plurality of banks comprising multiple sets of banks, including, a set of read data (RdDQ) lines; a set of write data (WrDQ) lines; one or more command signal lines (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0042, memory array 115 divided into 16 banks, RD[0]..RD[31] is read data lines, WD[0]..WD[31] is write data lines); and logic to implement full duplex concurrent read and write operations using commands sent over the one or more command signal lines and under which read data read from a first bank within a set of banks are received over the set of RdDQ lines while write data destined to be written to a second bank within a second set of banks are concurrently sent over the set of WrDQ lines (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0042, 105 is logic unit, CE, ADS etc are command signal lines).
Even though Leung et al. teach concurrent read-write operations and memory array 115 divided into 16 banks but silent exclusively about read data read from a first bank and write data destined to be written to a second bank. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Leung et al. where data line pairs form bi-directional bus connecting between read-write control circuit 105 and column of memory banks (see specially paragraph 0030) i.e. data is written to unmasked portion (first bank) of memory and read from masked portion (second bank) of memory array (see specially claim 28) in order to have independent bank control for write read operations and to improve write speed of memory device (see paragraph 0011).
Regarding claim 2, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Leung et al. further teach, comprising multiple memory channel interfaces, each configured to interface with a respective memory device having a plurality of banks and including: a respective set of RdDQ lines; a respective set of WrDQ lines; and the memory controller including logic to implement full duplex concurrent read and write operations under which read data stored in a first respective bank within a first respective set banks are received over a respective set of RdDQ lines while write data destined to be written to a second respective bank within a second respective set of banks are concurrently sent over a respective set of WrDQ lines (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0042).
Regarding claim 5, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Leung et al. further teach, wherein in the plurality of banks are partitioned into a plurality of bank groups, further configured to support concurrent read and write data transfers to respective banks within the same bank group of the memory device (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0038).
Regarding claim 6, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Leung et al. further teach, further comprising a System on a Chip (SoC) in which the memory controller is implemented and including one or more compute elements coupled to the memory controller (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034).
Regarding claim 7, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Leung et al. further teach, wherein the memory controller is implemented in a die and the memory channel interface comprises a die-to-die interface (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037).
Regarding claim 8, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Leung et al. further teach, wherein the set of RdDQ lines and the set of WrDQ lines comprise through silicon vias (TSVs) (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034).
Regarding independent claim 9, Leung et al. teach an apparatus comprising: one or more memory devices having a plurality of banks comprising multiple sets of banks; a memory controller, coupled to the one or more memory devices via plurality of memory channel interfaces (see Fig. 2-3, paragraph 0025-0030, Unit 104 is controller, data lines are interfacing channel), each including respective sets of Read data (RdDQ) lines and Write data (WrDQ) lines (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0042, RD[0]..RD[31] is read data lines, WD[0]..WD[31] is write data lines), one or more command signal lines and at least one clock signal line; and logic to implement full duplex concurrent read and write operations using commands sent over the one or more command signal lines and under which read data stored in a first bank within a first set of banks in a memory device are received over the set of RdDQ lines for a memory channel interface while write data destined to be written to a second bank within a second set of banks in the memory device are concurrently sent over the set of WrDQ lines for the memory channel interface (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0042, 105 is logic unit, CE, ADS etc are command signal lines, memory array 115 divided into 16 banks).
Even though Leung et al. teach concurrent read-write operations and memory array 115 divided into 16 banks but silent exclusively about read data stored in a first bank and write data destined to be written to a second bank. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Leung et al. where data line pairs form bi-directional bus connecting between read-write control circuit 105 and column of memory banks (see specially paragraph 0030) i.e. data is written to unmasked portion (first bank) of memory and read from masked portion (second bank) of memory array (see specially claim 28) in order to have independent bank control for write read operations and to improve write speed of memory device (see paragraph 0011).
Regarding claim 10, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Leung et al. further teach, further comprising a System on a Chip (SoC) in which the memory controller is implemented and including one or more compute elements coupled to the memory controller (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037).
Regarding claim 12, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Leung et al. further teach, wherein the SoC comprises an SoC die including the memory controller, the one or more memory devices comprises one or more memory dies, and wherein the SoC die is coupled to the one or more memory dies via one or more die-to- die interconnects (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0040).
Regarding claim 13, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Leung et al. further teach, wherein, for each of at least one of the memory channel interfaces, a memory device coupled to the memory channel interface is configured to support concurrent read transfers from and write transfers to the same bank on the memory device (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0041).
Regarding claim 14, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Leung et al. further teach, wherein, for each of at least one of the memory channel interfaces, a memory device coupled to the memory channel interface is configured to support concurrent read transfers from and write transfers to respective banks within the same set of banks (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034).
Regarding claim 15, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Leung et al. further teach, wherein a memory device comprises, memory channel input-output (IO) interface circuitry including a set of RdDQ lines and a set of WrDQ lines, one or more command signal lines, and at least one clock signal line; and a macro block of IO drivers coupled to the memory channel IO interface circuitry via a macro interface and coupled to at least a portion of the plurality of banks on the memory device, wherein the macro interface is configured to support full duplex operations under which read and write data are concurrently transferred over the macro interface (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0042).
Regarding independent claim 16, Leung et al. teach a memory device, comprising: a plurality of banks, each bank comprising an array of memory cells, the plurality of banks comprising multiple sets of banks; one or more memory channel interfaces, each memory channel interface configured to be coupled to a mating memory channel interface on a memory controller (see Fig. 2-3, paragraph 0025-0030, Unit 104 is controller, data lines are interfacing channel) and including respective sets of Read data (RdDQ) lines and Write data (WrDQ) lines (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0042, RD[0]..RD[31] is read data lines, WD[0]..WD[31] is write data lines), one or more command signal lines and at least one clock signal line; and one or more sets of input-output (IO) drivers coupled between the one or more memory channel interfaces and respective groups or sets of banks among the plurality of banks, wherein a memory channel interface is configured to support concurrent read and write data transfers by sending data read from in a first bank within a first set of banks over the set of RdDQ lines while concurrently receiving data over the set of WrDQ lines destined to be written to a second bank within a second set of banks (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0042, 101 is IO drivers, CE, ADS etc are command signal lines, memory array 115 divided into 16 banks).
Even though Leung et al. teach concurrent read-write operations and memory array 115 divided into 16 banks but silent exclusively about read from in a first bank and written to a second bank. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Leung et al. where data line pairs form bi-directional bus connecting between read-write control circuit 105 and column of memory banks (see specially paragraph 0030) i.e. data is written to unmasked portion (first bank) of memory and read from masked portion (second bank) of memory array (see specially claim 28) in order to have independent bank control for write read operations and to improve write speed of memory device (see paragraph 0011).
Regarding claim 17, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Leung et al. further teach, wherein the one or more sets of IO drivers comprise a macro block of IO drivers, and wherein the macro block of IO drivers is coupled to one or more memory channel interfaces via one or more respective macro interfaces supporting full duplex operations under which read data and write data are concurrently sent over the macro interface (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0040).
Regarding claim 18, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Leung et al. further teach, wherein a portion of IO drivers in a macro block are connected to a bank and support full duplex operations under which independent read and write operations may be performed concurrently for the bank (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037).
Regarding claim 19, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Leung et al. further teach, wherein respective portions of IO drivers in a macro block are connected to respective banks via respective pairs of uni-directional links, and the memory device supports concurrent full duplex operations using the pairs of uni-directional links under which read and write operations are performed concurrently for the respective banks (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034, 0037-0040).
Regarding claim 20, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Leung et al. further teach, comprising a plurality of memory channel interfaces coupled to respective macro blocks of IO drivers via respective macro interfaces (see Fig. 2-3, paragraph 0004-0008, 0025-0031, 0033-0034).
Claims 3-4, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Leung et al. (US Pub # 2002/0015344) in view of Smith (US Pub # 2019/0205244).
Regarding claim 3, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Leung et al. are silent about wherein the memory channel interface is coupled to one or more memory dies in a stacked three-dimensional (3D) structure.
Smith teaches wherein the memory channel interface is coupled to one or more memory dies in a stacked three-dimensional (3D) structure (see Fig.2, 17-2, 17-3 18-2 and paragraph 0325-0327, 0560-0563, DRAM chip 0…4 are stacked in a 3D structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Smith to the teaching of Leung et al. where DRAM memory device of Leung et al. would be stacked in a 3D structure taught by Smith in order to have independent die control for system performance improvement (see Smith, paragraph 0070).
Further reason to combine the teachings of Leung et al. and Smith is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards DRAM memory array.
Regarding claim 4, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Leung et al. are silent about wherein the memory controller is implemented in a compute die in a stacked 3D structure including the compute die and one or more memory dies stacked above the compute die, wherein the compute die comprises a central processing unit (CPU) or other processing unit (XPU) .
Smith teaches wherein the memory controller is implemented in a compute die in a stacked 3D structure including the compute die and one or more memory dies stacked above the compute die, wherein the compute die comprises a central processing unit (CPU) or other processing unit (XPU) (see Fig.2, 17-2, 17-3 18-2 and paragraph 0325-0327, 0560-0563, DRAM chip 0…4 are stacked in a 3D structure, Chip 0 is logic die / compute die).
Regarding claim 11, Leung et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Leung et al. are silent about wherein the apparatus comprises a stacked three- dimensional (3D) structure comprising an SoC die on which one or more memory dies are stacked, wherein are least one memory channel interface is coupled to at least one memory die using a set of through silicon vias (TSVs).
Smith teaches wherein the apparatus comprises a stacked three- dimensional (3D) structure comprising an SoC die on which one or more memory dies are stacked, wherein are least one memory channel interface is coupled to at least one memory die using a set of through silicon vias (TSVs). (see Fig.2, 17-2, 17-3 18-2 and paragraph 0156, 0325-0327, 0560-0563, DRAM chip 0…4 are stacked in a 3D structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Smith to the teaching of Leung et al. where DRAM memory device of Leung et al. would be stacked in a 3D structure taught by Smith in order to have independent die control for system performance improvement (see Smith, paragraph 0070).
Further reason to combine the teachings of Leung et al. and Smith is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards DRAM memory array.
Response to Arguments
Applicant's arguments filed 01/222/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 16 of remarks) that Applicant respectfully asserts the Examiner has failed to establish a prima facie of obviousness as set forth in M.P.E.P. §§2142-2143.03 for at least the reason the prior art reference (Leung) does not teach or suggest all the claim 1 limitations. Examiner respectfully disagrees with this statement.
First, as per claim 1 limitation “a set of banks” and “a second set of banks” would be interpreted broadly where “set of banks” can be an array of memory i.e. “a second set of banks” can be a memory array and “a set of banks” can be same memory array.
Second, the limitation “read from a first bank within a set of banks” also would be interpreted broadly where the claim limitation did not indicate first bank only i.e. if data is read from the whole array (divided by banks), this would include first bank also. Similarly, the limitation “write data destined to be written to a second bank within a second set of banks” did not specify second only i.e. . if data is written to the whole array (divided by banks), this would include second bank also. Or, first bank can be certain portion / area of whole memory array and second bank can be different portion / area of whole memory array.
In Fig. 3, paragraph 0025, Leung et al. teach “memory array 115 is divided into 16 banks of 128 rows and 2048 columns”.
In claim 29, Leung further teach “the writing and the concurrently reading operations are performed”.
In claim 28, Leung further teach “writing an unmasked portion of a plurality of data bits into a memory array and a read buffer of the semi-conductor memory device during a write memory array operation; and concurrently reading a masked portion of the plurality of data bits from the memory array into the read buffer during the same write memory array operation” where writing unmased portion of memory array and reading masked portion from the memory array clearly indicate two different area of memory array and unmasked portion of array would be called first bank and masked portion of array would be called second bank. SO, Leung et al. clearly teach the limitation.
Applicant further argues that “Leung do not involve a memory controller (which would be external to the memory device and coupled to I/O interface 101 via the memory channel lines (aka memory bus). There is no memory controller nor memory controller interface disclosed in Leung”. Examiner respectfully disagrees with this statement.
First, the limitation “memory controller” is broad where any unit / circuitry / device control the memory would be called controller.
Second, as per claim 1 limitation, “memory controller” includes memory channel interface coupled to memory device only. The limitation clearly did not mention external or internal. However, controller can be external to memory array also.
In Fig. 2, Paragraph 0026, Leung et al. teach “The memory array operation is controlled by memory control sequencer 104 using signals: row access strobe RAS#, sense-amp enable SE#, column switch enable CAS#, and precharge PRC#”. Here, control unit 104 controls memory operation, external to memory array and coupled to memory array through different channel. So, 104 is controller.
All other independent claims are rejected for the same reason explained above along with dependent claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824