Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/03/2025 has been entered.
Response to Arguments
In response to the applicant’s arguments filed on 10/03/2025, the amendments made to the independent claims, claims 1 and 7, overcome the previous prior art rejection. However, upon further search and consideration, a new rejection has been formulated below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728) in view of Gu et al (US 9368450).
Lee et al teaches
[claim 1] A semiconductor device, comprising: a semiconductor substrate having an upper surface and a lower surface opposite the upper surface (figures 2-6, paragraph 0018, element 201 is the semiconductor substrate with an upper surface [surface that touches element 202b], and a lower surface [surface that touches element 202a]),
wherein the semiconductor substrate includes a cavity and a peripheral region surrounding the cavity (figures 2-6, paragraph 0018, element 204 defines the cavity with a peripheral region surrounding the cavity),
wherein: in the peripheral region, the semiconductor substrate extends continuously from the upper surface to the lower surface and the cavity is formed into the upper surface and extends from the upper partially through the semiconductor substrate to an intermediate surface between the upper surface and the lower surface (figures 2-6, paragraph 0018, where the cavity [element 204] is formed in the substrate where outside the cavity there is a continuous formation of the substrate from the upper surface [surface of element 201 that touches 202b] to the lower surface [surface that touches element 202a], and the cavity forms an intermediate surface which is defined as the bottom of the cavity which resides between the upper and lower surface),
the intermediate surface being parallel to and spaced apart from the lower surface (paragraph 0018, figures 2-6, where the intermediate surface [bottom surface of cavity 204] is parallel to the lower surface [surface of 201 that touches 202a] and resides between the lower and upper surface [surface of 201 that touches elements 202a and 202b, respectively]);
a plurality of first through-silicon vias (TSVs) extending between the lower surface and the intermediate surface (figures 2-6, paragraphs 0016 and 0018, where element 206 is a ‘metal pillar’ defined in paragraph 0016 as a TSV, and connects the lower surface and the intermediate surface).
However, Lee et al does not specifically disclose
[claim 1] and at least one second through-silicon via (TSV) extending between the upper surface and the lower surface.
However, Gu et al does teach
[claim 1] and at least one second through-silicon via (TSV) extending between the upper surface and the lower surface (figure 2, col 7 lines 9-31, where element 208 is the substrate and equates to the substrate of Lee et al, the base reference. The cavity described by element 210 is the save as the cavity in Lee et al, the base reference. The TSV’s, element 262, extends from a bottom surface to a top surface of the substrate, element 208, outside the cavity).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al with the teachings of Gu et al in order to connect other circuits between the substrate, thus being able to integrate the IC that rests in the cavity of the substrate to be interconnected to other IC’s in a spatially efficient manner by stacking and connecting through TSV’s.
Regarding claim 2, Lee et al further discloses
[claim 2] The semiconductor device, wherein: the cavity is configured to receive an additional semiconductor device electrically coupled with the plurality of first TSVs at the intermediate surface (figure 2, paragraph 0018, where element 206 [TSVs] are attached to a semiconductor device [element 208]).
Claim(s) 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728) and Gu et al (US 9368450) in further view of Yong et al (US 20200357744 A1).
Lee et al teaches all of the limitations of the parent claim, claims 1, but does not specifically disclose
[claim 3] the semiconductor device of claim 1, further comprising: a passivation layer extending across the upper surface, the intermediate surface, and side-walls of the cavity.
[claim 4] the semiconductor device of claim 1, wherein the plurality of first TSVs are exposed at the intermediate surface.
[claim 5] the semiconductor device of claim 4, further comprising: a plurality of contact pads, wherein each contact pad of the plurality of contact pads is formed directly upon a respective TSV of the plurality of first TSVs.
[claim 6] the semiconductor device of claim 1, wherein: each of the plurality of first TSVs is spaced apart from the semiconductor substrate by a layer of non-conductive material.
However, Yong et al does teach
[claim 3] the semiconductor device of claim 1, further comprising: a passivation layer extending across the upper surface, the intermediate surface, and side-walls of the cavity (figure 3F, paragraph 0047, where elements 343 and 325 cover the first surface, the third surface and sidewalls of the cavity and are made of any suitable material like an epoxy, which is an oxide, and passivation layers are a type of oxide layer to insulate material, which said epoxy does).
[claim 4] the semiconductor device of claim 1, wherein the plurality of first TSVs are exposed at the intermediate surface (figure 1A, paragraphs 0030-0032, where element 117 can be seen to go through the substrate and be exposed before connecting to the semiconductor device, element 120, at the third surface 114).
[claim 5] the semiconductor device of claim 4, further comprising: a plurality of contact pads, wherein each contact pad of the plurality of contact pads is formed directly upon a respective TSV of the plurality of first TSVs (paragraph 0032, figure 1A, element 122 are contact pads that connect the plurality of TSV’s [element 117]).
[claim 6] the semiconductor device of claim 1, wherein: each of the plurality of first TSVs is spaced apart from the semiconductor substrate by a layer of non-conductive material (figure 3F, paragraph 0047, element 325 [an epoxy] is non-conductive and separates the TSV’s).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al as modified to incorporate the teachings of Yong et al in order to adequately connect the IC to the TSV’s in the cavity to form the strongest electrical connection for maximal efficiency of the device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728) in view of Gu et al (US 9368450) and in further view of Yu et al (US 20180012863).
Lee et al teaches
[claim 7] a top semiconductor device of the stack including: a semiconductor substrate having a first surface and a second surface spaced apart from and parallel to the first surface (figures 2-6, paragraph 0018, element 201 is the semiconductor substrate with a first surface [surface that touches element 202b], and a second surface [surface that touches element 202a], and the two surfaced are spaced apart and parallel to each other),
wherein the semiconductor substrate includes a cavity and a peripheral region surrounding the cavity (figures 2-6, paragraph 0018, element 204 defines the cavity with a peripheral region surrounding the cavity),
wherein: the cavity is formed into the first surface and extends from the first surface partially through the semiconductor substrate to a third surface between the first surface and the second surface (figures 2-6, paragraph 0018, where the cavity [element 204] is formed in the substrate where outside the cavity there is a continuous formation of the substrate from the first surface [surface of element 201 that touches 202b] to the second surface [surface that touches element 202a], and the cavity forms a third surface which is defined as the bottom of the cavity which resides between the first and second surface),
the third surface being spaced apart from and parallel to the first surface and the second surface (paragraph 0018, figures 2-6, where the third surface [bottom surface of cavity 204] is parallel to the second surface [surface of 201 that touches 202a] and resides between the second and first surface [surface of 201 that touches elements 202a and 202b, respectively]);
a plurality of first top semiconductor device TSVs extending between the second surface and the third surface (figures 2-6, paragraphs 0016 and 0018, where element 206 is a ‘metal pillar’ defined in paragraph 0016 as a TSV, and connects the second surface and the third surface);
However, Lee et al does not specifically teach
[claim 7] A semiconductor device assembly, comprising: a package substrate; a stack of semiconductor devices coupled with the package substrate, each including a plurality of through silicon vias (TSVs); and at least one second top semiconductor device TSV extending between the first surface and the second surface.
However, Gu et al does teach
[claim 7] and at least one second top semiconductor device TSV extending between the first surface and the second surface (figure 2, col 7 lines 9-31, where element 208 is the substrate and equates to the substrate of Lee et al, the base reference. The cavity described by element 210 is the save as the cavity in Lee et al, the base reference. The TSV’s, element 262, extends from a second surface to a first surface of the substrate, element 208, outside the cavity).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al with the teachings of Gu et al in order to connect other circuits between the substrate, thus being able to integrate the IC that rests in the cavity of the substrate to be interconnected to other IC’s in a spatially efficient manner by stacking and connecting through TSV’s.
However, Lee et al as modified does not specifically teach
[claim 7] A semiconductor device assembly, comprising: a package substrate; a stack of semiconductor devices coupled with the package substrate, each including a plurality of through silicon vias (TSVs);
However, Yu et al does teach
[claim 7] a stack of a semiconductor devices coupled with the package substrate, each including a plurality of through silicon vias (TSVs) (figure 1J, paragraph 0014, where there are a stack of semiconductor devices [elements 112, 140, 150 and 200] coupled through a plurality of silicon vias [elements 120 and 130]);
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al to include the teachings of Yu et al in order to stack semiconductor die and electrically connect them through silicon vias to maximize spatial density by stacking chips vertically and interconnecting them vertically instead of laying them all out horizontally and connecting them horizontally, it reduces overall cost and amount of material used.
Claim(s) 8-10, 12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728) and Gu et al (US 9368450) and in further view of Yong et al (US 20200357744 A1).
Lee et al teaches all of the limitations of the parent claim, claim 7, but does not specifically disclose
[claim 8] the semiconductor device assembly of claim 7, wherein: the plurality of first top semiconductor device TSVs are exposed at the third surface.
[claim 9] the semiconductor device assembly of claim 7, further comprising: an additional semiconductor device positioned within the cavity of the semiconductor substrate and electrically coupled to the plurality of TSVs at the third surface.
[claim 10] the semiconductor device assembly of claim 9, wherein a top surface of the additional semiconductor device and the first surface are co-planar.
[claim 12] the semiconductor device assembly of claim 9, further comprising: a first plurality of contact pads of the top semiconductor device, wherein a respective conductivity pad of the first plurality of contact pads is coupled to a respective first top semiconductor device TSV of the plurality of top semiconductor device TSVs, a second plurality of contact pads of the additional semiconductor device, wherein the additional semiconductor device is electrically coupled with the plurality of first top semiconductor device TSVs by electrically coupling the first plurality of contact pads and the second plurality of contact pads.
[claim 14] the semiconductor device assembly of claim 7, further comprising: an encapsulating material at least partially encapsulating the stack of semiconductor devices.
[claim 15] the semiconductor device assembly of claim 7, further comprising: a passivation layer extending across the first surface, the third surface, and side-walls of the cavity region of the top semiconductor device.
[claim 16] the semiconductor device assembly of claim 7, wherein: each of the plurality of TSVs is separated from the semiconductor substrate, along a direction that is parallel to the first surface, by a corresponding layer of non- conductive material.
However, Yong et al teaches
[claim 8] the semiconductor device assembly of claim 7, wherein: the plurality of first top semiconductor device TSVs are exposed at the third surface (figure 3F, element 317 where the top of the TSV are exposed and not in the substrate 310A).
[claim 9] the semiconductor device assembly of claim 7, further comprising: an additional semiconductor device positioned within the cavity of the semiconductor substrate and electrically coupled to the plurality of TSVs at the third surface (figure 3F, element 320 is positioned on top of the TSV’s inside the cavity and coupled to the TSVs at the third surface).
[claim 10] the semiconductor device assembly of claim 9, wherein a top surface of the additional semiconductor device and the first surface are co-planar (figure 3F, the top surface of element 320 is co-planar with the bottom surface of 310A and 310B).
[claim 12] the semiconductor device assembly of claim 9, further comprising: a first plurality of contact pads of the top semiconductor device, wherein a respective conductivity pad of the first plurality of contact pads is coupled to a respective first top semiconductor device TSV of the plurality of top semiconductor device TSVs (figure 3F, element 322 are the contact pads connected to the TSV’s and the semiconductor device in the cavity);
a second plurality of contact pads of the additional semiconductor device, wherein the additional semiconductor device is electrically coupled with the plurality of first top semiconductor device TSVs by electrically coupling the first plurality of contact pads and the second plurality of contact pads (figure 3F, paragraph 0043, element 318 are contact structures connected to the TSVs on the other side of the substrate and electrically connected to the first contact structures through the TSVs [element 317]).
[claim 14] the semiconductor device assembly of claim 7, further comprising: an encapsulating material at least partially encapsulating the stack of semiconductor devices (figure 3F, element 343 is an encapsulant and encapsulates one semiconductor device which would be the top device, which partially encapsulates the entire stack).
[claim 15] the semiconductor device assembly of claim 7, further comprising: a passivation layer extending across the first surface, the third surface, and side-walls of the cavity region of the top semiconductor device (figure 3F, paragraph 0047, where elements 343 and 325 cover the first surface, the third surface and sidewalls of the cavity and are made of any suitable material like an epoxy, which is an oxide, and passivation layers are a type of oxide layer to insulate material, which said epoxy does).
[claim 16] the semiconductor device assembly of claim 7, wherein: each of the plurality of TSVs is separated from the semiconductor substrate, along a direction that is parallel to the first surface, by a corresponding layer of non- conductive material (figure 3F, paragraph 0047, element 325 [an epoxy] is non-conductive and separates the TSV’s).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al as modified with the teachings of Yong et al in order to create a stack of die such that the semiconductor device can be connected to other IC’s or semiconductor devices in a spatially efficient manner.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728) and Gu et al (US 9368450) and Yong et al (US 20200357744 A1) and in further view of Yu et al (US 20180012863 A1).
Lee et al as modified teaches all of the limitaitions of the parent claim, claim 9, but does not specifically disclose
[claim 11] the semiconductor device assembly of claim 9, wherein: the additional semiconductor device is a logic device, and the stack of semiconductor devices includes a plurality of memory devices managed by the logic device.
However, Yu et al does teach
[claim 11] the semiconductor device assembly of claim 9, wherein: the additional semiconductor device is a logic device, and the stack of semiconductor devices includes a plurality of memory devices managed by the logic device (paragraph 0020, where all of the semiconductor chips could include logic chips and memory die, thus the top chip [element 200] could be a logic chip controlling the memory chips [element 140 and 150] below).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al to include the teachings of Yu et al in order to stack semiconductor die and electrically connect them through silicon vias to maximize spatial density by stacking chips vertically and interconnecting them vertically instead of laying them all out horizontally and connecting them horizontally, it reduces overall cost and amount of material used.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728) and Gu et al (US 9368450) and Yong et al (US 20200357744 A1) in further view of Tadayon (US 20210035951 A1).
Lee et al as modified teaches the limitations of the parent claim, claim 10, but do not specifically disclose
[claim 13] the semiconductor device assembly of claim 10, further comprising: a thermally conductive heat sink coupled with the first surface of the top semiconductor device and the top surface of the additional semiconductor device.
However, Tadayon does teach
[claim 13] the semiconductor device assembly of claim 10, further comprising: a thermally conductive heat sink coupled with the first surface of the top semiconductor device and the top surface of the additional semiconductor device (figure 4, paragraph 0053, where the heat sink [elements 430 and 431 combined] it attached to a first [bottom surface] surface of a semiconductor die [element 430] and is also attached to the top surface of another semiconductor die [element 451]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teaches of Lee et al as modified to incorporate the teachings of Tadayon in order to dissipate heat from semiconductor die that are stacked on top of each other efficiently instead of allowing their heat to dissipate into the other semiconductor die, potentially overheating the die or package altogether.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703) 756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818