Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/03/2025 has been entered.
Response to Arguments
In response to the applicant’s arguments filed on 04/16/2026, the amendments made to the independent claims, claims 1 and 7, overcome the previous prior art rejection. Additionally, new claims 21 and 22 do not add new material. Regarding amended claim 1, since claim 3 was incorporated into claim 1, it should be noted for the record that the language from claim 3 was amended to include “continuously” which does change the scope of the claim, thus warranting further search and consideration. However, upon further search and consideration, a new rejection has been formulated below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728) in view of Gu et al (US 9368450) and in further view of Huang et al (CN 111952194).
Lee et al teaches
[claim 1] A semiconductor device, comprising: a semiconductor substrate having an upper surface and a lower surface opposite the upper surface (figures 2-6, paragraph 0018, element 201 is the semiconductor substrate with an upper surface [surface that touches element 202b], and a lower surface [surface that touches element 202a]),
wherein the semiconductor substrate includes a cavity and a peripheral region surrounding the cavity (figures 2-6, paragraph 0018, element 204 defines the cavity with a peripheral region surrounding the cavity),
wherein: in the peripheral region, the semiconductor substrate extends continuously from the upper surface to the lower surface and the cavity is formed into the upper surface and extends from the upper partially through the semiconductor substrate to an intermediate surface between the upper surface and the lower surface (figures 2-6, paragraph 0018, where the cavity [element 204] is formed in the substrate where outside the cavity there is a continuous formation of the substrate from the upper surface [surface of element 201 that touches 202b] to the lower surface [surface that touches element 202a], and the cavity forms an intermediate surface which is defined as the bottom of the cavity which resides between the upper and lower surface),
the intermediate surface being parallel to and spaced apart from the lower surface (paragraph 0018, figures 2-6, where the intermediate surface [bottom surface of cavity 204] is parallel to the lower surface [surface of 201 that touches 202a] and resides between the lower and upper surface [surface of 201 that touches elements 202a and 202b, respectively]);
a plurality of first through-silicon vias (TSVs) extending between the lower surface and the intermediate surface (figures 2-6, paragraphs 0016 and 0018, where element 206 is a ‘metal pillar’ defined in paragraph 0016 as a TSV, and connects the lower surface and the intermediate surface).
However, Lee et al does not specifically disclose
[claim 1] and at least one second through-silicon via (TSV) extending between the upper surface and the lower surface, a passivation layer extending continuously across the upper surface, side-walls of the cavity, and the intermediate surface.
However, Gu et al does teach
[claim 1] and at least one second through-silicon via (TSV) extending between the upper surface and the lower surface (figure 2, col 7 lines 9-31, where element 208 is the substrate and equates to the substrate of Lee et al, the base reference. The cavity described by element 210 is the save as the cavity in Lee et al, the base reference. The TSV’s, element 262, extends from a bottom surface to a top surface of the substrate, element 208, outside the cavity).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al with the teachings of Gu et al in order to connect other circuits between the substrate, thus being able to integrate the IC that rests in the cavity of the substrate to be interconnected to other IC’s in a spatially efficient manner by stacking and connecting through TSV’s.
However, Lee as modified does not specifically disclose
[claim 1] a passivation layer extending continuously across the upper surface, side-walls of the cavity, and the intermediate surface.
However, Huang et al does teach
[claim 1] a passivation layer extending continuously across the upper surface, side-walls of the cavity, and the intermediate surface (figure 5, paragraph 0079, where the passivation layer [element 106] extends continuously across the upper surface, inner sidewalls and the intermediate surface [the bottom surface of the cavity 105 as shown in figure 4]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to modify the teachings of Lee as modified with the teachings of Huang et al in order to protect the substrate to enhance durability.
Regarding claim 2, Lee et al further discloses
[claim 2] The semiconductor device, wherein: the cavity is configured to receive an additional semiconductor device electrically coupled with the plurality of first TSVs at the intermediate surface (figure 2, paragraph 0018, where element 206 [TSVs] are attached to a semiconductor device [element 208]).
Claim(s) 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728), Gu et al (US 9368450), and Huang et al (CN 111952194) in further view of Yong et al (US 20200357744 A1).
Lee et al teaches all of the limitations of the parent claim, claims 1, but does not specifically disclose
[claim 4] the semiconductor device of claim 1, wherein the plurality of first TSVs are exposed at the intermediate surface.
[claim 5] the semiconductor device of claim 4, further comprising: a plurality of contact pads, wherein each contact pad of the plurality of contact pads is formed directly upon a respective TSV of the plurality of first TSVs.
[claim 6] the semiconductor device of claim 1, wherein: each of the plurality of first TSVs is spaced apart from the semiconductor substrate by a layer of non-conductive material.
However, Yong et al does teach
[claim 4] the semiconductor device of claim 1, wherein the plurality of first TSVs are exposed at the intermediate surface (figure 1A, paragraphs 0030-0032, where element 117 can be seen to go through the substrate and be exposed before connecting to the semiconductor device, element 120, at the third surface 114).
[claim 5] the semiconductor device of claim 4, further comprising: a plurality of contact pads, wherein each contact pad of the plurality of contact pads is formed directly upon a respective TSV of the plurality of first TSVs (paragraph 0032, figure 1A, element 122 are contact pads that connect the plurality of TSV’s [element 117]).
[claim 6] the semiconductor device of claim 1, wherein: each of the plurality of first TSVs is spaced apart from the semiconductor substrate by a layer of non-conductive material (figure 3F, paragraph 0047, element 325 [an epoxy] is non-conductive and separates the TSV’s).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al as modified to incorporate the teachings of Yong et al in order to adequately connect the IC to the TSV’s in the cavity to form the strongest electrical connection for maximal efficiency of the device.
Claims 7, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728) in view of Chandolu et al (US 20190206766).
However, Lee et al does teach
[claim 7] a semiconductor substrate having a first surface and a second surface spaced apart from and parallel to the first surface (figures 3a-3h, paragraph 0020, where element 201 is the semiconductor substrate and has a first surface [top surface] and the second surface [bottom surface] spaced part from each other and parallel to one another),
wherein the semiconductor substrate includes a cavity and a peripheral region surrounding the cavity (paragraph 20, figures 3a-3h, where element 204 is the cavity, and the peripheral region is the region around the cavity),
wherein: the cavity is formed into the first surface and extends from the first surface partially through the semiconductor substrate to a third surface between the first surface and the second surface, the third surface being spaced apart from and parallel to the first surface and the second surface (paragraph 0020, figures 3a-3h, where the cavity [element 204] is formed within the substrate [element 201] to a third surface [bottom surface of the cavity] which lies between the first and second surfaces [top and bottom surfaces of element 201] and is parallel to both the top and the bottom surface [first and second surfaces]);
a plurality of first top semiconductor device TSVs extending between the second surface and the third surface (figures 3a-3h, paragraph 0022, where element 203a is the through vias that extend from the second surface [bottom surface] to the third surface [bottom surface of the cavity]).
However, Lee et al does not specifically disclose
[claim 7] A semiconductor device assembly, comprising: a package substrate, a stack of semiconductor devices coupled with the package substrate, each including a plurality of through silicon vias (TSVs) including a plurality of first TSVs formed in a first region and at least one second TSV formed in a second region spaced apart from the first region, and a top semiconductor device of the stack, and at least one second top semiconductor device TSV extending between the first surface and the second surface, the cavity is vertically aligned with the first region of each of the plurality of semiconductor devices; and the peripheral region is vertically aligned with the second region of each of the plurality of semiconductor devices.
[claim 21] The semiconductor device assembly of claim 7, wherein each semiconductor device in the stack of semiconductor devices has first base substrate having a first longitudinal footprint, and wherein the semiconductor substrate of the top semiconductor device has a second longitudinal footprint equal to the first longitudinal footprint.
[claim 22] The semiconductor device assembly of claim 7, wherein the stack of semiconductor devices comprises: a first semiconductor device having a first plurality of TSVs; a second semiconductor device carried by the first semiconductor device and having a second plurality of TSVs, wherein each of the second plurality of TSVs is coupled to a corresponding one of the first plurality of TSVs via an electrical coupler between the first semiconductor device and the second semiconductor device; and a filler material between the first semiconductor device and the second semiconductor device surrounding the electrical couplers.
Chandolu et al teaches
[claim 7] A semiconductor device assembly, comprising: a package substrate (figure 3, paragraph 0031, where the semiconductor die of Lee et al is in place of the top die of Chandolou et al [figure 3, element 202 on top], where element 330 is the package, element 340 is the package substrate);
a stack of semiconductor devices coupled with the package substrate (figure 3, paragraph 0031, where element 202 is the stack of semiconductor devices coupled to the package substrate through element 308),
each including a plurality of through silicon vias (TSVs) including a plurality of first TSVs formed in a first region and at least one second TSV formed in a second region spaced apart from the first region (figure 3, paragraph 0031, where element 208 is the plurality of TSV’s, where the middle three TSV’s constitute the first region, and the outer two TSV’s on each side of the middle three TSV’s constitute the second region which is spaced apart from the first region),
and a top semiconductor device of the stack including (figure 3, paragraph 0031, where the top die [element 202] is the top semiconductor die]),
and at least one second top semiconductor device TSV extending between the first surface and the second surface (figure 3, paragraph 0031, where the lefthand side TSV’s [element 208] extends from the first surface to the second surface [bottom surface to the top surface]),
the cavity is vertically aligned with the first region of each of the plurality of semiconductor devices; and the peripheral region is vertically aligned with the second region of each of the plurality of semiconductor devices (figure 3a-3h, paragraph 0021 of Lee et al, where the device of Lee et al is in place of the top semiconductor device [element 202] of Chandolou et al [figure 3], and when in such a position the peripheral region is vertically aligned with the second region [region surrounding the cavity of Lee et al is vertical, and so is the second region of Chandolou et al]).
[claim 21] The semiconductor device assembly of claim 7, wherein each semiconductor device in the stack of semiconductor devices has first base substrate having a first longitudinal footprint, and wherein the semiconductor substrate of the top semiconductor device has a second longitudinal footprint equal to the first longitudinal footprint (figure 3, paragraphs 0020 and 0031, where each semiconductor device [element 201 and 202] has the exact same longitudinal footprint [size left to right] and contains a substrate [paragraph 0020], thus the longitudinal footprint of the first semiconductor substrates [the bottom three 202 elements] all have a substrate the same longitudinal footprint as the top semiconductor device).
[claim 22] The semiconductor device assembly of claim 7, wherein the stack of semiconductor devices comprises: a first semiconductor device having a first plurality of TSVs (figure 3, paragraph 0031, where the bottom element 201 and 202 is the first semiconductor device and has a plurality of first TSVs [element 208]);
a second semiconductor device carried by the first semiconductor device and having a second plurality of TSVs, wherein each of the second plurality of TSVs is coupled to a corresponding one of the first plurality of TSVs via an electrical coupler between the first semiconductor device and the second semiconductor device (paragraph 0031, figure 3, where the second semiconductor device is the second from the bottom device designated by element 201 and 202 which has a plurality of TSv’s [element 208] which extend through the device and couple the first [bottom] and second [second from bottom] semiconductor devices);
and a filler material between the first semiconductor device and the second semiconductor device surrounding the electrical couplers (figure 3, paragraph 0033, where element 350 is the filler material between the first and second semiconductor devices and surrounding the electrical couplers between the two).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al with the teachings of Chandolu et al in order to attach a semiconductor device to more semiconductor devices below it to maximite spatial density for connected semiconductor devices.
Claim(s) 8-10, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728), and Chandolu et al (US 20190206766) and in further view of Yong et al (US 20200357744 A1).
Lee et al teaches all of the limitations of the parent claim, claim 7, but does not specifically disclose
[claim 8] the semiconductor device assembly of claim 7, wherein: the plurality of first top semiconductor device TSVs are exposed at the third surface.
[claim 9] the semiconductor device assembly of claim 7, further comprising: an additional semiconductor device positioned within the cavity of the semiconductor substrate and electrically coupled to the plurality of TSVs at the third surface.
[claim 10] the semiconductor device assembly of claim 9, wherein a top surface of the additional semiconductor device and the first surface are co-planar.
[claim 12] the semiconductor device assembly of claim 9, further comprising: a first plurality of contact pads of the top semiconductor device, wherein a respective conductivity pad of the first plurality of contact pads is coupled to a respective first top semiconductor device TSV of the plurality of top semiconductor device TSVs, a second plurality of contact pads of the additional semiconductor device, wherein the additional semiconductor device is electrically coupled with the plurality of first top semiconductor device TSVs by electrically coupling the first plurality of contact pads and the second plurality of contact pads.
[claim 14] the semiconductor device assembly of claim 7, further comprising: an encapsulating material at least partially encapsulating the stack of semiconductor devices.
However, Yong et al teaches
[claim 8] the semiconductor device assembly of claim 7, wherein: the plurality of first top semiconductor device TSVs are exposed at the third surface (figure 3F, element 317 where the top of the TSV are exposed and not in the substrate 310A).
[claim 9] the semiconductor device assembly of claim 7, further comprising: an additional semiconductor device positioned within the cavity of the semiconductor substrate and electrically coupled to the plurality of TSVs at the third surface (figure 3F, element 320 is positioned on top of the TSV’s inside the cavity and coupled to the TSVs at the third surface).
[claim 10] the semiconductor device assembly of claim 9, wherein a top surface of the additional semiconductor device and the first surface are co-planar (figure 3F, the top surface of element 320 is co-planar with the bottom surface of 310A and 310B).
[claim 12] the semiconductor device assembly of claim 9, further comprising: a first plurality of contact pads of the top semiconductor device, wherein a respective conductivity pad of the first plurality of contact pads is coupled to a respective first top semiconductor device TSV of the plurality of top semiconductor device TSVs (figure 3F, element 322 are the contact pads connected to the TSV’s and the semiconductor device in the cavity);
a second plurality of contact pads of the additional semiconductor device, wherein the additional semiconductor device is electrically coupled with the plurality of first top semiconductor device TSVs by electrically coupling the first plurality of contact pads and the second plurality of contact pads (figure 3F, paragraph 0043, element 318 are contact structures connected to the TSVs on the other side of the substrate and electrically connected to the first contact structures through the TSVs [element 317]).
[claim 14] the semiconductor device assembly of claim 7, further comprising: an encapsulating material at least partially encapsulating the stack of semiconductor devices (figure 3F, element 343 is an encapsulant and encapsulates one semiconductor device which would be the top device, which partially encapsulates the entire stack).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al as modified with the teachings of Yong et al in order to create a stack of die such that the semiconductor device can be connected to other IC’s or semiconductor devices in a spatially efficient manner.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728), and Chandolu et al (US 20190206766) and Yong et al (US 20200357744 A1) and in further view of Yu et al (US 20180012863 A1).
Lee et al as modified teaches all of the limitaitions of the parent claim, claim 9, but does not specifically disclose
[claim 11] the semiconductor device assembly of claim 9, wherein: the additional semiconductor device is a logic device, and the stack of semiconductor devices includes a plurality of memory devices managed by the logic device.
However, Yu et al does teach
[claim 11] the semiconductor device assembly of claim 9, wherein: the additional semiconductor device is a logic device, and the stack of semiconductor devices includes a plurality of memory devices managed by the logic device (paragraph 0020, where all of the semiconductor chips could include logic chips and memory die, thus the top chip [element 200] could be a logic chip controlling the memory chips [element 140 and 150] below).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Lee et al to include the teachings of Yu et al in order to stack semiconductor die and electrically connect them through silicon vias to maximize spatial density by stacking chips vertically and interconnecting them vertically instead of laying them all out horizontally and connecting them horizontally, it reduces overall cost and amount of material used.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728), and Chandolu et al (US 20190206766), and Yong et al (US 20200357744 A1) in further view of Tadayon (US 20210035951 A1).
Lee et al as modified teaches the limitations of the parent claim, claim 10, but do not specifically disclose
[claim 13] the semiconductor device assembly of claim 10, further comprising: a thermally conductive heat sink coupled with the first surface of the top semiconductor device and the top surface of the additional semiconductor device.
However, Tadayon does teach
[claim 13] the semiconductor device assembly of claim 10, further comprising: a thermally conductive heat sink coupled with the first surface of the top semiconductor device and the top surface of the additional semiconductor device (figure 4, paragraph 0053, where the heat sink [elements 430 and 431 combined] it attached to a first [bottom surface] surface of a semiconductor die [element 430] and is also attached to the top surface of another semiconductor die [element 451]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teaches of Lee et al as modified to incorporate the teachings of Tadayon in order to dissipate heat from semiconductor die that are stacked on top of each other efficiently instead of allowing their heat to dissipate into the other semiconductor die, potentially overheating the die or package altogether.
Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20140110728), and Chandolu et al (US 20190206766) and in further view of Huang et al (CN 111952194).
Lee et al as modified teaches all of the limitations of the parent claim, claim 7, but does not specifically disclose
[claim 15] The semiconductor device assembly of claim 7, further comprising: a passivation layer extending continuously across the first surface, the third surface, and side-walls of the cavity region of the top semiconductor device.
However, Huang et al does teach
[claim 15] The semiconductor device assembly of claim 7, further comprising: a passivation layer extending continuously across the first surface, the third surface, andside-walls of the cavity region of the top semiconductor device (figure 5, paragraph 0079, where the passivation layer [element 106] extends continuously across the upper surface, inner sidewalls and the intermediate surface [the bottom surface of the cavity 105 as shown in figure 4]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to modify the teachings of Lee as modified with the teachings of Huang et al in order to protect the substrate to enhance durability.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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