DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed July 8, 2025. Claims 1, 6, 9-11 and 13 have been amended. No claims have been added. Claims 5, 8, and 12 have been canceled. Claims 11, and 13-15 stand withdrawn. Currently, claims 1-4, 6-7, and 9-10 are pending.
Response to Arguments
Applicant's arguments filed July 8, 2025 have been fully considered but they are not persuasive.
Applicant asserts that Lowe et al. (US 20220310637 A1) herein after “Lowe”, Lee (US 20220139920 A1) and Pandey et al. (US 10756093 B1) herein after “Pandey” in combination not disclose the limitations of newly amended claim 1. Specifically, that “Pandey provides no disclosure or indication that given silicon pillar is provided with an upper portion and a lower portion, the upper portion contacts with a capacitor, the lower portion contacts with a bit line, not to mention that the upper portion being smaller than the lower portion in size, on this basis, the gate-all-around structure may be arranged around the upper portion and positioned below the conductive layer at intervals”. Therefore, “Pandey, whether considered separately or in a combination, fail to disclose, teach, or suggest at least the above features as claimed, and therefore fail to cure at least the aforementioned deficiencies of Lowe and Lee”.
The Examiner respectfully disagrees with the assertion that Pandey provides no disclosure or indication that given silicon pillar is provided with an upper portion and a lower portion. As outlined on pages 7-8 of the previous Office Action, and shown in the annotation of Fig. 4B of Pendey, Pandey discloses wherein the given silicon pillar (Fig. 4B, active regions 12, col. 3, line 16) is provided with an upper portion (see Annotation 2, Fig. 4B of Pandey, UP2) and a lower portion (see Annotation of Fig. 4B of Pandey, LP2).
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Annotation of Fig. 4B of Pandey
Drawings can be used to anticipate claims if they clearly show the structure as claimed (see MPEP 2125). The figure shows that the silicon pillars have an upper portion and a lower portion. Furthermore, Fig. 4B shows that the upper portion (UP2) being smaller than the lower portion (LP2) in size (see Annotation of Fig. 4B of Pandey where the width of the upper portion is less than the width of the lower portion).
Pandey was not relied upon by the Examiner to disclose or suggest “the upper portion contacts with a capacitor, the lower portion contacts with a bit line…, the gate-all-around structure may be arranged around the upper portion and positioned below the conductive layer at intervals”. Claim 1 does not required that “the upper portion contacts with a capacitor, the lower portion contacts with a bit line”. Further, as outlined on page 5 of the previous Office Action, Lowe was relied upon to disclose a gate-all-around structure (Fig. 5, conductive metal-containing material 34, ¶ [0046]) is arranged around upper portion (20) and positioned below the conductive layer (42) at intervals.
Therefore, the Examiner asserts that the combination of Lowe, Lee and Pandey discloses all the limitations of newly amended claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lowe et al. (US 20220310637 A1) herein after “Lowe” in view of Lee (US 20220139920 A1) and Pandey et al. (US 10756093 B1) herein after “Pandey”.
Regarding claim 1, Fig. 5 of Lowe discloses a semiconductor structure (Fig. 5, construction 10, ¶ [0016]), comprising a substrate (Fig. 5, semiconductor material 12, ¶ [0018]), wherein
a plurality of trenches (see Annotation 1, Fig. 5 of Lowe, T) are crisscross arranged in the substrate (12), such that a plurality of silicon pillars (Fig. 5, pillars 20, ¶ [0020]) are formed on the substrate (12), and each of the plurality of trenches (T) is filled with a spacer (Fig. 5, insulative material 44, ¶ [0037]),
a conductive layer (Fig. 5, conductive caps 42, ¶ [0036]) being arranged at a top of a given one of the plurality of silicon pillars (20), the conductive layer (42) covering a top surface of the given silicon pillar (Fig. 5, “conductive caps 42 are formed directly against the semiconductor material 12 of the pillars 20”, ¶ [0036]), and
the conductive layer (42) being configured to contact with a capacitor (Fig. 5, storage elements 48, ¶ [0038]);
a gate-all-around structure (Fig. 5, conductive metal-containing material 34, ¶ [0046]) is arranged around the given silicon pillar (20), a dielectric layer (Fig. 4, insulative material 24, ¶ [0021]) being arranged between the gate-all-around structure (34) and the given silicon pillar (20);
the given silicon pillar (20) is provided with an upper portion (see Annotation 1, Fig. 5 of Lowe, UP) and a lower portion (see Annotation 1, Fig. 5 of Lowe, LP), the upper portion (UP) being connected to an upper end of the lower portion (LP), and the gate-all-around structure (34) being arranged around the upper portion (UP) and being positioned below the conductive layer (42) at intervals.
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Annotation 1, Fig. 5 of Lowe
Lowe fails to disclose the conductive layer covering a partial side surface thereof adjacent to the top surface;
the upper portion being smaller than the lower portion in size.
In the similar field of endeavor of memory cells, Fig. 2E of Lee discloses the conductive layer (Fig. 2E, internal electrode 235, ¶ [0057]) covering a partial side surface thereof adjacent to the top surface (Fig. 2E, “the internal electrode surrounds a top portion of semiconductor pillars 204”, ¶ [0058]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure of Lowe with the conductive layer disclosed by Lee, to enhance contact area and reduce resistance (see Lee, ¶ [0058]).
Lee fails to disclose the upper portion being smaller than the lower portion in size.
In the similar field of endeavor of DRAM cells, Fig. 4B of Pandey discloses wherein the given silicon pillar (Fig. 4B, active regions 12, col. 3, line 16) is provided with an upper portion (see Annotation 2, Fig. 4B of Pandey, UP2) and a lower portion (see Annotation 2, Fig. 4B of Pandey, LP2), the upper portion (UP2) being smaller than the lower portion (LP2) in size (see Annotation 2, Fig. 4B of Pandey where the width of the upper portion is less than the width of the lower portion).
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Annotation 2, Fig. 4B of Pandey
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure of Lowe with the silicon pillar as disclosed by Pandey, to further divide the upper portions of the pillars (see Pandey, col. 4, lines 49-51).
Regarding claim 2, Lowe, Lee and Pandey together disclose the semiconductor structure according to claim 1 as applied above, and Fig. 5 of Lowe further discloses wherein a top surface of the spacer (44) is flush with a top surface of the conductive layer (42) (shown in Fig. 5).
Regarding claim 3, Lowe, Lee and Pandey together disclose the semiconductor structure according to claim 1 as applied above, and Fig. 5 of Lowe further discloses wherein a material of the spacer (44) is silicon nitride (“The insulative material 44 may comprise any suitable composition(s), and in some embodiments may comprise, consist essentially of, or consist of… silicon nitride”, ¶ [0037]).
Regarding claim 4, Lowe, Lee and Pandey together disclose the semiconductor structure according to claim 1 as applied above, and Fig. 5 of Lowe further discloses wherein a material of the conductive layer (42) is titanium nitride or tungsten (“The conductive caps 42 may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride”, ¶ [0034]).
Regarding claim 6, Lowe, Lee and Pandey together disclose the semiconductor structure according to claim 1 as applied above, and Fig. 5 of Lowe further discloses wherein the dielectric layer (24) covers rest of side surface (Fig. 5, “the insulative material 24 extends along sidewalls 21 of the pillars 20”, ¶ [0021]) of the given silicon pillar (20) not covered by the conductive layer (42).
Regarding claim 9, Lowe, Lee and Pandey together disclose the semiconductor structure according to claim 1 as applied above, and Fig. 5 of Lowe further discloses wherein a material of the gate-all-around structure (34) is titanium nitride or tungsten (“The highly conductive metal-containing material may include, for example, one or more of… tungsten (W)…, conductive metal nitride… The patterned highly-conductive metal-containing material may be utilized to form conductive gating structures of the transistors”, “Some embodiments include transistors having conductive gating material which includes TiN”, ¶ [0012-0013]).
Regarding claim 10, Lowe, Lee and Pandey together disclose the semiconductor structure according to claim 1 as applied above, and Fig. 5 of Lowe further discloses wherein a material of the dielectric layer (24) is silicon oxide (“the insulative material 24 may comprise, consist essentially of, or consist of one or more of silicon dioxide”, ¶ [0022]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lowe (US 20220310637 A1), Lee (US 20220139920 A1) and Pandey (US 10756093 B1) in further view of Chern et al. (US 20220037332 A1) herein after “Chern”.
Regarding claim 7, Lowe, Lee and Pandey together disclose the semiconductor structure according to claim 6 as applied above, but the combination fails to disclose wherein the dielectric layer and the conductive layer are equal in thickness.
In the similar field of endeavor of DRAM devices, Fig. 8 of Chern discloses wherein the dielectric layer (Fig. 8, dielectric layer 620, ¶ [0045]) and the conductive layer (Fig. 8, conductive layer 610, ¶ [0044]) are equal in thickness (Fig. 8, “the conductive layer 610 may have a thickness of about 1-15 nm”, “the capacitor dielectric layer 620 may have a thickness of about 1-10 nm”, ¶ [0043] and [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor structure of Lowe with the layers as disclosed by Chern, to simplify the fabrication process (see Chern, ¶ [0046]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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