DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The amendment filed 08/05/2026 has been received and considered. Claims 1-20 are presented for examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/05/2026 has been entered.
Claim Objections
Claims include the typo “ ,”. Examiner interprets as “," for examination purposes.
Claim 17, line 5 includes the typo “dm,”. Examiner interprets as “dm" for examination purposes.
Appropriate correction or clarification is required.
Claim Rejections -35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without any additional elements that provide a practical application or amount to significantly more than the abstract idea.
Independent claim 1, Step 1: method (process = 2019 PEG Step 1 = yes).
Independent claim 1, Step 2A, Prong One: Claim recites:
transforming in parallel, elements of each group of a plurality of groups of elements of a tensor X into respective power-of-two elements by a processor circuit, wherein the respective power-of-two element from element xt of the tensor is pt, pt = (xt * log2e), and pt has an integer part and a fraction part; determining respective group-level biases for the groups by a comparison circuit, wherein the group-level bias of groupm is dm, and dm is an integer part of a maximum of the power-of-two elements of groupm; determining a greatest one of the respective group-level biases by the comparison circuit to be a tensor-level bias, dmax
… adjusting the respective group-biased elements based on the respective group-level biases and the tensor-level bias to generate respective tensor-biased elements; and determining softmax values for the elements of the tensor based on the respective tensor-biased elements and the tensor-level sum.
The limitations are substantially drawn to mathematical concepts: mathematical relationships, formulas or equations, and calculations, but for the recitation of generic computer components. Information and data also fall within the realm of abstract ideas because information and/or data are intangible. See Electric Power Group1 (Electric Power hereinafter): “Information… is an intangible”.
As to the limitations "transforming… groups of elements of a tensor X into respective power-of-two elements" and “determining a greatest one of the respective group-level biases by the comparison circuit to be a tensor-level bias, dmax”, under their broadest reasonable interpretations, the transforming and determining are mathematical concepts: calculations. The specification reads (underline emphasis added):
"[0019]… computing dmax by dividing an input tensor is divided into several groups, converting tensor elements into power-of-two values, determining group-level biases, adjusting the power-of-two values according to the group-level biases, and summing the adjusted values of the groups"
As to the limitations "adjusting the respective group-biased elements based on the respective group-level biases and the tensor-level bias to generate respective tensor-biased elements”, under their broadest reasonable interpretations, they are mathematical concepts: calculations. The specification reads (underline emphasis added):
"[0025]… the group-biased power-of-two values (ex_t *2-d_m) are tensor-wise adjusted based on the tensor-level dmax value. The tensor-wise biases for elements in groupm are made by retrieving from buffer2, dm and exponents of the associated group-wise-adjusted power-of-two values ex_t *2-d_m".
As to the limitations "determining softmax values for the elements of the tensor based on the respective tensor-biased elements and the tensor-level sum", the claimed invention further reads “3… wherein the softmax value of xt = (tensor-biased element corresponding to xt)/(tensor-level sum)”.
If a claim limitation, under its broadest reasonable interpretation, covers mathematical concepts, then it falls within the "(a) Mathematical concepts" grouping of abstract ideas. Independent claim is substantially drawn to mathematical concepts (2019 PEG Step 2A, Prong One: Abstract Idea Grouping? = Yes, (a) Mathematical concepts).
Independent claim 1, Step 2A Prong two: As to the additional element processor circuit, it is recited as performing generic computer functions routinely used in computer applications.
As to the limitations "comparing, by a compare-and-select circuit, a first group-level bias of a first group of the plurality of groups, as determined by the comparison circuit, with a current maximum bias, wherein the current maximum bias is a current value of dmax stored in a register; and selecting, by the compare-and-select circuit and based on the comparison, the greater of the first group-level bias and the current maximum bias to store in the register as a new dmax" and "generating, for each group, respective group-biased elements by adjusting in parallel, using a plurality of adder circuits, the respective power-of-two elements based on the group-level bias of the group; accumulating, by an accumulator circuit and an update circuit, the respective group-biased elements into a tensor-level sum"; they represent no more than just “apply it” limitations, because they invoke other machinery merely as a tool to perform an existing process.
The additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea (2019 PEG Step 2A, Prong Two: Additional elements that integrate the Judicial Exception/Abstract idea into a practical application?= NO).
Independent claim 1, Step 2B: As discussed with respect to Step 2A, Prong two, the claim recites the additional element processor circuit at a high level of generality and as performing generic computer functions routinely used in computer applications. Generic computer components recited as performing generic computer functions that are well-understood, routine and conventional activities amount to no more than implementing the abstract idea with a computerized system. The use of a computer to implement the abstract idea of a mathematical algorithm has not been held by the courts to be enough to qualify as “significantly more”. See MPEP 2106.05. The implementation on a computing system is described in the specification (underline emphasis added):
"[0026] FIG. 2 shows an exemplary circuit arrangement 200 for computing softmax and log(softmax) functions on a tensor X. The circuit arrangement generally includes one or more processor circuits configured to perform parallel multiply-and-accumulate operations, registers for storing temporary result values, and various addition and subtraction circuits”.
As discussed with respect to Step 2A, Prong two, limitations invoking other machinery merely as a tool to perform an existing process are just “apply it” limitations. See MPEP 2106.05(f)(2). In combination, these limitations amount to implementation of mental concepts including observations, evaluations, judgments, opinions, and mathematical concepts.
As to the limitations "comparing, by a compare-and-select circuit, a first group-level bias of a first group of the plurality of groups, as determined by the comparison circuit, with a current maximum bias, wherein the current maximum bias is a current value of dmax stored in a register; and selecting, by the compare-and-select circuit and based on the comparison, the greater of the first group-level bias and the current maximum bias to store in the register as a new dmax"; comparisons and selections are mental in nature. These limitations, as drafted and under a broadest reasonable interpretation, can be characterized as entailing a user evaluating information (evaluations, judgments, opinions), that can be performed in the human mind or by a human using a pen and paper. See for example in the Specification, the maximum value selector "compare-and-select circuit 206" (underline emphasis added):
"[0006]… determining a greatest one of the respective group-level biases by the comparison circuit (206) to be a tensor-level bias, dmax…
[0026] FIG. 2 shows an exemplary circuit arrangement 200 for computing softmax and log(softmax) functions on a tensor X. The circuit arrangement generally includes one or more processor circuits configured to perform parallel multiply-and-accumulate operations, registers for storing temporary result values, and various addition and subtraction circuits.
[0027]… The compare-and-select circuit 206 compares the dm value from circuit 204 to the current dmax value in register 208 and selects the greater of the two values to update the contents of the register".
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The claim recites "register" at a high level of generality and as performing generic register functions routinely used in circuit applications. Examiner notes that the limitations "comparison circuit" and "compare-and-select circuit", are well known to persons of ordinary skill in related areas since 1988. Lazzaro, Ryckebusch, Mahowald, & Mead, "Winner-Take-All Networks of O(N) Complexity", discloses (see page 709) – underline emphasis added:
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As to the limitations "generating, for each group, respective group-biased elements by adjusting in parallel, using a plurality of adder circuits, the respective power-of-two elements based on the group-level bias of the group", under their broadest reasonable interpretations, they amount to implementation of mathematical concepts: calculations. The specification reads (underline emphasis added):
"[0022]… 2(x_t)_j values for a group are determined by polynomial fitting, and the power-of-two values are adjusted by xt_k -dm + (the exponent bits of 2(x_t)_j)"
The claim recites "adder circuits" at a high level of generality and as performing generic register functions routinely used in circuit applications. Examiner notes that the limitations "adder circuits", are well known to persons of ordinary skill in related areas. Katsuhiro, (Katsuhiro hereinafter), International Pub. No. JP2018120547, discloses (see page 14, 3rd paragraph):
"a mask circuit capable of setting a plurality of outputs of the plurality of first registers as one of an input and a non-input at an input of the fourth adder"
As to the limitations "accumulating, by an accumulator circuit and an update circuit, the respective group-biased elements into a tensor-level sum”, under their broadest reasonable interpretations, they amount to implementation of mathematical concepts: calculations. The specification reads (underline emphasis added):
"[0023] The adjusted power-of-two values are accumulated into a group-level sum (2-d_m summ=SUMgroup_m = sum(ex_t *2-d_m) for all t in groupm) as the adjusted power-of-two values are computed. The group-level sums are accumulated into a tensor-level sum as each group is accumulated"
The claim recites "accumulator circuit and an update circuit" at a high level of generality and as performing generic register functions routinely used in circuit applications. Examiner notes that the limitations "accumulator circuit and an update circuit", are well known to persons of ordinary skill in related areas. Katsuhiro discloses (see page 8, 2nd paragraph):
'an accumulator ACML that accumulates the product-sum addition values of the eight sets of image data X0-X7 and coefficients W0-W7 latched by the register RG40 in synchronization with the clock. The initial value IV of the accumulator is “0”, and the adder AD50 adds the product-sum value of the register RG40 to the input value selected by the selector Sa0, and the register RG50 latches the added value. That is, accumulator ACML cumulatively adds the product-sum values of register RG40'
Thus, taken alone the individual additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as an ordered combination adds nothing that is not already present when looking at the additional elements taken individually. There is no indication that their combination improves the functioning of a computer itself or improves any other technology (underline emphasis added). Therefore, the claim does not amount to significantly more than the abstract idea itself (2019 PEG Step 2B: NO).
Claim 11 recites substantially the same elements as claim 1 and is rejected for the same reasons above. Further, the additional element a circuit arrangement is rejected below:
Independent claim 11, Step 2A Prong two and 2B: As to the further additional element a circuit arrangement, it is interpreted as drawn to a generic computer. As to the further circuit additional elements; see Independent claim 1, Step 2B above.
Dependent claims, Step 2A, Prong One: Dependent claims limitations further the mathematical concepts of their independent claims. (See Independent claim 1, Step 2A, Prong One above). If a claim limitation, under its broadest reasonable interpretation, covers mathematical concepts, then it falls within the "(a) Mathematical concepts" grouping of abstract ideas. Dependent claims are substantially drawn to mathematical concepts (2019 PEG Step 2A, Prong One: Abstract Idea Grouping? = Yes, (a) Mathematical concepts).
Dependent claims, Step 2A Prong Two and Step 2B:
As to the circuit limitations of claims 2, 7, 10, 12, 13, 16, 17, and 20; these limitations represent no more than just “apply it” limitations, because they invoke other machinery merely as a tool to perform an existing process. (See Independent claim 1, Step 2B above).
As to the further additional elements "5… a first processor circuit… a second processor circuit, and the first processor circuit and the second processor circuit operate in parallel" and "6… a first processor circuit… a second processor circuit… activating the first processor circuit and deactivating the second processor circuit in response to a first state of mode control signals; and deactivating the first processor circuit and activating the second processor circuit in response to a second state of the mode control signals", they are interpreted as drawn to a generic computer. (See Independent claim 1, Step 2B above).
This judicial exception is not integrated into a practical application of the exception (2019 PEG Step 2A, Prong Two: Additional elements that integrate the Judicial exception/Abstract idea into a practical application? = NO).
The claims do not provide an inventive concept in Step 2B. Therefore, the dependent claims do not amount to significantly more than the abstract idea itself (2019 PEG Step 2B: NO).
Allowable Subject Matter
Claims 1-20 are allowable over prior art of record. They will be allowed once all outstanding rejections/objections are traversed.
A reason for the indication of allowable subject matter was provided in the Office Action dated 05/29/2026.
Response to Arguments
Regarding the Claim Objections, the amendment corrected no deficiencies.
Regarding the rejections under 101, Applicant's arguments have been considered, but they are not persuasive. Applicant argues, (see page 9, next to last paragraph to page 11, next to last paragraph; page 13, last paragraph to page 16, 1st paragraph):
‘… Starting with prong one of step 2A, the amended claims do not recite a judicial exception, at all…
… claims are directed at a specific implementation of a set of circuitry components arranged in a way to perform a series of operations, including comparing, determining, transforming, and storing. That is, claim 1, as amended, recites a specific, ordered arrangement of purpose-built circuits (comparison circuit, compare-and-select circuit, register, plurality of adder circuits, accumulator circuit, update circuit) that transforms the input tensor into softmax values. Accordingly, the claims are directed to a hardware implementation of the softmax operations, and not on any mathematical operations or concepts themselves…
… operations, which determine the maximum value across a plurality of different groups by using special purpose computing components (e.g., the comparison circuit, the compare-and-select circuit, and the register) and then generate, accumulate, adjust, and compute softmax values using additional circuits (e.g., the plurality of adder circuits, the accumulator circuit, and the update circuit), are a clear and practical application of any alleged abstract idea…
… MPEP further notes that "[w]hen determining whether a machine recited in a claim provides significantly more," relevant factors may include "the particularity of generality of the elements of the machine or apparatus," "whether the machine or apparatus implements the steps of the method," and "whether its involvement is extra- solution activity or a field-of-use…
… claims represent special purpose computing circuitry that imposes meaningful limits on the claim. That is, the components described therein (e.g., the "comparison circuit," the "compare-and-select circuit," the "register," the "plurality of adder circuits," the "accumulator circuit," and the "update circuit"), do not execute insignificant aspects of the claim methods, such as "mere data gathering" steps, but instead implement core aspects of the claimed methods by which the overall bias is determined, the group-biased elements are generated and accumulated, and the softmax values are ultimately computed. Additionally, Applicant notes that the components described herein do not perform isolated functions or operations, but instead work together to execute the significant aspects of the claim. That is, output from the register and the comparison circuit are fed into the compare-and-select circuit, which in turn updates the register as needed to track, over time, a maximum bias; the plurality of adder circuits then use the group-level biases to generate group-biased elements; and the accumulator circuit and update circuit accumulate those elements into a tensor-level sum used to determine the final softmax values. In this way, the circuits are interconnected and work in concert to produce the claimed result…'
The MPEP reads (underline emphasis added):
2106.05 Particular Machine [R-07.2022] (b)… while the application of a judicial exception by or with a particular machine is an important clue, it is not a stand-alone test for eligibility… All claims must be evaluated for eligibility using the two-part test from Alice/Mayo… McRO, Inc. v. Bandai Namco Games… ("[T]here is nothing that requires a method ‘be tied to a machine or transform an article’ to be patentable")… if a claim fails the Alice/Mayo test… then the claim is ineligible even if it passes the M-or-T test. DDR Holdings, LLC v.Hotels.com… ("[I]n Mayo, the Supreme Court emphasized that satisfying the machine-or-transformation test, by itself, is not sufficient to render a claim patent-eligible, as not all transformations or machine implementations infuse an otherwise ineligible claim with an 'inventive concept.'")'
Examiner's response: Applicant's argument is not persuasive, because while the M-or-T test is an important clue, it is not a stand-alone test. A claim must pass the two-part framework from Alice/Mayo for eligibility. (See MPEP 2106.05(b) and Independent claim 1, Step 2B supra). The claim recites the argued circuitry at a high level of generality and as performing generic register functions routinely used in circuit applications. Examiner notes that the circuit limitations are well known to persons of ordinary skill in related areas. (See Independent claim 1, Step 2B supra).
Applicant further argues, (see page 11, last paragraph to page 13, 2nd paragraph):
‘… as explained in the specification, the present claims "are useful in neural network inference and training," as the claims are directed at improvements to softmax function computations.15 As explained, "in applications involving large tensors, traversing all elements of the tensor to find the maximum value can consume a considerable amount of time, and until the maximum of the tensor elements is found, the exponential function calculation will be blocked."16 To solve these and other technical problems, the present specification describes techniques to "significantly reduce the time expended in computing dmax by dividing an input tensor into several groups, converting tensor elements into power-of-two values, determining group-level biases, adjusting the power- of-two values according to the group-level biases, and summing the adjusted values of the groups."17
Further, these improvements are clearly reflected in the claims, as amended. Claim 1, as amended, recites each step of the improvement described above: "transforming in parallel, elements of each group of a plurality of groups of elements of a tensor X into respective power-of-two elements," "determining respective group-level biases for the groups by a comparison circuit," "generating, for each group, respective group-biased elements by adjusting in parallel, using a plurality of adder circuits, the respective power-of-two elements based on the group-level bias of the group," and "accumulating, by an accumulator circuit and an update circuit, the respective group- biased elements into a tensor-level sum…’
As pointed out by Applicant, the application description reads (underline emphasis added):
[0017]… exponential functions of softmax are transformed into 2X form…
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The MPEP reads (underline emphasis added):
‘2106.05(a) Improvements to the Functioning of a Computer or To Any Other Technology or Technical Field [R-07.2022]… if the specification explicitly sets forth an improvement but in a conclusory manner (i.e., a bare assertion of an improvement without the detail necessary to be apparent to a person of ordinary skill in the art), the examiner should not determine the claim improves technology. An indication that the claimed invention provides an improvement can include a discussion in the specification that identifies a technical problem and explains the details of an unconventional technical solution expressed in the claim, or identifies technical improvements realized by the claim over the prior art. For example, in McRO, the court relied on the specification’s explanation of how the particular rules recited in the claim enabled the automation of specific animation tasks that previously could only be performed subjectively by humans, when determining that the claims were directed to improvements in computer animation instead of an abstract idea… the court in Affinity Labs of Tex. v. DirecTV, LLC relied on the specification’s failure to provide details regarding the manner in which the invention accomplished the alleged improvement when holding the claimed methods of delivering broadcast content to cellphones ineligible… the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements… analyze the "improvements" consideration by evaluating the specification and the claims to ensure that a technical explanation of the asserted improvement is present in the specification, and that the claim reflects the asserted improvement'
and '2106.04(d)(1) Evaluating Improvements in the Functioning of a Computer, or an Improvement to Any Other Technology or Technical Field in Step 2A Prong Two [R-10.2019]… first the specification should be evaluated to determine if the disclosure provides sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing an improvement… Second, if the specification sets forth an improvement in technology, the claim must be evaluated to ensure that the claim itself reflects the disclosed improvement. That is, the claim includes the components or steps of the invention that provide the improvement described in the specification. The claim itself does not need to explicitly recite the improvement described in the specification… the "improvements" analysis in Step 2A determines whether the claim pertains to an improvement to the functioning of a computer or to another technology… invention may integrate the judicial exception into a practical application by demonstrating that it improves the relevant existing technology although it may not be an improvement over well-understood, routine, conventional activity… the word "improvements" in the context of this consideration is limited to improvements to the functioning of a computer or any other technology/technical field, whether in Step 2A Prong Two or in Step 2B...'.
Examiner's response: Applicant's argument is not persuasive, because as to the argued improvements ('improvements to softmax function computations… reduce the time expended in computing dmax'), the claims may provide an improved abstract idea – improved or faster computations, but do not provide limitations such that an improvement to the functioning of a computer itself or to any other technology is realized. An improved abstract idea is an abstract idea. An improved abstract idea is a species of the genus abstract idea. (See 2106.04(d)(1) supra).
The specification does not provide sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing/realizing any improvements to the functioning of a computer itself or any other technology or technical field (underline emphasis added). (See MPEP 2106.05(a) or 2106.04(d)(1) supra).
Therefore, the rejections are maintained.
Conclusion
Examiner would like to point out that any reference to specific figures, pages, columns and lines should not be considered limiting in any way, the entire reference is considered to provide disclosure relating to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUAN CARLOS OCHOA whose telephone number is (571)272-2625. The examiner can normally be reached Mondays, Tuesdays, Thursdays, and Fridays 9:30AM -8:00 PM.
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/JUAN C OCHOA/Primary Examiner, Art Unit 2186
1 Electric Power Group, LLC v. Alstom S.A., 119 USPQ2d 1739 Fed. Cir. 2016
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