DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The amended claims overcome the previous 112 rejection.
The applicant argues on page 8 of the response that “[a]s shown in FIGS. 4B-4H of the as-filed specification, the recess 101 and the first shallow trench isolation structure 13A are formed at different locations. However, in Maeda, the alleged ‘recess’ is the location for filling STI 104-I. Maeda does not disclose the recess, and the STI 104-I are located at different locations.”
Maeda discloses that there are multiple STIs 104-I. Thus, Maeda still reads on the claims in that one STI 104-I can correspond to the claimed recess and another can correspond to the claimed first shallow trench isolation structure. See the rejections below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 10, 11, 13-15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda, US 2013/0134520 A1, in view of Ota, US 2002/0047170 A1.
Claim 8: Maeda discloses
a substrate (100) comprising a first region (I) and a second region (II), the first region being formed with a recess (the recess within which 104-I to the left is formed);
a first shallow trench isolation structure (104-I to the right) in the first region and a second shallow trench isolation structure (104-II) in the second region, a height of the first shallow trench isolation structure in a first (vertical) direction being larger than a height of the second shallow trench isolation structure in the first direction (FIG. 13B);
and a first gate oxide layer (130) on the recess and a second gate oxide layer (310) on the second shallow trench isolation structure;
wherein the first region is a high-voltage device region, and the second region is a low-voltage device region ([0073]);
and wherein the recess and the first shallow trench isolation structure are formed at different locations in the first region:
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Claim 8 also recites that “a first top surface of the first shallow trench isolation structure is higher than a second top surface of the first gate oxide layer in the first direction.” Maeda does not disclose this; however, this was known in the art. See e.g. Ota, FIG. 19, which shows STI 15 with a high top surface, higher than the gate oxide 25 surrounding high voltage transistors A1 and low transistors A2. It would have been obvious to have used such high STIs as known to be effective in high voltage/low voltage devices, such as Maeda discloses, that provides a structurally higher isolation.
Claim 10: Maeda discloses
a first gate layer (202-I) on the first gate oxide layer;
and a second gate layer (320, [0136]) on the second gate oxide layer.
Claim 11: a thickness of the first gate oxide layer is greater than a thickness of the second gate oxide layer. “a thickness of the first gate insulating layer 130-I may be greater than that of the second gate insulating layer 130-II.” [0169]. Maeda discloses that the first gate oxide is thicker in some embodiments and illustrates that it is larger in all embodiments, suggesting to those in the art that the first gate oxide is thicker in all embodiments.
Claim 13: Maeda discloses
a third shallow trench isolation structure in the second region adjacent to the second shallow trench isolation structure;
and a channel disposed between the second shallow trench isolation structure and the third shallow trench isolation structure,
wherein the second gate layer is formed on the second shallow trench isolation structure and the third shallow trench isolation structure, and the second gate layer surrounds the channel from three sides of the channel.
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Claim 21: in altering the device of Maeda to have the STIs of Ota, it would have been obvious to have the first shallow trench isolation structure penetrates the first gate oxide layer, as it is thicker, and thus is formed above and below the gate oxide layer.
Claim 22: Ota does not disclose that the first top surface of the first shallow trench isolation structure is coplanar to a third top surface of the first gate layer, although they have similar height. However, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP2144.04(IV). Those in the art would have structured these elements according to ordinary considerations, and the relative height would not appear to be a patentable distinction.
Claim 14: Maeda discloses
a substrate (100) comprising a first region (I) and a second region (II);
a recess on the substrate in the first region (the recess within which 104-I to the left is formed);
a plurality of first shallow trench isolation structures (104-I to the right) in the first region and a plurality of second shallow trench isolation structures (104-II) in the second region, a height of the first shallow trench isolation structure in a first direction being larger than a height of the second shallow trench isolation structure in the first direction (FIG. 13B);
a first gate layer (130) in the first region between adjacent first shallow trench isolation structures;
and a second gate layer in the second region above adjacent second shallow trench isolation structures, wherein the second gate layer surrounds a channel (110-II) from three sides of the channel (FIG. 13B);
wherein the first region is a high-voltage device region, and the second region is a low-voltage device region ([0073]);
and wherein the recess and the first shallow trench isolation structure are formed at different locations in the first region:
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Maeda does not disclose that a first top surface of the first shallow trench isolation structure is coplanar to a second top surface of the first gate layer. See e.g. Ota, FIG. 19, which shows STI 15 with a high top surface, higher than the gate oxide 25 surrounding high voltage transistors A1 and low transistors A2. It would have been obvious to have used such high STIs as known to be effective in high voltage/low voltage devices, such as Maeda discloses, that provides a structurally higher isolation.
Thus it was known for the STI and the gate to extend above the gate dielectric. Ota does not disclose that the first top surface of the first shallow trench isolation structure is coplanar to a third top surface of the first gate layer, although they have similar height. However, changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP2144.04(IV). Those in the art would have structured these elements according to ordinary considerations, and the relative height would not appear to be a patentable distinction.
Claim 15: the channel is a fin-like structure (FIG. 13B).
Claim 16: Maeda discloses:
a first gate oxide layer (130) on the recess between the substrate and the first gate layer;
and a second gate oxide layer (310) between the second gate layer and the channel.
Claim 23: the first top surface of the first shallow trench isolation structure is higher than a third top surface of the first gate oxide layer in the first direction (Ota FIG. 19).
Claim 24: in altering the device of Maeda to have the STIs of Ota, it would have been obvious to have the first shallow trench isolation structure penetrates the first gate oxide layer, as it is thicker, and thus is formed above and below the gate oxide layer.
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda in view of Ota and Fujita, US 2024/0170335. Maeda does not disclose that the substrate further comprises a third region comprising a slicing groove. However, this was well-known in the art. See e.g. Fujita, FIGS. 5A and 5B, slicing grooves 16. It would have been obvious to have had such a groove in Maeda to facilitate singulation of devices formed together on a single wafer, in a third region between two devices on the wafer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and are listed in the attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10-6.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897