DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Non-Final office action is in response to application 17/893,156, Applicant’s response filed 10/09/2025 to Election/Restriction requirement. Claims 1 and 16 are currently withdrawn. No claims are currently amended. Claims 1-16 are currently pending in this application. Election/Restrictions 2. Applicant’s election without traverse of claims 2-15 in the reply filed on 10/09/2025 is acknowledged. Examiner reminds Applicant to consider cancelling all non-elected/withdrawn claims upon response to this office action. Information Disclosure Statement 3. The information disclosure statement (IDS) submitted on 08/22/2022 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 5. Claim(s) 2-15 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tseng et al. (US PG Pub No. 2011/0307233 ). 6. With respect to independent claim 2, Tseng teaches : receiving first data representing a hardware-description language (HDL) description of an electronic circuit ( receiving, as input, user circuit design data at 200 of Fig 3, where the user circuit design data is in HDL form, para 207 ) ; identifying, using the first data, a first description of a first storage element configured to process, during a first time period, an input signal to store data associated with the input signal and to output, during a second time period, an output signal representing the data ( using HDL data, performing component analysis of the processed HDL, and identifying components such as register components which are data storage elements, para 208; see first register latch taking input, outputting signal, Figs 78-79, para 601-605 ) ; determining a memory structure configured to store the data ( see use of latch/register to store data, Figs 80A, 80B, 81A, 81B, para 620-629 ) ; determining a second description of a second storage element configured to store a reference value indicating a location of the data in the computer-memory structure, a topology of the second storage element corresponding to a topology of the first storage element ( see memory components to store data, accessing individual data in specific memory locations , para 217 ) ; determining, using the first data and the second description, a circuit model corresponding to the HDL description and the second storage element ( see description, second storage elements, see use of latch/register to store data, Figs 80A, 80B, 81A, 81B, para 620-629, see second latches/registers to store data, see replacement latch to store data, para 620-629 ) ; storing, using a first portion of the circuit model corresponding to the second storage element, the reference value ( see Figs 75A-B, 76A-B, 77A-B, storing values in latch/register, para 215-220 ) ; and processing, by the memory structure during the second time period, the reference value to output the data ( see storing/outputting data in second time period, see timing tables/graphs; see Figs 75A-B, 76A-B, 77A-B, storing values in latch/register, para 215-220; see description, second storage elements, see use of latch/register to store data, Figs 80A, 80B, 81A, 81B, para 620-629, see second latches/registers to store data, see replacement latch to store data, para 620-629 ) . 7. With respect to independent claim 3, Tseng teaches : receiving first data representing a hardware-description language (HDL) description of a first electronic circuit ( receiving, as input, user circuit design data at 200 of Fig 3, where the user circuit design data is in HDL form, para 207 ) ; identifying in the first data, a first representation of a first group of circuit elements corresponding to a circuit-element transformation technique ( using HDL data, performing component analysis of the processed HDL, and identifying components such as register components which are data storage elements, para 208; see first register latch taking input, outputting signal, Figs 78-79, para 601-605; transforming a circuit design into a more efficient representation; para 245; transforming user’s circuit design into a functionally equivalent design while controlling timing of clock in/out signals, para 604; circuit re-timing, para 604 ) ; determining a second representation of a second group of circuit elements by applying the circuit-element transformation technique to the first group of circuit elements ( see transformation, para 605; see storing/outputting data in second time period, see timing tables/graphs; see Figs 75A-B, 76A-B, 77A-B, storing values in latch/register, para 215-220; see description, second storage elements, see use of latch/register to store data, Figs 80A, 80B, 81A, 81B, para 620-629, see second latches/registers to store data, see replacement latch to store data, para 620-629 ) ; identifying a second electronic circuit determined by replacing the first group of circuit elements in the first data with the second group of circuit elements ( see simulation results, see second latches/registers to store data, see replacement latch to store data, para 620-629 ) ; simulating operation of the second electronic circuit to determine second data representing values of signals in the second electronic circuit ( see transformation, para 605; see storing/outputting data in second time period, see timing tables/graphs; see Figs 75A-B, 76A-B, 77A-B, storing values in latch/register, para 215-220 ) ; determining a first signal corresponding to the first group of circuit elements ( see first register latch taking input, outputting signal, Figs 78-79, para 601-605 ) ; determining a first time period corresponding to a first value of the first signal ( see transformation, para 605; see storing/outputting data in first time period, see timing tables/graphs; see Figs 75A-B, 76A-B, 77A-B, storing values in latch/register, para 215-220; see description, second storage elements, see use of latch/register to store data, Figs 80A, 80B, 81A, 81B, para 620-629, see first latches/registers to store data, see replacement latch to store data, para 620-629 ) ; determining, using the circuit-element transformation technique, at least one second signal corresponding to the second group of circuit elements, wherein the second signal, at a second time period, corresponds to a representation of the first value ( see transformation, para 605; see storing/outputting data in second time period, see timing tables/graphs; see Figs 75A-B, 76A-B, 77A-B, storing values in latch/register, para 215-220; see transformation, para 605; see storing/outputting data in second time period, see timing tables/graphs; see Figs 75A-B, 76A-B, 77A-B, storing values in latch/register, para 215-220; see description, second storage elements, see use of latch/register to store data, Figs 80A, 80B, 81A, 81B, para 620-629, see second latches/registers to store data, see replacement latch to store data, para 620-629 ) ; and determining using at least one value of the at least one second signal during the second time period and the circuit-element transformation technique, the first value ( verifying accuracy of circuit, input signals as test vectors, determining values based on replacement by glitch free circuit latch replacement, Figs 80A, 80B, 81A, 81B, para 620-629, see first latches/registers to store data, see replacement latch to store data, para 620-629 ) . 8. With respect to claim 4, Tseng teaches : The computer-implemented method of claim 3, wherein the circuit-element transformation technique is reversible ( see reverting back to previous values in user design, para 216-218 ) . 9. With respect to claim 5, Tseng teaches : The computer-implemented method of claim 3, wherein the se cond group of circuit elements have an equivalent behavior to the first group of circuit elements ( transforming user’s circuit design into a functionally equivalent design while controlling timing of clock in/out signals, para 604; circuit re-timing, para 604 ) . 10. With respect to claim 6, Tseng teaches : The computer-implemented method of claim 3, wherein the circuit-element transformation technique corresponds to retiming of operation of at least one data-preserving element ( using HDL data, performing component analysis of the processed HDL, and identifying components such as register components which are data storage elements, para 208 ) . 11. With respect to claim 7, Tseng teaches : The computer-implemented method of claim 3, wherein the circuit-element transformation technique corresponds to migration of logic across at least one data-preserving element ( migration/reduction of hardware in simulation performance, para 417; reducing complexity of PCB design, para 541; design is reduced to ASIC form for testing, para 1094 ) . 12. With respect to claim 8, Tseng teaches : The computer-implemented method of claim 7, wherein the at least one data-preserving element comprises: a multiplexer ( see multiplexer, Fig 80B ) ; and a flip-flop including: an input driven by an output of the multiplexer ( see arrangement of D flip flop and multiplexer, input/output driven by flip flop, Fig 80B, para 617-625 ) , and an output connected to an input of the multiplexer ( see output of D flip flop connected to input of MUX, Fig 80B, para 614-625 ) . 13. With respect to claim 9, Tseng teaches : The computer-implemented method of claim 7, wherein the data-preserving element comprises an array ( see array as latches , 228,241, 252, 611-616 ) . 14. With respect to claim 10, Tseng teaches : The computer-implemented method of claim 7, wherein the data-preserving element comprises a queue ( see FIF queue, para 928 ) . 15. With respect to claim 11, Tseng teaches : The computer-implemented method of claim 7, wherein the data-preserving element comprises a ring ( see ring configuration in Fig 80B [compare to Applicant’s Figure 6E] ) . 16. With respect to claim 12, Tseng teaches : The computer-implemented method of claim 3, wherein the circuit-element transformation technique comprises time-domain multiplexing ( see time-domain multiplexing, para 645 ) . 17. With respect to claim 13, Tseng teaches : The computer-implemented method of claim 3, wherein the circuit-element transformation technique comprises storing data values in a storage array and configures a storage element to refer to a value stored in the storage array ( see array as latches for storing values, 228,241, 252, 611-616 ) . 18. With respect to claim 14, Tseng teaches : The computer-implemented method of claim 3, wherein th e circuit-element transformation technique absorbs a storage element into a first-in-first-out (FIFO) component ( see FIFO queue, para 928 ) . 19. With respect to claim 15, Tseng teaches : The computer-implemented method of claim 3, wherein the circuit-element transformation technique absorbs a storage element into a queue ( see FIFO queue, para 928 ) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov . Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUCHIN PARIHAR/ Primary Examiner, Art Unit 2851