Prosecution Insights
Last updated: April 19, 2026
Application No. 17/893,274

SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE SEMICONDUCTOR DEVICES

Non-Final OA §112
Filed
Aug 23, 2022
Examiner
CULBERT, CHRISTOPHER A
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Non-Final)
41%
Grant Probability
Moderate
2-3
OA Rounds
3y 8m
To Grant
46%
With Interview

Examiner Intelligence

Grants 41% of resolved cases
41%
Career Allow Rate
137 granted / 333 resolved
-26.9% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
81 currently pending
Career history
414
Total Applications
across all art units

Statute-Specific Performance

§103
55.8%
+15.8% vs TC avg
§102
20.9%
-19.1% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 333 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office action is in response to Amendments filed 11/7/2025. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-11 and 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claims 1 and 18 each recite that the first extension portion is formed by laterally expanding the plurality of sacrificial layers. This limitation is not enabled as the sacrificial layers are not laterally expanded but, instead, further laterally removed. claims 2-11 and 19-20 depend from claims 1 and 18 and are, therefore, also rejected. Allowable Subject Matter Claims 12-18 are allowed. The following is an examiner’s statement of reasons for allowance: Claim 12 recites a specific method for manufacturing a semiconductor device including forming a mold stack including a plurality of insulating layers and a plurality of sacrificial layers alternately arranged on a substrate; forming a preliminary pad structure by sequentially patterning the mold stack, wherein the preliminary pad structure has a stepped shape and includes a preliminary pad portion that includes a portion of at least one sacrificial layer among the plurality of sacrificial layers, and the preliminary pad portion has a greater thickness than the at least one sacrificial layer in a vertical direction that is perpendicular to an upper surface of the substrate; forming a cell contact hole, which extends in the vertical direction through the preliminary pad portion and through remaining ones of the plurality of sacrificial layers and includes a first extension portion extending in a horizontal direction; forming a sacrificial ring pattern in the first extension portion; forming a sacrificial plug within the cell contact hole; forming a plurality of gate spaces by removing the plurality of sacrificial layers and forming a pad space by removing the preliminary pad portion and the sacrificial ring pattern; forming a dielectric liner on inner walls of the plurality of gate spaces and the pad space; forming a plurality of gate electrodes within the plurality of gate spaces on the dielectric liner and forming a pad portion within the pad space; removing the sacrificial plug to expose a sidewall of the pad portion and removing a portion of the dielectric liner exposed in the cell contact hole; and forming, in the cell contact hole, a cell contact plug contacting the sidewall of the pad portion and extending in the vertical direction. This specific combination of features is neither taught by nor obvious over the prior art of record. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A CULBERT/Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Aug 23, 2022
Application Filed
Aug 20, 2025
Non-Final Rejection — §112
Sep 05, 2025
Interview Requested
Sep 22, 2025
Examiner Interview Summary
Sep 22, 2025
Applicant Interview (Telephonic)
Nov 13, 2025
Response Filed
Mar 01, 2026
Non-Final Rejection — §112
Mar 09, 2026
Interview Requested

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12557465
PHOTOELECTRIC DEVICE
2y 5m to grant Granted Feb 17, 2026
Patent 12532521
METHOD FOR MANUFACTURING SELF-ALIGNED EXCHANGE GATES AND ASSOCIATED SEMICONDUCTING DEVICE
2y 5m to grant Granted Jan 20, 2026
Patent 12520723
ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE SAME
2y 5m to grant Granted Jan 06, 2026
Patent 12512315
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Dec 30, 2025
Patent 12501743
MICRO-LED STRUCTURE AND MICRO-LED CHIP INCLUDING SAME
2y 5m to grant Granted Dec 16, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
41%
Grant Probability
46%
With Interview (+4.4%)
3y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 333 resolved cases by this examiner. Grant probability derived from career allow rate.

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