DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the objection to claim(s) 19, Applicant did not address this objection. Accordingly, the objection to claim(s) 19 is maintained.
RE: the rejection of claim(s) 6 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 6 has been withdrawn.
RE: the rejection of claim(s) 1-20 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but further search and consideration prompted the new grounds of rejection presented herein.
Claim Objections
Claims 2, 19 are objected to because of the following informalities:
Claim 2 includes “wherein the first and second heat sink provide” where it is understood “heat sink” should be corrected to the plural form “heat sinks”. Appropriate correction is required.
Claim 19 is still objected to because of the following informalities: Claim 19 recites “one or more conductive vias conductive via” and this is considered to be a typographical error of “one or more conductive vias.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 includes “a first upper segment”, “a second upper segment”, “a first semiconductor die”, and “a second semiconductor die” and it is unclear if these refer to the same “first upper segment”, “second upper segment”, “first semiconductor die”, and “second semiconductor die” introduced in claim 1. For the purposes of examination, the segments in claim 9 will be interpreted as “a first upper shield segment” and “a second upper shield segment” and the dies will be interpreted as the same elements as in claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 7-8, 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20200168534A1 (“Bonifield”) in view of US 20230070629 A1 (“Lee”), further in view of US20160118188A1 (“Wada”), further in view of US 20050011656 A1 (“Patterson”), further in view of US 2010/0127347 A1 (“Quinn”).
RE: Claim 1, Bonifield discloses A semiconductor package (structure in FIG. 2), comprising:
a barrier (206, 210, 215);
semiconductor dies (102, 106, [0017]) including a first semiconductor die (102) and a second semiconductor die (106); and
a capacitive interface (110, 112 including 211, 212, 209) formed within the barrier and providing a communication path between the semiconductor dies, the capacitive interface having a plurality of capacitive elements (211, 212, 209);
the capacitive elements in the capacitive interface including a first upper segment (211) adjacent to the first semiconductor die, and a second upper segment (212) adjacent to the second semiconductor die, portions of both the first upper segment and the second upper segment exposed on a top surface of the barrier (FIG. 2 shows 211, 212 are exposed on a top surface of 210).
Bonifield does not explicitly disclose:
the barrier (206, 210, 215) is a ceramic barrier;
a ceramic header having two interior cavities separated by the ceramic barrier;
the first semiconductor die and the second semiconductor die are mounted within each of the cavities, respectively;
the plurality of capacitive elements alternate with a plurality of shielding elements.
However, Bonifield discloses layer 215 is a protective overcoat oxide layer, [0026].
In the same field of endeavor, Lee discloses protective layer 200 includes oxide ceramic, [0036]. When the average polarizability of oxide ions (α.sub.O2−) of the oxide ceramic is 2 Å.sup.3 or more, moisture permeation may be suppressed to improve moisture resistance reliability of the entire component, [0036], see FIG. 2.
It would have been obvious to one of ordinary skill in the art to modify protective layer 215 to be made of an oxide ceramic as taught by Lee in order to improve moisture resistance of the device as further taught by Lee.
Further Bonifield discloses layers 206, 210 are dielectric layers, [0024].
In the same field of endeavor, Wada discloses The present invention relates to a multilayer ceramic capacitor and a method for producing the multilayer ceramic capacitor and more particularly to an improvement in the crystal grain morphology of a dielectric ceramic advantageous to a decrease in the size and an increase in the capacitance of a multilayer ceramic capacitor, [0002].
Wada further discloses multilayer ceramic capacitor 1 includes a multilayer body 5, which includes a plurality of stacked dielectric ceramic layers 2 and a plurality of internal electrodes 3 and 4, [0047], see FIG. 1.
Wada further discloses The dielectric ceramic layers 2 are formed of a multilayer body ceramic containing crystal grains and crystal grain boundaries, [0051].
It would have been obvious to one of ordinary skill in the art to modify the dielectric layers 206, 210 to be ceramic dielectric layers as taught by Wada to improve the capacitance of the device as further taught by Wada. As a result, the combination of the ceramic dielectric layers 206, 210, 215 would correspond to the claimed ceramic barrier.
In the same field of endeavor, Patterson discloses an integrated circuit package generally made from a ceramic material, [0056].
Patterson further discloses 716 is a circuit package containing a plurality of circuit die 712, [0089], see FIG. 8.
Patterson further discloses each layer shown in FIG. 8 is hermetic. Ceramic material is used for the first layer 706 and the second layer 708. Thus, no moisture is allowed into the space containing the first plurality of circuit die 712 and the second plurality of circuit die 714. This prevents failure of the circuit die, [0092].
In FIG. 8, the plurality of circuit die 712 are disposed in a recess of the package 716.
In FIG. 8, solder balls 732 connect a substrate 728 on which the plurality of die 712 are mounted to the package 716.
It would have been obvious to one of ordinary skill in the art to provide a ceramic package for containing the plurality of die 102, 104, 106 and their substrates DAP1, DAP2 as taught by Patterson in order to improve moisture resistance of the device as further taught by Patterson.
As a result, the ceramic package would correspond to the claimed ceramic header having two interior cavities separated by the ceramic barrier formed by 206, 210, 215; and the first semiconductor die 102 and the second semiconductor die 106 are mounted within each of the cavities of the ceramic package, respectively.
In the same field of endeavor, Quinn discloses A ground shield 306 includes ground shield conductive curtains 308, 310, that essentially surround the core capacitor portion 304 and shield capacitor portion 302 of the integrated capacitor. The ground shield conductive curtains 308, 310, include poly elements 312, 314 and contacts 316, 318 to P+ regions 320, 322 in the substrate 226, [0046], FIG. 3A. Quinn further teaches forming patterns in the appropriate metal layers and vias through the inter-metal dielectric (“IMD”) layers or inter-layer dielectric (“ILD”), [0024].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the ground shield 306 including shields 302, 308, 310 surrounding capacitive elements 211, 212 of capacitors 110, 112 as taught by Quinn in order to shield these capacitive elements from each other and prevent cross-talk or interference. As a result, the plurality of capacitive elements 211, 212 would alternate with a plurality of shielding elements positioned within portions of dielectric layers 206, 210, 215.
RE: Claim 3, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The semiconductor package of claim 1, wherein the capacitive elements in the capacitive interface comprising:
a central lower segment (Bonifield FIG. 2: 209) extending from the first upper segment and the second upper segment (In FIG. 2, 209 extends from under 211 to under 212).
RE: Claim 7, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The semiconductor package of claim 1, wherein capacitance values of each capacitive element are approximately the same (Bonifield teaches capacitors 110, 112 may be symmetric, meaning that the symmetric capacitors may generate substantially equal capacitance, [0017]).
RE: Claim 8, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The semiconductor package of claim 1, wherein capacitance values of each capacitive element is different (Bonifield teaches capacitors 110, 112 may be symmetric, meaning that the symmetric capacitors may generate substantially equal capacitance (e.g., capacitance within 10% range of each other), [0017]; Accordingly Bonifield teaches the capacitances may be different as they may be within a range of each other).
RE: Claim 13, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The semiconductor package of claim 1, wherein the shielding elements in the capacitive interface provide ground shielding between adjacent ones of the capacitive elements (As modified by Quinn, Quinn’s 308 and 310 are ground shield conductive curtains providing ground shielding between adjacent ones of 211, 212, see [0046] in Quinn).
RE: Claim 14, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The semiconductor package of claim 1, wherein the shielding elements in the capacitive interface comprise:
a first lower segment (As modified, Quinn’s uppermost 314 in 310 in FIG. 3A of Quinn); and
a second lower segment spaced apart from the first lower segment (As modified, Quinn’s lowermost 314 of 310 in FIG. 3A of Quinn), wherein a distance between the first lower segment and the second lower segment provides electrical isolation between a first semiconductor die and a second semiconductor die (Quinn teaches The shield capacitor portion 254 surrounds the core capacitor portion 252 and isolates the core capacitor portion from electronic noise similarly to how an outer conductive sheath of a cable isolates the inner wires from electronic noise, [0043]; Accordingly, the distance between the uppermost and lowermost 314 would be occupied by additional 314 providing electrical isolation between 102 and 106).
Claim 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonifield in view of Lee, further in view of Wada, further in view of Patterson, further in view of Quinn as applied to claim 1, and further in view of US 7259460 B1 (“Bayan”).
RE: Claim 2, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The semiconductor package of claim 1, further comprising:
a lid structure coupled to a top surface of the ceramic header (Patterson discloses a radiation shielding lid 702, [0089] attached to the ceramic package 716; It would have been obvious to include a radiation shielding lid attached to the ceramic package as taught by Patterson in order to provide radiation shielding to the dies 102, 104, 106), the lid structure and ceramic header forming a portion of a package enclosing the semiconductor dies (As modified, the ceramic package and lid would form a package enclosing the dies 102, 106);
a first heat sink (In Bonifield FIG. 2: DAP1; DAP1 and DAP2 are metal plates, [0027]; DAP is a die attach pad, [0002]) coupled to a bottom surface of the ceramic header and providing a mounting surface for a first semiconductor die (As modified, DAP1 is coupled to the bottom surface of 102 and would be coupled to the bottom surface of the ceramic package; In FIG. 2 Bonifield DAP1 provides a mounting surface for 102); and
a second heat sink (DAP2) coupled to the bottom surface of the ceramic header and providing a mounting surface for a second semiconductor die (As modified, DAP2 is coupled to the bottom surface of 106 and would be coupled to the bottom surface of the ceramic package; In FIG. 2 Bonifield DAP2 provides a mounting surface for 106).
Bonifield in view of Lee, Wada, Patterson, Quinn does not explicitly disclose:
wherein the first and second heat sink provide independent ground planes for the first and second semiconductor dies.
However, in the same field of endeavor, Bayan discloses it is desirable to make a die attach pad a ground (or power) plane. In the illustrated embodiment, the die support structure 109 may be configured as a ground (or power) plane simply by downbonding to the pads 117 and/or the support bars 118, Col. 5, lines 7-13. Bayan further discloses the die support structure may be divided into two or more components. Such an approach can be particularly useful in situations where it is desirable to provide multiple independent ground/power planes, Col. 5, lines 33-35.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make each die attach pads DAP1, DAP2 independent ground planes as taught by Bayan in order to provide closer ground potentials to dies 102, 106 which do not interfere with each other, and to provide some electromagnetic shielding to dies 102, 106.
Claims 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonifield in view of Lee, further in view of Wada, further in view of Patterson, further in view of Quinn as applied to claim 3, and further in view of US20020085334A1 (“Figueroa”).
RE: Claim 4, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The semiconductor package of claim 3, wherein the central lower segment extends under but is not attached to the first upper segment (In Bonifield FIG. 2, 209 extends under 211 but is not conductively attached to 211).
However, Bonifield in view of Lee, Wada, Patterson, Quinn does not explicitly disclose the central lower segment is conductively attached to the second upper segment.
In the same field of endeavor, Figueroa discloses Some of the vias 330, 332, 334 associated with a tier make contact with every other layer of the tier, [0030].
In FIG. 3, Figueroa shows a via 332 in contact with a metal layer in 316
In FIG. 3, via 334 is not in contact with the same metal layer in 316.
Figueroa discloses Each layer 311-325 of patterned conductive material is separated by a dielectric layer, and each set of adjacent layers and intermediate dielectric layers form a parallel plate capacitor, [0029].
Figueroa further discloses via is filled with conductive material, [0030].
Figueroa further discloses embodiments of the present invention provide a multiple tier capacitor, which can be used to provide additional charge, decoupling capacitance, [0026].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce at least one additional conductive layer between 212 and 209 and to conductively attach 212 and 209 with a conductive via as taught by Figueroa in order to provide additional decoupling capacitance.
RE: Claim 5, Bonifield in view of Lee, Wada, Patterson, Quinn, Figueroa discloses The semiconductor package of claim 4, wherein the central lower segment is conductively attached to the second upper segment by a conductive via through the ceramic barrier (As modified, the conductive via would extend between 209 and 212 and therefore extend through 210).
RE: Claim 6, Bonifield in view of Lee, Wada, Patterson, Quinn, Figueroa discloses The semiconductor package of claim 4, wherein a capacitance value of the capacitive elements is determined by an amount of overlap between the first upper segment and the central lower segment (US 20080174434 A1 (“Strauser”) discloses portions of the elements 22 and 24 overlap 26, thereby forming a capacitor. As is known to those skilled in the art, the amount of overlap 26 determines the capacitance, [0046]; Accordingly, the amount of overlap between 211 and 209 would determine a capacitance value of 211, 209).
Claims 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonifield in view of Lee, further in view of Wada, further in view of Patterson, further in view of Quinn as applied to claim 1, and further in view of US 7445968 B2 (“Harrison”).
RE: Claim 9, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The semiconductor package of claim 1, wherein the shielding elements in the capacitive interface comprise:
a first upper segment (As modified, Quinn’s left ground curtain 310 would include an uppermost 314 as shown in FIG. 3A of Quinn) adjacent to a first semiconductor die (the term “adjacent” is not defined in the instant specification; the term “adjacent” is defined as “not distant”, definition 1b by Merriam-Webster; accordingly, as the Quinn’s shield is around the capacitive elements 211, 212, Quinn’s shield elements would be adjacent to Bonifield’s 102, 106);
a second upper segment (As modified, Quinn’s right ground curtain 308 would include an uppermost 312 as shown in FIG. 3A of Quinn) adjacent to a second semiconductor die;
a first lower segment (As modified, Quinn’s left ground curtain 310 would include a lower 314 positioned below and conductively attached to the uppermost 314 as shown in FIG. 3A of Quinn) positioned below and conductively attached to the first upper segment; and
a second lower segment (As modified, Quinn’s right ground curtain 308 would include a lower 312 positioned below and conductively attached to the uppermost 312 as shown in FIG. 3A of Quinn) positioned below and conductively attached to the second upper segment, wherein the first lower segment and the second lower segment extend toward each other but do not touch (As modified, Quinn’s lower 314 and lower 312 extend toward each other but do not touch).
Bonifield in view of Lee, Wada, Patterson, Quinn does not explicitly disclose:
the first lower segment conductively attached to a first heat sink;
the second lower segment conductively attached to a second heat sink.
In the same field of endeavor, Patterson discloses the second base acts as the principle heat sink and can be attached to a system heat sink. This allows for heat to dissipate from the first plurality of circuit die 816 and the second plurality of circuit die 818, [0096].
Accordingly it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first heat sink and a second heat sink as taught by Patterson in order to dissipate heat from 102, 104.
In a similar field of endeavor, Harrison discloses multiple ground vias 180 are used for establishing a ground path that can be used for grounding the semiconductor dies 120,130, for grounding the metallization layer to aid in electromagnetic shielding, and/or as a path to a thermal heat sink, for example heat sink 175 coupled to via 180, which in turn is coupled to metallization layer 150, Col. 3, lines 23-28, see FIG. 1.
In FIG. 1, Harrison shows the dies 120, 130 and the substrate 110 mounted on the heat sink.
FIG. 1 shows the multiple vias 180 extending through a substrate 110 which Harrison discloses is ceramic, Col. 3, lines 29-35.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to conductively attach Quinn’s lower grounded 314 to the first heat sink by a first ground via in the ceramic barrier 206, 210, 215 as taught by Harrison in order to dissipate heat from Quinn’s ground shield conductive curtain 310.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to conductively attach Quinn’s lower grounded 312 to the second heat sink by a second ground via in the ceramic barrier 206, 210, 215 as taught by Harrison in order in order to dissipate heat from Quinn’s ground shield conductive curtain 308.
RE: Claim 10, Bonifield in view of Lee, Wada, Patterson, Quinn, Harrison discloses The semiconductor package of claim 9, wherein an end of the first lower segment is adjacent an edge of the first heat sink (Harrison shows the layer 150 connected to the heat sink 175 by the via 180 is not distant from the heat sink; Accordingly, as modified, an end of Quinn’s lower 314 would be adjacent to an edge of the first heat sink), and wherein an end of the second lower segment is adjacent an edge of the second heat sink (Harrison shows the layer 150 connected to the heat sink 175 by the via 180 is not distant from the heat sink; Accordingly, as modified, an end of Quinn’s lower 312 would be adjacent to an edge of the second heat sink).
RE: Claim 11, Bonifield in view of Lee, Wada, Patterson, Quinn, Harrison discloses semiconductor package of claim 9, wherein the first lower segment is conductively attached to the first upper segment and to the first heat sink by conductive vias through the ceramic barrier (As modified, a lower 314 would be conductively attached to the uppermost 314 by at least one via 314 as shown in FIG. 3A of Quinn, and would be conductively attached to the first heat sink by the first ground via, and these vias would be positioned in dielectric layers 206, 210, 215 as discussed above for claims 1 and 9).
RE: Claim 12, Bonifield in view of Lee, Wada, Patterson, Quinn, Harrison discloses The semiconductor package of claim 11, wherein the second lower segment is conductively attached to the second upper segment and to the second heat sink by conductive vias through the ceramic barrier (As modified, a lower 312 would be conductively attached to the uppermost 312 by at least one via 312 as shown in FIG. 3A of Quinn, and would be conductively attached to the second heat sink by the second ground via, and these vias would be positioned in dielectric layers 206, 210, 215 as discussed above for claims 1 and 9).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonifield in view of Lee, further in view of Wada, further in view of Patterson, further in view of Quinn.
RE: Claim 15, Bonifield discloses A system, comprising:
a barrier (206, 210, 215);
a first heat sink (DAP1; DAP1 is a metal plate, [0027]);
a first integrated circuit (IC) die (102) mounted on the first heat sink;
a second IC die (106); and
a capacitive interface (110, 112 including 211, 212, 209) in the barrier between the first IC die and the second IC die, the capacitive interface having a plurality of capacitive elements (211, 212, 209).
Bonifield does not explicitly disclose:
the barrier is ceramic;
a ceramic header having a first open space separated from a second open space by the ceramic barrier;
the first heat sink attached to a bottom of the ceramic header below the first open space;
a second heat sink attached to a bottom of the ceramic header below the second open space;
the second IC die mounted on the second heat sink;
the plurality of capacitive elements alternate with a plurality of shielding elements;
wherein the ceramic barrier is mounted on portions of the first heat sink and the second heat sink.
However, Bonifield discloses layer 215 is a protective overcoat oxide layer, [0026].
In the same field of endeavor, Lee discloses protective layer 200 includes oxide ceramic, [0036]. When the average polarizability of oxide ions (α.sub.O2−) of the oxide ceramic is 2 Å.sup.3 or more, moisture permeation may be suppressed to improve moisture resistance reliability of the entire component, [0036], see FIG. 2.
It would have been obvious to one of ordinary skill in the art to modify protective layer 215 to be made of an oxide ceramic as taught by Lee in order to improve moisture resistance of the device as further taught by Lee.
Further Bonifield discloses layers 206, 210 are dielectric layers, [0024].
In the same field of endeavor, Wada discloses The present invention relates to a multilayer ceramic capacitor and a method for producing the multilayer ceramic capacitor and more particularly to an improvement in the crystal grain morphology of a dielectric ceramic advantageous to a decrease in the size and an increase in the capacitance of a multilayer ceramic capacitor, [0002].
Wada further discloses multilayer ceramic capacitor 1 includes a multilayer body 5, which includes a plurality of stacked dielectric ceramic layers 2 and a plurality of internal electrodes 3 and 4, [0047], see FIG. 1.
Wada further discloses The dielectric ceramic layers 2 are formed of a multilayer body ceramic containing crystal grains and crystal grain boundaries, [0051].
It would have been obvious to one of ordinary skill in the art to modify the dielectric layers 206, 210 to be ceramic dielectric layers as taught by Wada to improve the capacitance of the device as further taught by Wada. As a result, the combination of the ceramic dielectric layers 206, 210, 215 would correspond to the claimed ceramic barrier.
In the same field of endeavor, Patterson discloses an integrated circuit package generally made from a ceramic material, [0056].
Patterson further discloses 822 is a circuit package containing a plurality of circuit die 818, [0094], see FIG. 9.
Patterson further discloses the first base 808 and the second base 810 can also be interconnected through the thermal layer connectors 836. In this embodiment, the second base acts as the principle heat sink and can be attached to a system heat sink, [0096].
Patterson further discloses attaching circuit die 416 to a radiation shielding base 408, [0081].
In FIG. 9, the plurality of circuit die 818 are disposed in a space defined by the package 822.
In FIG. 8, a substrate 812 on which die 818 are mounted are in the package 822.
It would have been obvious to one of ordinary skill in the art to provide a ceramic package for containing the plurality of die 102, 104, 106 and their substrates DAP1, DAP2 as taught by Patterson in order to provide heat sinks and improve heat dissipation from the die 102, 104, 106.
As a result:
the ceramic package (Patterson’s 822 in FIG. 9) would correspond to the claimed ceramic header having a first open space separated from a second open space by the ceramic barrier formed by Bonifield’s 206, 210, 215;
the first heat sink (Bonifield’s DAP1) would be attached to a bottom of the ceramic header below the first open space (In Bonifield, 102 is attached to DAP1, [0029] and therefore DAP1 would be attached to the ceramic package as Patterson discloses substrates are attached to packages, [0070], [0049]);
the second heat sink attached to a bottom of the ceramic header below the second open space (Patterson’s base 810 functions as a heat sink, [0096]; Patterson’s base 810 would be attached to Patterson’s ceramic package 822 as shown in Patterson FIG. 9 and would be below both open spaces in the package);
the second IC die mounted on the second heat sink (Bonifield’s 106 would be mounted on Patterson’s base 810);
wherein the ceramic barrier is mounted on portions of the first heat sink and the second heat sink (206, 210, 215 would be mounted on portions of Bonifield’s DAP1 and Patterson’s base 810).
In the same field of endeavor, Quinn discloses A ground shield 306 includes ground shield conductive curtains 308, 310, that essentially surround the core capacitor portion 304 and shield capacitor portion 302 of the integrated capacitor. The ground shield conductive curtains 308, 310, include poly elements 312, 314 and contacts 316, 318 to P+ regions 320, 322 in the substrate 226, [0046], FIG. 3A. Quinn further teaches forming patterns in the appropriate metal layers and vias through the inter-metal dielectric (“IMD”) layers or inter-layer dielectric (“ILD”), [0024].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the ground shield 306 including shields 302, 308, 310 surrounding capacitive elements 211, 212 of capacitors 110, 112 as taught by Quinn in order to shield these capacitive elements from each other and prevent cross-talk or interference. As a result, the plurality of capacitive elements 211, 212 would alternate with a plurality of shielding elements positioned within portions of dielectric layers 206, 210, 215.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonifield in view of Lee, further in view of Wada, further in view of Patterson, further in view of Quinn as applied to claim 15, and further in view of US 20170055341 A1 (“Ma”).
RE: Claim 16, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The system of claim 15, further comprising:
a first connection (In Bonifield FIG. 2: 207) coupling the first IC die to first ends of the capacitive elements (In Bonifield FIG. 2, 207 couples 102 to first ends of 211, 209);
a second connection (208) coupling the second IC die to second ends of the capacitive elements (In Bonifield FIG. 2, 208 couples 106 to second ends of 212, 209); and
a lid structure (Patterson discloses lid structure 808 in FIG. 9 for package 822; Accordingly, it would have been obvious to provide a lid 808 as taught by Patterson in order to better protect Bonifield’s die 102, 104, 106) coupled to a top surface of the ceramic header, the lid structure and ceramic header forming a portion of a package enclosing the IC dies (As modified, Patterson’s lid 808 and ceramic package 822 form at least a portion of a package enclosing die 102, 106).
Bonifield in view of Lee, Wada, Patterson, Quinn does not explicitly disclose:
the first connection is a first set of bond wires;
the second connection is a second set of bond wires.
However, Bonifield discloses 207, 208 are inter-die connections, [0020]-[0023].
In the same field of endeavor, Ma discloses The electronic elements of the power device 1 are connected with each other through the bond-wires 7. The die 6 and at least one capacitor 8 are directly connected to the printed circuit board 2 through the bond-wires 7, [0054].
FIG. 4 of Ma shows the die 6 and the capacitor 8 are connected by multiple bond wires 7.
Accordingly, it would have been obvious to one of ordinary skill in the art to modify the inter-die connection 207 between the die 102 and the capacitor 110 to include multiple bond wires connecting the die 102 to the capacitor 110 as taught by Ma in order to reduce the resistance of the connection between the die 102 and capacitor 110 by using multiple wires.
It would have been further obvious to one of ordinary skill in the art to modify the inter-die connection 207 between the die 106 and the capacitor 112 to include multiple bond wires connecting the die 106 to the capacitor 112 as taught by Ma in order to reduce the resistance of the connection between the die 106 and capacitor 112 by using multiple wires.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonifield in view of Lee, further in view of Wada, further in view of Patterson, further in view of Quinn as applied to claim 15, and further in view of Figueroa.
RE: Claim 17, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The system of claim 15, wherein the capacitive elements comprise:
a first upper segment (Bonifield FIG. 2: 211) adjacent to the first IC die;
a second upper segment (Bonifield’s 212) adjacent to the second IC die; and
a central lower segment (Bonifield’s 209) extending from the first upper segment to the second upper segment,
wherein the central lower segment extends under but is not attached to the first upper segment (In Bonifield FIG. 2, 209 extends under but is not conductively attached to 211).
Bonifield in view of Lee, Wada, Patterson, Quinn does not explicitly disclose the central lower segment is conductively attached to the second upper segment by a conductive via through the ceramic barrier.
In the same field of endeavor, Figueroa discloses Some of the vias 330, 332, 334 associated with a tier make contact with every other layer of the tier, [0030].
In FIG. 3, Figueroa shows a via 332 in contact with a metal layer in 316
In FIG. 3, via 334 is not in contact with the same metal layer in 316.
Figueroa discloses Each layer 311-325 of patterned conductive material is separated by a dielectric layer, and each set of adjacent layers and intermediate dielectric layers form a parallel plate capacitor, [0029].
Figueroa further discloses via is filled with conductive material, [0030].
Figueroa further discloses embodiments of the present invention provide a multiple tier capacitor, which can be used to provide additional charge, decoupling capacitance, [0026].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce at least one additional conductive layer between 212 and 209 and to conductively attach 212 and 209 with a conductive via as taught by Figueroa in order to provide additional decoupling capacitance.
RE: Claim 18, Bonifield in view of Lee, Wada, Patterson, Quinn, Figueroa discloses The system of claim 17, wherein a capacitance value of the capacitive elements is determined by an amount of overlap between the first upper segment and the lower central segment (US 20080174434 A1 (“Strauser”) discloses portions of the elements 22 and 24 overlap 26, thereby forming a capacitor. As is known to those skilled in the art, the amount of overlap 26 determines the capacitance, [0046]; Accordingly, the amount of overlap between 211 and 209 would determine a capacitance value of 211, 209).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bonifield in view of Lee, further in view of Wada, further in view of Patterson, further in view of Quinn as applied to claim 15, and further in view of Harrison.
RE: Claim 19, Bonifield in view of Lee, Wada, Patterson, Quinn discloses The system of claim 15, wherein the shielding elements comprise:
a first upper segment (As modified, Quinn’s left ground curtain 310 would include an uppermost 314 as shown in FIG. 3A of Quinn) adjacent to a first semiconductor die (the term “adjacent” is not defined in the instant specification; the term “adjacent” is defined as “not distant”, definition 1b by Merriam-Webster; accordingly, as the Quinn’s shield is around the capacitive elements 211, 212, Quinn’s shield elements would be adjacent to Bonifield’s 102, 106);
a second upper segment (As modified, Quinn’s right ground curtain 308 would include an uppermost 312 as shown in FIG. 3A of Quinn) adjacent to a second semiconductor die;
a first lower segment (As modified, Quinn’s left ground curtain 310 would include a lower 314 positioned below and conductively attached to the uppermost 314 by multiple 314 as shown in FIG. 3A of Quinn) positioned below and conductively attached to the first upper segment by one or more conductive vias through the ceramic barrier; and
a second lower segment (As modified, Quinn’s right ground curtain 308 would include a lower 312 positioned below and conductively attached to the uppermost 312 by multiple 312 as shown in FIG. 3A of Quinn) positioned below and conductively attached to the second upper segment, wherein the first lower segment and the second lower segment extend toward each other but do not touch (As modified, Quinn’s lower 314 and lower 312 extend toward each other but do not touch).
Bonifield in view of Lee, Wada, Patterson, Quinn does not explicitly disclose:
the first lower segment conductively attached to the first heat sink;
the second lower segment conductively attached to the second heat sink by one or more conductive vias through the ceramic barrier.
In a similar field of endeavor, Harrison discloses multiple ground vias 180 are used for establishing a ground path that can be used for grounding the semiconductor dies 120,130, for grounding the metallization layer to aid in electromagnetic shielding, and/or as a path to a thermal heat sink, for example heat sink 175 coupled to via 180, which in turn is coupled to metallization layer 150, Col. 3, lines 23-28, see FIG. 1.
In FIG. 1, Harrison shows the dies 120, 130 and the substrate 110 mounted on the heat sink.
FIG. 1 shows the multiple vias 180 extending through a substrate 110 which Harrison discloses is ceramic, Col. 3, lines 29-35.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to conductively attach Quinn’s lower grounded 314 to the Bonifield’s heat sink DAP1 or Patterson’s heat sink 810 by a first ground via in the ceramic barrier 206, 210, 215 as taught by Harrison in order to dissipate heat from Quinn’s ground shield conductive curtain 310. As modified, DAP1 is mounted on and thermal conductively attached to Patterson’s 810.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to conductively attach Quinn’s lower grounded 312 to Patterson’s heat sink 810 by a second ground via in the ceramic barrier 206, 210, 215 as taught by Harrison in order in order to dissipate heat from Quinn’s ground shield conductive curtain 308.
RE: Claim 20, Bonifield in view of Lee, Wada, Patterson, Quinn, Harrison discloses The system of claim 19, wherein an end of the first lower segment is adjacent an edge of the first heat sink (As modified, the end of 211 is adjacent to or not distant from an edge of DAP1), and wherein an end of the second lower segment is adjacent an edge of the second heat sink (As modified, the end of 212 would be adjacent to or not distant from an edge of Patterson’s base 810), and wherein the shielding elements in the capacitive interface provide ground shielding between adjacent ones of the capacitive elements (As modified, Quinn’s shielding elements provide ground shielding between Bonifield’s 211, 212).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899