DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 15, 2026, has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed April 15, 2026. Claims 14 and 27 are amended. The Examiner notes that claims 14-23 and 27-30 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-15, 17-19, 21, and 27-30 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuzumi (US 2022/0199641 A1) in view of Hu (US 2020/0258898 A1).
With respect to claim 14, Fukuzumi teaches in Fig. 1P:
A memory array comprising strings (strings 160) of memory cells (memory cells 162) comprising:
a stack (stack structure 101) comprising vertically-alternating insulative tiers (insulative structures 104) and conductive tiers (conductive structures 142), strings of memory cells comprising lower channel-material strings (channel material 114) that extend through the insulative tiers (104) and the conductive tiers (142);
a memory structure laterally adjacent each of the lower channel- material strings, the memory structure comprising a charge blocking region (dielectric blocking material 120), a storage material (memory material 118) and a charge passage material (tunnel dielectric material 116),
vertical transistor strings (upper pillar structures 137) each comprising multiple select-gate transistors ([0069] “The additional conductive structures 145 of the other stack structure 105 may serve as select gate structures, such as select gate drain (SGD) structures”) comprising upper channel-material strings (channel material 130) directly above the stack (101);
conductive masses (conductive material 122) that are individually vertically-between and directly electrically couple together individual of the upper channel-material strings (130) to individual of the lower channel-material strings (114),
the conductive masses comprising at least one of conductively-doped semiconductive material or conductive metal material ([0041] “In some embodiments, the conductive material 122 comprises doped polysilicon”),
and a gate insulator (first liner material 128) radially outward of the upper channel-material strings (130), the gate insulator (128) having laterally-outermost surfaces (right and left surfaces in cross section) and lowest surfaces (bottom surface) in a vertical cross-section, the upper channel-material strings (130) extending to be directly under and directly against the lowest surfaces of the gate insulator in the vertical cross-section and extending laterally to the laterally-outermost surfaces of the gate insulator in the vertical cross-section (see Fig. 1P) where directly under and directly against the lowest surfaces of the gate insulator, the gate insulator being absent from the stack below the conductive masses (128 does not extend to stack 101).
Fukuzumi fails to teach:
and comprising a planar upper surface extending entirely across the charge blocking region, the storage material and the charge passage material;
the conductive masses entirely covering the planar upper surface of the memory structure and having lateral edges coextensive with lateral edges of the planar upper surface of the memory structure;
Hu teaches:
and comprising a planar upper surface (upper surface of lower storage layer 112 and lower channel portion 114 in lower portion) extending entirely across the charge blocking region, the storage material and the charge passage material ([0041] “the storage layer 112 may be formed of a composite layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer (i.e., an ONO layer stack)”);
the conductive masses (conductive plug 120) entirely covering the planar upper surface of the memory structure and having lateral edges coextensive with lateral edges of the planar upper surface of the memory structure (see Fig. 1, conductive plug is coextensive with the edges of 112);
Fukuzumi discloses the claimed invention except for the conductive masses covering the planar upper surface of the memory structure with edges coextensive with the memory structure. It would be obvious to modify Fukuzumi by Hu under the rationale “Use of Known Technique To Improve Similar Devices.” The Graham factual inquiries of this rational are:
(1) a finding that the prior art contained a “base” device (method, or product) upon which the claimed invention can be seen as an “improvement;”
(2) a finding that the prior art contained a “comparable” device (method, or product that is not the same as the base device) that has been improved in the same way as the claimed invention;
(3) a finding that one of ordinary skill in the art could have applied the known “improvement” technique in the same way to the “base” device (method, or product) and the results would have been predictable to one of ordinary skill in the art; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Fukuzumi features a base device that is similar to the claimed invention. Hu teaches a comparable device that it is known to have a conductive mass that completely covers the planar upper surface of a memory structure. The ordinary artisan would understand that the device of Fukuzumi could be modified to use a different etching process such as the process of Hu such that the conductive layer covers a planar surface of the memory structure with a predictable result of forming a connection between an upper and lower memory string. The Examiner notes that although Fukuzumi teaches benefits to the rounded portions of the conductive structure in [0040], however, Fukuzumi also teaches in [0042] that “In other embodiments, the upper portions of the conductive material 122 comprises sharp corners.” The Examiner determined based on this teaching that Fukuzumi does not teach away from the modification due to the teaching of alternative embodiments.
With respect to claim 15, Fukuzumi further teaches:
wherein the at least one is only one of the conductively-doped semiconductive material and the conductive metal material. ([0041] “the conductive material 122 comprises doped polysilicon. In some embodiments, the conductive material 122 is doped with one or more n-type dopants”)
With respect to claim 17, Fukuzumi further teaches:
wherein the at least one comprises the conductively-doped semiconductive material. ([0041] “the conductive material 122 comprises doped polysilicon. In some embodiments, the conductive material 122 is doped with one or more n-type dopants”)
With respect to claim 18, Fukuzumi further teaches:
wherein the conductively-doped semiconductive material comprises conductively n-type doped semiconductive material. ([0041] “the conductive material 122 comprises doped polysilicon. In some embodiments, the conductive material 122 is doped with one or more n-type dopants”)
With respect to claim 19, Fukuzumi further teaches:
wherein the conductively-doped semiconductive material comprises conductively n-type doped polysilicon. ([0041] “the conductive material 122 comprises doped polysilicon. In some embodiments, the conductive material 122 is doped with one or more n-type dopants”)
With respect to claim 21, Fukuzumi further teaches:
wherein the individual conductive masses (122) comprise an uppermost surface that is below a vertically-lowest gate of the select-gate transistors (transistors of stack 105), the individual upper channel-material strings (130) extending down into one of the individual conductive masses (122) to have a bottom therein that is below the uppermost surface of the one individual conductive mass (see Fig. 1P).
With respect to claim 27, Fukuzumi teaches in Fig. 1P:
A memory array comprising strings (strings 160) of memory cells (memory cells 162) comprising:
a stack (stack structure 101) comprising vertically-alternating insulative tiers (insulative structures 104) and conductive tiers (conductive structures 142), strings of memory cells comprising lower channel-material strings (channel material 114) that extend through the insulative tiers (104) and the conductive tiers (142);
a memory structure laterally adjacent each of the lower channel- material strings, the memory structure comprising a charge blocking region (dielectric blocking material 120), a storage material (memory material 118) and a charge passage material (tunnel dielectric material 116),
vertical transistor strings (upper pillar structures 137) each comprising multiple select-gate transistors ([0069] “The additional conductive structures 145 of the other stack structure 105 may serve as select gate structures, such as select gate drain (SGD) structures”) comprising upper channel-material strings (channel material 130) directly above the stack (101);
conductive masses (conductive material 122) that are individually vertically-between and directly electrically couple together individual of the upper channel-material strings (130) to individual of the lower channel-material strings (114),
the conductive masses comprising at least one of conductively-doped semiconductive material or conductive metal material ([0041] “In some embodiments, the conductive material 122 comprises doped polysilicon”),
and a gate insulator (first liner material 128) radially outward of the upper channel-material strings (130), the gate insulator (128) having laterally-outermost surfaces (right and left surfaces in cross section) and lowest surfaces (bottom surface) in a vertical cross-section, the upper channel-material strings (130) extending to be directly under and directly against the lowest surfaces of the gate insulator
Fukuzumi fails to teach:
and comprising a planar upper surface extending across an entire width of the memory structure
the conductive masses having a width equivalent to a width of the planar upper surface
Hu teaches:
and comprising a planar upper surface (upper surface of lower storage layer 112 and lower channel portion 114 in lower portion) extending across an entire width of the memory structure (112 and 114)
([0041] “the storage layer 112 may be formed of a composite layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer (i.e., an ONO layer stack)”);
the conductive masses (conductive plug 120) entirely covering the planar upper surface of the memory structure and having lateral edges coextensive with lateral edges of the planar upper surface of the memory structure (see Fig. 1, conductive plug is coextensive with the edges of 112);
Fukuzumi discloses the claimed invention except for the conductive masses covering the planar upper surface of the memory structure with edges extending along the entire width of the structure. It would be obvious to modify Fukuzumi by Hu under the rationale “Use of Known Technique To Improve Similar Devices.” The Graham factual inquiries of this rational are:
(1) a finding that the prior art contained a “base” device (method, or product) upon which the claimed invention can be seen as an “improvement;”
(2) a finding that the prior art contained a “comparable” device (method, or product that is not the same as the base device) that has been improved in the same way as the claimed invention;
(3) a finding that one of ordinary skill in the art could have applied the known “improvement” technique in the same way to the “base” device (method, or product) and the results would have been predictable to one of ordinary skill in the art; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Fukuzumi features a base device that is similar to the claimed invention. Hu teaches a comparable device that it is known to have a conductive mass that completely covers the planar upper surface of a memory structure. The ordinary artisan would understand that the device of Fukuzumi could be modified to use a different etching process such as the process of Hu such that the conductive layer covers a planar surface of the memory structure with a predictable result of forming a connection between an upper and lower memory string.. The Examiner notes that although Fukuzumi teaches benefits to the rounded portions of the conductive structure in [0040], however, Fukuzumi also teaches in [0042] that “In other embodiments, the upper portions of the conductive material 122 comprises sharp corners.” The Examiner determined based on this teaching that Fukuzumi does not teach away from the modification due to the teaching of alternative embodiments.
With respect to claim 28, Fukuzumi further teaches:
wherein the conductive masses (122) individually have an arcuate bottom (see Fig. 1P).
With respect to claim 29, Fukuzumi further teaches:
wherein the conductive masses (122) individually extend to below individual tops of individual of the lower channel-material strings (114).
With respect to claim 30, Fukuzumi further teaches:
wherein the upper channel-material strings (130) are laterally narrower than the lower channel-material strings (114), the upper channel-material strings individually being radially offset from radial centers of the individual conductive masses and individual of the lower channel-material strings (string on the left has an upper string offset from the center).
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuzumi (US 2022/0199641 A1) in view of Hu (US 2020/0258898 A1) as applied to claims 14 above in view of Sharma (US 2019/0311756 A1).
With respect to claim 16, Fukuzumi/Hu teaches all limitations of independent claim 14 upon which claim 16 depends. Fukuzumi/Hu fails to teach:
wherein the at least one is both of the conductively-doped semiconductive material and the conductive metal material.
Sharma teaches in para. 59:
“The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).”
A person of ordinary skill in the art would have been able to make a simple substitute the material combination of Sharma into the device of Fukuzumi with predictable results.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sharma into the device of Fukuzumi to make the conductive material of both doped-semiconductive material and a metal material. The ordinary artisan would have been motivated to modify Fukuzumi in the manner set forth above for the purpose of forming a conductive material in a semiconductor device and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 20, Fukuzumi/Hu teaches all limitations of independent claim 14 upon which claim 20 depends. Fukuzumi/Hu fails to teach:
wherein the at least one comprises the conductive metal material.
Sharma teaches in para. 59:
“The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).”
A person of ordinary skill in the art would have been able to make a simple substitute the material combination of Sharma into the device of Fukuzumi with predictable results.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sharma into the device of Fukuzumi to make the conductive material of both doped-semiconductive material and a metal material. The ordinary artisan would have been motivated to modify Fukuzumi in the manner set forth above for the purpose of forming a conductive material in a semiconductor device and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuzumi (US 2022/0199641 A1) in view of Hu (US 2020/0258898 A1) as applied to claim 14 above in view of Wang (US 2023/0411285 A1).
With respect to claim 22, Fukuzumi/Hu teaches all limitations of claim 14 upon which claim 22 depends. Fukuzumi further teaches:
wherein the select-gate transistors are select gate drains (Fig. 2A, SGD transistor 16U),
Fukuzumi/Hu fails to teach:
an uppermost first tier in the stack below the conductive masses comprising a GIDL-generator erase transistor comprising one of the lower channel-material strings
Wang teaches in Fig. 8A:
an uppermost first tier (one of conductive layer 802) in the stack below the conductive masses (one of contact landing layers 708) (see annotated Fig. 8A above) comprising a GIDL-generator erase transistor (GIDL lines 702) comprising one of the lower channel-material strings (channel material strings through 702, para. 61 “Although not shown, it is understood that 3D memory device 700 may include a plurality of channel structures (e.g., channel structures 611 in FIG. 6) in a core array region, and each channel structure may extend vertically through stack structure 701 to be in contact with semiconductor layer 801”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wang into the device of Fukuzumi/Hu to make the uppermost first tier in the stack below the conductive mass to be a GIDL generator erase transistor. The ordinary artisan would have been motivated to modify Fukuzumi/Hu in the manner set forth above for the purpose of improving erase effectiveness compared to other erase mechanisms in a NAND Flash memory with an increased number of stacked layers (para. 32 of Wang).
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With respect to claim 23, Fukuzumi/Hu/Wang further teaches:
wherein the upper channel-material strings (channel-material strings through 704, para. 61 of Wang “Although not shown, it is understood that 3D memory device 700 may include a plurality of channel structures (e.g., channel structures 611 in FIG. 6) in a core array region, and each channel structure may extend vertically through stack structure 701 to be in contact with semiconductor layer 801”) above the conductive masses (see annotated Fig. 8A above) are devoid of comprising GIDL-generator erase transistors (704 of Wang comprises source select gate (SSG) lines).
Response to Arguments
Applicant’s arguments with respect to claims 14 and 27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
