Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed February 17, 2026. Claims 14 and 27 are amended. The Examiner notes that claims 14-23 and 27-30 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14, 15, 17-21, and 27-30 are rejected under 35 U.S.C. 103 as being unpatentable over by Takahashi (US 2014/0264525 A1) in view of Fukuzumi (US 2022/0199641 A1).
With respect to claim 14, Takahashi teaches in Fig. 2A:
A memory array comprising strings of memory cells, comprising:
a stack comprising vertically-alternating insulative tiers (insulating layer 121) and conductive tiers (control gate electrodes 3),
strings of memory cells comprising lower channel-material strings (portions 1x and 1y of semiconductor channel 1) that extend through the insulative tiers and the conductive tiers (see Fig. 2A);
a memory structure (memory film 13 described in para. 53-58, comprising blocking dielectric 7, charge storage regions 9, and tunnel dielectric 11) laterally adjacent each of the lower channel-material strings (portions 1x and 1y of channel 1),
the memory structure comprising a charge blocking region (blocking dielectric 7), a storage material (charge storage regions 9), and a charge passage material (tunnel dielectric 11), and comprising a planar upper surface extending across an entire width of the memory structure (see Fig. 2A, memory film 13 has a flat top surface at interface with 25)
select-gate transistors (select transistors 16U) comprising upper channel-material strings directly above the stack (Fig. 2A);
and conductive masses (conductive landing pads 25) that are individually vertically-between and directly electrically couple together individual of the upper channel-material strings to individual of the lower channel-material strings (Fig. 2A, para. 39 “The landing pad may be formed over each channel portion (except over the upper most channel portion if desired) during the same deposition step as the channel deposition step or during subsequent deposition step. Then, the next overlying channel portion is formed on the landing pad”, para. 40 “the landing pad adds an amount of resistance to the vertical NAND string, the landing pad may also be considered a resistor built into the vertical channel of the vertical NAND string.”),
the conductive masses comprising at least one of conductively-doped semiconductive conductively-doped semiconductive material (para. 38, “the landing pad is made of the same semiconductor material as the channel of the vertical NAND. For example, the landing pad may comprise a polysilicon landing pad if the channel is a polysilicon channel. A semiconductor landing pad may be intrinsic or have the same conductivity type (e.g., p or n) as the channel”) or conductive metal material (para. 38 “the landing pad may comprise a metal material (e.g., Ti, W, etc.)).
the conductive masses (25) entirely covering the planar upper surface of the memory structure (13, see Fig. 2A)
Takahashi fails to teach:
a gate insulator radially outward of the upper channel-material strings,
the gate insulator having laterally-outermost surfaces and lowest surfaces in a vertical cross-section
the upper channel-material strings extending to be directly under and directly against the lowest surfaces of the gate insulator in the vertical cross-section and extending laterally to the laterally-outermost surfaces of the gate insulator in the vertical cross-section where directly under and directly against the lowest surfaces of the gate insulator.
Fukuzumi teaches in Fig. 1P:
a gate insulator (para. 51, liner material 128 which may be silicon dioxide) radially outward of the upper channel-material strings (channel material 130),
the gate insulator having laterally-outermost surfaces and lowest surfaces in a vertical cross-section
the upper channel-material strings extending to be directly under and directly against the lowest surfaces of the gate insulator in the vertical cross-section and extending laterally to the laterally-outermost surfaces of the gate insulator in the vertical cross-section where directly under and directly against the lowest surfaces of the gate insulator. (see Fig. 1P).
Takahashi discloses the claimed invention except for shape of the gate insulator and upper channel strings. Fukuzumi discloses that it is known in the art to provide a gate insulator and upper channel string in the claimed shape. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide channel-material strings of Takahashi with a radially outward gate insulator including channel-material strings extending directly under the gate insulator in order to provide a good electrical connection between the channel strings. See MPEP 2144.
With respect to claim 15, Takahashi further teaches:
wherein the at least one is only one of the conductively-doped semiconductive material and the conductive metal material (para. 38 teaches that the landing pad may comprise a semiconductor material or “alternatively, the landing pad may comprise a metal”)
With respect to claim 17, Takahashi further teaches:
wherein the at least one comprises the conductively-doped semiconductive material (para. 38, “the landing pad is made of the same semiconductor material as the channel of the vertical NAND. For example, the landing pad may comprise a polysilicon landing pad if the channel is a polysilicon channel. A semiconductor landing pad may be intrinsic or have the same conductivity type (e.g., p or n) as the channel”).
With respect to claim 18, Takahashi further teaches:
wherein the conductively-doped semiconductive material comprises conductively n-type doped semiconductive material (para. 38, “the landing pad is made of the same semiconductor material as the channel of the vertical NAND. For example, the landing pad may comprise a polysilicon landing pad if the channel is a polysilicon channel. A semiconductor landing pad may be intrinsic or have the same conductivity type (e.g., p or n) as the channel”).
With respect to claim 19, Takahashi further teaches:
wherein the conductively-doped semiconductive material comprises conductively n-type doped polysilicon (para. 38, “the landing pad is made of the same semiconductor material as the channel of the vertical NAND. For example, the landing pad may comprise a polysilicon landing pad if the channel is a polysilicon channel. A semiconductor landing pad may be intrinsic or have the same conductivity type (e.g., p or n) as the channel”).
With respect to claim 20, Takahashi further teaches:
wherein the at least one comprises the conductive metal material (para. 38 “the landing pad may comprise a metal (e.g., Ti, W, etc.)
With respect to claim 21, Takahashi further teaches:
wherein the individual conductive masses (25) comprise an uppermost surface (top of 25) that is below a vertically-lowest gate (gate of 16U, not labeled in Fig. 2A, labeled as 16UG in Fig. 15H, which shows a step in the method of forming the device of Fig. 2A) of the select-gate transistors (select transistor 16U),
Fukuzumi further teaches:
the individual upper channel-material (130) strings extending down into one of the individual conductive masses (conductive material 122) to have a bottom therein that is below the uppermost surface of the one individual conductive mass (see Fig. 1P)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Takahashi in view of Fukuzumi as explained above.
With respect to claim 27, Takahashi teaches in Fig. 2A:
A memory array comprising strings of memory cells, comprising:
a stack comprising vertically-alternating insulative tiers (insulating layer 121) and conductive tiers (control gate electrodes 3),
strings of memory cells comprising lower channel-material strings (portions 1x and 1y of semiconductor channel 1) that extend through the insulative tiers and the conductive tiers (see Fig. 2A);
a memory structure (memory film 13 described in para. 53-58, comprising blocking dielectric 7, charge storage regions 9, and tunnel dielectric 11) laterally adjacent each of the lower channel-material strings (portions 1x and 1y of channel 1),
the memory structure comprising a charge blocking region (blocking dielectric 7), a storage material (charge storage regions 9), and a charge passage material (tunnel dielectric 11), and comprising a planar upper surface extending across an entire width of the memory structure (see Fig. 2A, memory film 13 has a flat top surface at interface with 25)
select-gate transistors (select transistors 16U) comprising upper channel-material strings directly above the stack (Fig. 2A);
and conductive masses (conductive landing pads 25) that are individually vertically-between and directly electrically couple together individual of the upper channel-material strings to individual of the lower channel-material strings (Fig. 2A, para. 39 “The landing pad may be formed over each channel portion (except over the upper most channel portion if desired) during the same deposition step as the channel deposition step or during subsequent deposition step. Then, the next overlying channel portion is formed on the landing pad”, para. 40 “the landing pad adds an amount of resistance to the vertical NAND string, the landing pad may also be considered a resistor built into the vertical channel of the vertical NAND string.”),
the conductive masses comprising at least one of conductively-doped semiconductive conductively-doped semiconductive material (para. 38, “the landing pad is made of the same semiconductor material as the channel of the vertical NAND. For example, the landing pad may comprise a polysilicon landing pad if the channel is a polysilicon channel. A semiconductor landing pad may be intrinic or have the same conductivity type (e.g., p or n) as the channel”) or conductive metal material (para. 38 “the landing pad may comprise a metal material (e.g., Ti, W, etc.)
the conductive masses (25) entirely covering the planar upper surface of the memory structure (13, see Fig. 2A)
Takahashi fails to teach:
a gate insulator radially outward of the upper channel-material strings,
the qate insulator having laterally-outermost surfaces and lowest surfaces in a vertical cross-section,
the upper channel-material strings extending to be directly under and directly against the lowest surfaces of the gate insulator in the vertical cross-section and extending laterally to the laterally-outermost surfaces of the gate insulator in the vertical cross-section where directly under and directly against the lowest surfaces of the gate insulator,
the upper channel-material strings individually having an arcuate bottom that is within individual of the conductive masses in the vertical cross-section and that extends laterally to directly below the laterally-outermost surfaces of the gate insulator in the vertical cross-section.
Fukuzumi teaches in Fig. 1P:
a gate insulator (para. 51, liner material 128 which may be silicon dioxide) radially outward of the upper channel-material strings (channel material 130),
the gate insulator having laterally-outermost surfaces and lowest surfaces in a vertical cross-section
the upper channel-material strings extending to be directly under and directly against the lowest surfaces of the gate insulator in the vertical cross-section and extending laterally to the laterally-outermost surfaces of the gate insulator in the vertical cross-section where directly under and directly against the lowest surfaces of the gate insulator. (see Fig. 1P).
the upper channel-material strings (130) individually having an arcuate bottom (see Fig. 1P, the bottom of 130 is curved) that is within individual of the conductive masses (122) in the vertical cross-section and that extends laterally to directly below the laterally-outermost surfaces of the gate insulator in the vertical cross-section.
Takahashi discloses the claimed invention except for shape of the gate insulator and upper channel strings. Fukuzumi discloses that it is known in the art to provide a gate insulator and upper channel string in the claimed shape. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide channel-material strings of Takahashi with a radially outward gate insulator including channel-material strings extending directly under the gate insulator in order to provide a good electrical connection between the channel strings. See MPEP 2144.
With respect to claim 28, Fukuzumi further teaches:
wherein the conductive masses (122) individually have an arcuate bottom (see Fig. 1P, bottom of conductive plugs 122 is curved)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Takahashi in view of Fukuzumi as explained above.
With respect to claim 29, Fukuzumi further teaches:
wherein the conductive masses (122) individually extend to below individual tops of individual of the lower channel-material strings (144) (see Fig. 1P, bottommost surface of 122 extends below topmost surface of 114).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Takahashi in view of Fukuzumi as explained above.
With respect to claim 30, Fukuzumi further teaches:
wherein the upper channel-material strings (130) are laterally narrower than the lower channel-material strings (114),
the upper channel-material strings individually being radially offset from radial centers of the individual conductive masses and individual of the lower channel-material strings. (see Fig. 1P, the upper channel pillar is narrower than the lower channel pillar and radially offset)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Takahashi in view of Fukuzumi as explained above.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2014/0264525 A1) and Fukuzumi (US 2022/0199641 A1) as applied to claims 14 above in view of Sharma (US 2019/0311756 A1).
With respect to claim 16, Takahashi/Fukuzumi teaches all limitations of independent claim 14 upon which claim 16 depends. Takahashi/Fukuzumi fails to teach:
wherein the at least one is both of the conductively-doped semiconductive material and the conductive metal material.
Sharma teaches in para. 59:
“The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).”
A person of ordinary skill in the art would have been able to make a simple substitute the material combination of Sharma into the device of Takahashi with predictable results.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Sharma into the device of Takahashi to make the conductive material of both doped-semiconductive material and a metal material. The ordinary artisan would have been motivated to modify Takahashi in the manner set forth above for the purpose of forming a conductive material in a semiconductor device and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2014/0264525 A1) and Fukuzumi (US 2022/0199641 A1) as applied to claim 14 above in view of Wang (US 2023/0411285 A1).
With respect to claim 22, Takahashi/Fukuzumi teaches all limitations of claim 14 upon which claim 22 depends. Takahashi further teaches:
wherein the select-gate transistors are select gate drains (Fig. 2A, SGD transistor 16U),
Takahashi/Fukuzumi fails to teach:
an uppermost first tier in the stack below the conductive masses comprising a GIDL-generator erase transistor comprising one of the lower channel-material strings
Wang teaches in Fig. 8A:
an uppermost first tier (one of conductive layer 802) in the stack below the conductive masses (one of contact landing layers 708) (see annotated Fig. 8A above) comprising a GIDL-generator erase transistor (GIDL lines 702) comprising one of the lower channel-material strings (channel material strings through 702, para. 61 “Although not shown, it is understood that 3D memory device 700 may include a plurality of channel structures (e.g., channel structures 611 in FIG. 6) in a core array region, and each channel structure may extend vertically through stack structure 701 to be in contact with semiconductor layer 801”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Wang into the device of Takahashi/Fukuzumi to make the uppermost first tier in the stack below the conductive mass to be a GIDL generator erase transistor. The ordinary artisan would have been motivated to modify Takahashi/Fukuzumi in the manner set forth above for the purpose of improving erase effectiveness compared to other erase mechanisms in a NAND Flash memory with an increased number of stacked layers (para. 32 of Wang).
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With respect to claim 23, Takahashi/Fukuzumi/Wang further teaches:
wherein the upper channel-material strings (channel-material strings through 704, para. 61 of Wang “Although not shown, it is understood that 3D memory device 700 may include a plurality of channel structures (e.g., channel structures 611 in FIG. 6) in a core array region, and each channel structure may extend vertically through stack structure 701 to be in contact with semiconductor layer 801”) above the conductive masses (see annotated Fig. 8A above) are devoid of comprising GIDL-generator erase transistors (704 of Wang comprises source select gate (SSG) lines).
Response to Arguments
Applicant's arguments filed February 17, 2026 have been fully considered but they are not persuasive.
Applicant argues that the prior art of record allegedly does not teach the newly amended limitations:
“a memory structure laterally adjacent each of the lower channel- material strings, the memory structure comprising a charge blocking region, a storage material and a charge passage material, and comprising a planar upper surface extending entirely across the charge blocking region, the storaqe material and the charge passage material; the conductive masses entirely covering the planar upper surface of the memory structure;”
As described above, Takahashi teaches the memory structure as claimed in para. 53-58, applicable to the embodiment of Fig. 2A. The argument is therefore found unpersuasive and the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897