DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of the claims under 35 USC 103, Applicant’s amendments and arguments have been fully considered. However, further search and consideration have prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-9, 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over US20210098400A1 (“Shen”) in view of US20070099368A1 (“Ahn”), further in view of US20200075523A1 (“Torres”), further in view of US 20180114719 A1 (“Briggs”).
RE: Claim 1, Shen discloses A method (method 10, FIG. 1) comprising:
providing a substrate (200A and/or 206, 209 formed over 200A; FIG. 2, [0011]-[0012]);
patterning a first photoresist material layer (220A in FIG. 6A) overlying the substrate to form a first opening (222 defined by in 220A in FIG. 6A) with a first width (first width of 222 defined by 220A in FIG. 6A) in the first photoresist material layer;
patterning a second photoresist material layer (220B in FIG. 6A) overlying the first photoresist material layer to form a second opening (222 defined by 220B in FIG. 6A) aligned with the first opening with a second width (second width of 222 defined by 220B in FIG. 6A) in the second photoresist material layer;
depositing metal (copper included in 230, [0029], FIG. 7A) in the first and second openings to form a metal trace (230);
forming a dielectric layer (combination of 240 and 246, FIGs. 9-12, 240 includes silicon nitride or silicon oxide, [0034]; 246 includes polyimide, [0036]; the instant application identifies silicon nitride, silicon oxide, polyimide as dielectric materials, [0040], [0045]) overlying the substrate; and
forming an interconnection metal layer (seed layer of bump 250 includes copper, [0039]-[0040]; bump 250 includes a seed layer (not depicted) disposed under the bulk conductive layer in the opening 248, [0039], see FIGs. 13, 14A-14B on the metal trace.
Shen does not explicitly disclose:
the bottom layer 220A is a photoresist;
the process of patterning the second photoresist material layer overlying the first photoresist material layer to form the second opening aligned with the first opening with the second width in the second photoresist material layer is performed after forming the first opening with the first width in the first photoresist material layer;
the second width of the second opening is smaller than the first width of the first opening,
wherein the interconnection metal layer is coplanar with the dielectric layer.
However, Shen discloses both the bottom layer 220A and the photoresist layer 220B (together referred to as the masking element 220) are configured to be patternable by the same lithography process. For example, the lithography process may include exposing the masking element 220 to a radiation source (e.g., extreme ultraviolet, or EUV, radiation) through a photomask, and developing the exposed masking element 220 to form a desired pattern in the masking element 220, [0019]. Since 220A and 220B are patterned by being exposed to light through a photomask and developed to form a desired pattern, 220A and 220B are both considered a photoresist.
Alternatively or additionally, in the same field of endeavor, Ahn discloses photoresist layers 27, 28, 29 and 30 are patterned by a photolithography process, an electron beam lithography process, etc. to form an opening, FIG. 2D, [0026]. Ahn further teaches Here, the composition of the first and second photoresist layers 27 and 28 should be decided by considering an etch selectivity so as not to damage the first and second photoresist layers 27 and 28 while the third insulating layer 26 is over-etched, [0027]. FIG. 2D in Ahn shows that each photoresist layer 27, 28, 29, 30 has a different opening width, where the width of the opening in 30 is smaller than the width of the opening in 29.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the bottom layer 220A a photoresist layer as taught by Ahn in order to simplify manufacturing as this would result in the bottom layer 220A and the photoresist layer 220B each being configured to be patternable by a lithography process as taught by Shen, which Shen teaches includes exposing the masking element 220 to a radiation source (e.g., extreme ultraviolet, or EUV, radiation) through a photomask, and developing the exposed masking element 220 to form a desired pattern in the masking element 220, [0019].
In the same field of endeavor, Torres discloses in FIGs. 5A-5B:
patterning a first resist material layer (502 in FIG. 5A, [0038]) overlying a substrate (102) to form a first opening (504) with a first width (first width of 504 in FIG. 5A) in the first resist material layer;
after forming the first opening with the first width in the first resist material layer, patterning a second resist material layer (506 in FIG. 5B) overlying the first resist material layer to form a second opening (508) aligned with the first opening with a second width (second width of 508 in FIG. 5B is smaller than first width of 504) smaller than the first width in the second resist material layer;
depositing metal in the first and second openings to form a metal trace (electroplating a metal to the contact 106 to fabricate the conductive bump 108, [0038]).
As Torres discloses that each of the resists 502 and 506 are patterned and etched to form first and second openings 504, 506 on a substrate 102 for the deposition of metal, [0038] each of the patterned resists 502 and 506 functions as a mask.
Further, Torres teaches that film resists are illuminated prior to etching, [0031].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first patterning process in FIG. 6A so that forming the bottom layer 220A of the masking element 220 is formed with a first opening having a first width is performed before forming the photoresist layer 220B of the masking element 220 with a second opening having a second width smaller than the first width as taught by Torres in order to widen the starting width of the first opening in the bottom layer 220A in FIG. 6A, thereby widening the base of the resulting RDL 230 to improve its structural and mechanical integrity.
In the same field of endeavor, Briggs discloses in FIG. 2C:
The coplanar surface of the dielectric layer 14, barrier layer 16, seed layer 18 (if employed), and interconnect 20 provides sufficient line resistance and cap coverage, [0053].
Briggs further teaches the coplanar surface includes materials of the dielectric layer, barrier layer, interconnect, and seed layer (if employed). As described above, the wet etch process enables barrier planarization to provide coplanar interconnect structures, and the damage experienced with the interconnect structures is greatly diminished, [0058]
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric layer 246 and the seed layer of 250 to be coplanar as taught by Briggs in order to prevent any damage to 250 as further taught by Briggs.
RE: Claim 3, Shen in view of Ahn, Torres, Briggs discloses The method of claim 1, wherein prior to patterning the first photoresist material layer overlying the substrate, the method further comprises depositing at least one seed layer (Shen: 216, FIG. 4 which is before 220A and 220B are formed, [0016]) on the substrate.
RE: Claim 4, Shen in view of Ahn, Torres, Briggs discloses The method of claim 3, wherein prior to forming the dielectric layer overlying the substrate, the method further comprises removing the first and second photoresist material layers via a first etching process (Shen: referring to FIG. 8, the patterned masking element 220 is removed, [0030]; FIG. 8 is before FIGs. 9-12 which shows dielectric 240, 246).
RE: Claim 5, Shen in view of Ahn, Torres, Briggs discloses The method of claim 4, further comprising removing exposed portions of the at least one seed layer via a metal etching process (Shen: portions of the seed layer 216 not disposed under the RDL 230 are selectively removed from the workpiece 200 without removing, or substantially removing, portions of the RDL 230 or the first passivation layer 212. In one example, the etching process may be a dry etching process, [0030], FIG. 8; the seed layer is metal, [0016], therefore, etching portions of the seed layer is considered a metal etching process).
RE: Claim 6, Shen in view of Ahn, Torres, Briggs discloses The method of claim 1, wherein forming the dielectric layer overlying the substrate includes depositing the dielectric layer over the substrate and the metal trace (Shen: FIGs. 11-12 show 240, 246 deposited over 230 and 206, 209 which are formed over 200A) and patterning the dielectric layer to form an opening (248, FIG. 12) over all or a portion of the metal trace.
RE: Claim 7, Shen in view of Ahn, Torres, Briggs discloses The method of claim 6, wherein forming the interconnection metal layer on the metal trace comprises depositing the interconnection metal layer (Shen: seed layer of bump 250 including copper, [0039]-[0040]) in the opening of the dielectric layer and on the metal trace.
RE: Claim 8, Shen in view of Ahn, Torres, Briggs discloses The method of claim 7, further comprising patterning a third photoresist material layer (Shen: masking element (not depicted) including a photoresist layer over the protection layer 246, [0040]) overlying the dielectric layer to form an opening (re-exposed opening 248, [0040]; Shen teaches exposing the masking element to a radiation source through a photomask, developing the exposed masking element to form a patterned masking element that re-exposes at least the opening 248, [0040]) over the interconnection metal layer.
RE: Claim 9, Shen in view of Ahn, Torres, Briggs discloses The method of claim 8, further comprising depositing an under bump metallization layer (Shen: bulk conductive layer of 250, [0039]-[0040]; FIG. 13 shows 250 in 240, 246) in the opening of the third photoresist material layer (250 would be deposited in the opening of the photoresist layer so that it is deposited in 248) and on the interconnection metal layer (forming the bulk conductive layer over the seed layer, [0040]) and removing the third photoresist material layer via a second etching process (After forming the solder layer 252, the patterned masking element is removed by wet etching, [0041]).
RE: Claim 21, Shen in view of Ahn, Torres, Briggs discloses The method of claim 3, wherein the at least one seed layer comprises titanium tungsten (TiW) or copper (Cu) (Shen teaches the seed layer 216 includes copper, [0016]).
RE: Claim 22, Shen in view of Ahn, Torres, Briggs discloses The method of claim 1, wherein the interconnection metal layer comprises Cu (Shen teaches seed layer of bump 250 includes copper, [0039]-[0040]).
RE: Claim 23, Shen in view of Ahn, Torres, Briggs discloses The method of claim 9, wherein the under bump metallization layer comprises Cu (Shen: bulk conductive layer of 250 includes copper, [0039]).
RE: Claim 24, Shen in view of Ahn, Torres, Briggs discloses The method of claim 9, further comprising forming a solder bump (Shen: 252 or 252’, FIGs. 13, 14A-14B) on the under bump metallization layer.
RE: Claim 25, Shen in view of Ahn, Torres, Briggs discloses The method of claim 1, wherein the dielectric layer comprises polyimide (Shen: 246 includes polyimide, [0036]).
RE: Claim 26, Shen in view of Ahn, Torres, Briggs discloses The method of claim 1, wherein the dielectric layer comprises silicon oxide or silicon nitride (Shen: 240 includes silicon oxide or silicon nitride, [0034]).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Ahn, further in view of Torres, further in view of Briggs as applied to claim 3, and further in view of US 8168540 B1 to Reid et al. (hereinafter “Reid”).
RE: Claim 27, Shen in view of Ahn, Torres, Briggs does not explicitly disclose The method of claim 3, wherein the at least one seed layer is deposited via electroplating.
However, in the same field of endeavor, Reid discloses that a copper seed layer is deposited via electroplating, Col. 4, lines 9-11. Reid further discloses that electroplating processes can typically deposit very thin conformal films, the invention addresses the conflict between excessive field thickness and inadequate sidewall coverage obtained with films laid using PVD, Col. 1, lines 45-50.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit the seed layer via electroplating as taught by Reid which would allow the deposition of a very thin conformal seed layer, which would ensure adequate sidewall coverage in 214 in FIG. 4 of Shen while saving material costs.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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