DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/10/2026 has been entered.
Response to Amendment
The amendment with respect to claim(s) 1, 11, and 20 filed on 01/29/2026 have been fully considered for examination based on their merits. The previously presented claims 2-10, and 12-19 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 9-11, filed 01/29/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of LIAO.
Regarding Independent Claim(s) 1. The Applicant argues that the prior art, LIAO and HUANG fails to disclose or suggest the newly amended features to claims 1, 11 and 20. The Examiner agrees that the arguments are persuasive, and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph.
Regarding Claim(s) 2-20. The independent Claim(s) 11 and 20, and dependent claims 2-10, and 12-19 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 9, 11-15, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yi-Bp Liao et al, (hereinafter LIAO), US 20210366907 A1, in view of HUANG, (Prior Art used in the previous Office Action filed on 01/23/2026).
Regarding Claim 1, LIAO teaches a semiconductor structure (Fig. 2, 200, workpiece, [0020]) comprising:
a first stacked device structure (Figs. 16A/16B, 200, workpiece) comprising:
a first field-effect transistor (annotated Figures 16A/16B) disposed on a substrate (Figs. 16A/16B, 202) having a front side (annotated Figures 16A/16B) and a back side (annotated Figures 16A/16B), the first field-effect transistor (annotated Figures 16A/16B) comprising a sidewall of a first source/drain region (Figs. 16A/16B, 228S/228D, first source/drain feature) disposed on a sidewall of the first field-effect transistor (annotated Figures 16A/16B);
a second field-effect transistor (annotated Figures 16A/16B) vertically stacked (Figs. 16A/16B, Z direction) above the first field-effect transistor (annotated Figures 16A/16B), the second field-effect transistor (annotated Figures 16A/16B) comprising a sidewall of a second source/drain region (Figs. 16A/16B, 244S/244D, second source/drain feature) disposed on a sidewall of the second field-effect transistor (annotated Figures 16A/16B);
a first front side source/drain contact (Figs. 16B, 234, first drain contact) disposed on a top surface of the first source/drain region (Fig. 16B, 228D, first drain feature);
a first back side source/drain contact (Figs. 16A/16B, 250/252, top source contact/second drain contact) disposed on a bottom surface of the second source/drain region (Figs. 16A/16B, 244S/244D, second source/drain feature).
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LIAO does not explicitly disclose a semiconductor structure comprising: a first isolation pillar structure located within the first field-effect transistor, the second field-effect transistor, the first front side source/drain contact and the first back side source/drain contact.
HUANG teaches a semiconductor structure (Fig. 2, 200, integrated circuit structure) comprising:
a first isolation pillar structure (Fig. 2, 202, dielectric walls) located within the first field-effect transistor (annotated Figure 2(ii); lower left of part 2(ii), [0046]), the second field-effect transistor (annotated Figure 2(ii); upper left of part 2(ii), [0046]), the first front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) and the first back side source/drain contact (Fig. 2(iii), 206, upper source/drain contacts).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LIAO to incorporate the teachings of HUANG, such that a semiconductor structure comprising: a first isolation pillar structure located within the first field-effect transistor, the second field-effect transistor, the first front side source/drain contact and the first back side source/drain contact, so that the self-aligned dielectric wall in combination with nanowire or nanoribbon transistors enable to reduce the space at an NMOS and PMOS boundary and eventually lead to an ultimately scaled 3-D stacked nanocomb (forksheet) CMOS architecture (HUANG, [0026]).
Regarding Claim 2, LIAO as modified by HUANG teaches the semiconductor structure of claim 1.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), wherein the first isolation pillar structure (Fig. 2, 202/201, backbone, or dielectric wall, [0037]) separates a first part (annotated Figure 2(iii) above) of the first source/drain region (Fig. 2(iii), 224, lower source/drain structures) and the first front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) from a second part (annotated Figure 2(iii) above) of the first source/drain region and the first front side source/drain contact and a first part of the second source/drain region (Fig. 2(iii), 226, upper source/drain structures) and the first back side source/drain contact (Fig. 2(iii), 206, upper source/drain contacts) from a second part of the second source/drain region and the first back side source/drain contact.
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Regarding Claim 3, LIAO as modified by HUANG teaches the semiconductor structure of claim 1.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), further comprising:
a second stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]) adjacent to the first stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]), the second stacked device structure comprising:
a third field-effect transistor (annotated Figure 2 (ii) ); lower right of part 2(ii), [0046]) disposed on the substrate (Fig. 1, 101), the third field-effect transistor comprising a third source/drain region (Fig. 2(iii), 224, lower source/drain structures);
a fourth field-effect transistor (annotated Figure 2 (ii) ); upper right of part 2(ii), [0046]) vertically stacked (annotated Figure 2 (ii), [0046]) above the third field-effect transistor, the fourth field-effect transistor comprising a fourth source/drain region (Fig. 2(iii), 226, upper source/drain structures);
a second front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) disposed on the third source/drain region (Fig. 2(iii), 224, lower source/drain structures);
a second back side source/drain contact (Fig. 2(iii), 206, upper source/drain contacts) disposed on the fourth source/drain region (Fig. 2(iii), 226, upper source/drain structures); and
a second isolation pillar structure (Fig. 2, 201, backbone) located within the third field-effect transistor (annotated Figure 2 (ii) ); lower right of part 2(ii), [0046]), the fourth field-effect transistor (annotated Figure 2 (ii) ); upper right of part 2(ii), [0046]), the second front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) and the second back side source/drain contact (Fig. 2(iii), 206, upper source/drain contacts).
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Regarding Claim 4, LIAO as modified by HUANG teaches the semiconductor structure of claim 3.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), further comprising:
a third isolation pillar structure (Fig. 2(ii), 201, backbone, or dielectric wall, [0037]) located between the first stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]) and the second stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]).
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Regarding Claim 5, LIAO as modified by HUANG teaches the semiconductor structure of claim 4.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), further comprising:
a gate disposed between (Fig. 2(ii), 204/208, upper gate electrode/lower gate electrode, [0037]) the first stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]) and the second stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]); and
a third isolation pillar structure (Fig. 2(ii), 201, backbone, or dielectric wall, [0037]) disposed within the gate (Fig. 2(ii), 204/208, upper gate electrode/lower gate electrode, [0037]) between the first stacked device structure and the second stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]).
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Regarding Claim 6, HUANG teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure) of claim 3, further comprising:
an interconnect structure (Fig. 2, 220/214, upper vias/lower vias; 218/212, corresponding lines; 244, through wall via enables front to back or back to front routing, [0039-0041]) located between the first stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]) and the second stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]).
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Regarding Claim 9, LIAO as modified by HUANG teaches the semiconductor structure of claim 1.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), wherein the first field-effect transistor (annotated Figure 2 (ii); lower left of part 2(ii), [0046]) and the second field-effect transistor (annotated Figure 2 (ii); lower left of part 2(ii), [0046]) comprise respective nanosheet field-effect transistor devices (Fig. 2(ii), 203, semiconductor channels, are first and second stacks of nanoribbons or nanowires, [0044]).
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Regarding Claim 11, LIAO teaches a semiconductor structure (Fig. 2, 200, workpiece, [0020]) comprising:
a first stacked device structure (Figs. 16A/16B, 200, workpiece) comprising:
a first field-effect transistor (annotated Figures 16A/16B) disposed on a substrate (Figs. 16A/16B, 202) having a front side (annotated Figures 16A/16B) and a back side (annotated Figures 16A/16B), the first field-effect transistor (annotated Figures 16A/16B) comprising a sidewall of a first source/drain region (Figs. 16A/16B, 228S/228D, first source/drain feature) disposed on a sidewall of the first field-effect transistor (annotated Figures 16A/16B);
a second field-effect transistor (annotated Figures 16A/16B) vertically stacked (Figs. 16A/16B, Z direction) above the first field-effect transistor (annotated Figures 16A/16B), the second field-effect transistor (annotated Figures 16A/16B) comprising a sidewall of a second source/drain region (Figs. 16A/16B, 244S/244D, second source/drain feature) disposed on a sidewall of the second field-effect transistor (annotated Figures 16A/16B);
a first front side source/drain contact (Figs. 16B, 234, first drain contact) disposed on a top surface of the first source/drain region (Fig. 16B, 228D, first drain feature);
a first back side source/drain contact (Figs. 16A/16B, 250/252, top source contact/second drain contact) disposed on a bottom surface of the second source/drain region (Figs. 16A/16B, 244S/244D, second source/drain feature).
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LIAO does not explicitly disclose a semiconductor structure comprising: a first isolation pillar structure located within the first field-effect transistor, the second field-effect transistor, the first front side source/drain contact and the first back side source/drain contact.
HUANG teaches a semiconductor structure (Fig. 2, 200, integrated circuit structure) comprising:
a first isolation pillar structure (Fig. 2, 202, dielectric walls) located within the first field-effect transistor (annotated Figure 2(ii); lower left of part 2(ii), [0046]), the second field-effect transistor (annotated Figure 2(ii); upper left of part 2(ii), [0046]), the first front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) and the first back side source/drain contact (Fig. 2(iii), 206, upper source/drain contacts).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LIAO to incorporate the teachings of HUANG, such that a semiconductor structure comprising: a first isolation pillar structure located within the first field-effect transistor, the second field-effect transistor, the first front side source/drain contact and the first back side source/drain contact, so that the self-aligned dielectric wall in combination with nanowire or nanoribbon transistors enable to reduce the space at an NMOS and PMOS boundary and eventually lead to an ultimately scaled 3-D stacked nanocomb (forksheet) CMOS architecture (HUANG, [0026]).
Regarding Claim 12, LIAO as modified by HUANG teaches the integrated circuit of claim 11.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), wherein the first isolation pillar structure (Fig. 2, 202/201, backbone, or dielectric wall, [0037]) separates a first part (annotated Figure 2(iii) above) of the first source/drain region (Fig. 2(iii), 224, lower source/drain structures) and the first front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) from a second part (annotated Figure 2(iii) above) of the first source/drain region and the first front side source/drain contact and a first part of the second source/drain region (Fig. 2(iii), 226, upper source/drain structures) and the first back side source/drain contact (Fig. 2(iii), 206, upper source/drain contacts) from a second part of the second source/drain region and the first back side source/drain contact.
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Regarding Claim 13, LIAO as modified by HUANG teaches the semiconductor structure of claim 11.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), wherein at least one of the one or more semiconductor structures (Fig. 2, 200, integrated circuit structure, [0042]) further comprises:
a second stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]) adjacent to the first stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]), the second stacked device structure comprising:
a third field-effect transistor (annotated Figure 2 (ii) ); lower right of part 2(ii), [0046]) disposed on the substrate (Fig. 1, 101), the third field-effect transistor comprising a third source/drain region (Fig. 2(iii), 224, lower source/drain structures);
a fourth field-effect transistor (annotated Figure 2 (ii) ); upper right of part 2(ii), [0046]) vertically stacked (annotated Figure 2 (ii), [0046]) above the third field-effect transistor, the fourth field-effect transistor comprising a fourth source/drain region (Fig. 2(iii), 226, upper source/drain structures);
a second front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) disposed on the third source/drain region (Fig. 2(iii), 224, lower source/drain structures);
a second back side source/drain contact (Fig. 2(iii), 206, upper source/drain contacts) disposed on the fourth source/drain region (Fig. 2(iii), 226, upper source/drain structures); and
a second isolation pillar structure (Fig. 2, 201, backbone) located within the third field-effect transistor (annotated Figure 2 (ii) ); lower right of part 2(ii), [0046]), the fourth field-effect transistor (annotated Figure 2 (ii) ); upper right of part 2(ii), [0046]), the second front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) and the second back side source/drain contact (Fig. 2(iii), 206, upper source/drain contacts).
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Regarding Claim 14, LIAO as modified by HUANG teaches the semiconductor structure of claim 13.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), wherein at least one of the one or more semiconductor structures (Fig. 2, 200, integrated circuit structure, [0042]) further comprises:
a gate disposed between (Fig. 2(ii), 204/208, upper gate electrode/lower gate electrode, [0037]) the first stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]) and the second stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]); and
a third isolation pillar structure (Fig. 2(ii), 201, backbone, or dielectric wall, [0037]) disposed within the gate (Fig. 2(ii), 204/208, upper gate electrode/lower gate electrode, [0037]) between the first stacked device structure and the second stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]).
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Regarding Claim 15, LIAO as modified by HUANG teaches the semiconductor structure of claim 13.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), wherein at least one of the one or more semiconductor structures (Fig. 2, 200, integrated circuit structure, [0042]) further comprises:
an interconnect structure (Fig. 2, 220/214, upper vias/lower vias; 218/212, corresponding lines; 244, through wall via enables front to back or back to front routing, [0039-0041]) located between the first stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]) and the second stacked device structure (annotated Figure 2 (ii), cut on the gate structure, [0046]).
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Regarding Claim 18, LIAO as modified by HUANG teaches the semiconductor structure of claim 11.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), wherein the first field-effect transistor (annotated Figure 2 (ii); lower left of part 2(ii), [0046]) and the second field-effect transistor (annotated Figure 2 (ii); lower left of part 2(ii), [0046]) comprise respective nanosheet field-effect transistor devices (Fig. 2(ii), 203, semiconductor channels, are first and second stacks of nanoribbons or nanowires, [0044]).
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Regarding Claim 20, LIAO teaches a semiconductor structure (Fig. 2, 200, workpiece, [0020]) comprising:
a first stacked device structure (Figs. 16A/16B, 200, workpiece) comprising:
a first field-effect transistor (annotated Figures 16A/16B) disposed on a substrate (Figs. 16A/16B, 202) having a front side (annotated Figures 16A/16B) and a back side (annotated Figures 16A/16B), the first field-effect transistor (annotated Figures 16A/16B) comprising a sidewall of a first source/drain region (Figs. 16A/16B, 228S/228D, first source/drain feature) disposed on a sidewall of the first field-effect transistor (annotated Figures 16A/16B);
a second field-effect transistor (annotated Figures 16A/16B) vertically stacked (Figs. 16A/16B, Z direction) above the first field-effect transistor (annotated Figures 16A/16B), the second field-effect transistor (annotated Figures 16A/16B) comprising a sidewall of a second source/drain region (Figs. 16A/16B, 244S/244D, second source/drain feature) disposed on a sidewall of the second field-effect transistor (annotated Figures 16A/16B);
a first front side source/drain contact (Figs. 16B, 234, first drain contact) disposed on a top surface of the first source/drain region (Fig. 16B, 228D, first drain feature);
a first back side source/drain contact (Figs. 16A/16B, 250/252, top source contact/second drain contact) disposed on a bottom surface of the second source/drain region (Figs. 16A/16B, 244S/244D, second source/drain feature).
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LIAO does not explicitly disclose a semiconductor structure comprising: a first isolation pillar structure located within the first field-effect transistor, the second field-effect transistor, the first front side source/drain contact and the first back side source/drain contact.
HUANG teaches a semiconductor structure (Fig. 2, 200, integrated circuit structure) comprising:
a first isolation pillar structure (Fig. 2, 202, dielectric walls) located within the first field-effect transistor (annotated Figure 2(ii); lower left of part 2(ii), [0046]), the second field-effect transistor (annotated Figure 2(ii); upper left of part 2(ii), [0046]), the first front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) and the first back side source/drain contact (Fig. 2(iii), 206, upper source/drain contacts).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LIAO to incorporate the teachings of HUANG, such that a semiconductor structure comprising: a first isolation pillar structure located within the first field-effect transistor, the second field-effect transistor, the first front side source/drain contact and the first back side source/drain contact, so that the self-aligned dielectric wall in combination with nanowire or nanoribbon transistors enable to reduce the space at an NMOS and PMOS boundary and eventually lead to an ultimately scaled 3-D stacked nanocomb (forksheet) CMOS architecture (HUANG, [0026]).
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIAO, in view of HUANG, as applied to claim(s) 1-6, 9, 11-15, 18, and 20 and further in view of YU, (Prior Art used in the previous Office Action filed on 01/23/2026).
Regarding Claim 7, LIAO as modified by HUANG teaches the semiconductor structure of claim 6.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), further comprising:
a back side power rail connected to the interconnect structure with a metal via (Fig. 2(iii) 244, dielectric wall, backside via/metal line can route through the dielectric wall to communicate with the front side interconnect, [0053]);
wherein the first front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) is electrically connected to the back side power rail ([0040-0041]) through the interconnect structure and the metal via (Fig. 2(iii) 244, through-via, [0053]).
Though HUANG teaches a backside power delivery, LIAO as modified by HUANG does not explicitly disclose the semiconductor structure, further comprising: a back side power rail connected to the interconnect structure with a metal via; wherein the first front side source/drain contact is electrically connected to the back side power rail through the interconnect structure and the metal via.
YU teaches the semiconductor structure (Figs. 10/24, 100), further comprising:
a back side power rail connected to the interconnect structure with a metal via (Fig. 24, metal contacts on the backside and the backside power rail are formed by backside processes, [0010], [0066]);
wherein the first front side source/drain contact (Fig. 10, 115a/115b, S/D region, [0036], [0045]) is electrically connected to the back side power rail through the interconnect structure and the metal via ([0036], [0045], [0063], [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIAO as modified by HUANG to incorporate the teachings of YU, such that the semiconductor structure, further comprising: a back side power rail connected to the interconnect structure with a metal via; wherein the first front side source/drain contact is electrically connected to the back side power rail through the interconnect structure and the metal via, so that the epitaxial S/D feature (146) formed over the S/D region (115a/115b) is to be connected power rail to improve the performance of the FETs (YU, [0010], [0063]).
Regarding Claim 16, LIAO as modified by HUANG teaches the semiconductor structure of claim 15.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), wherein at least one of the one or more semiconductor structures (Fig. 2, 200, integrated circuit structure, [0042]) further comprises:
a back side power rail connected to the interconnect structure with a metal via (Fig. 2(iii) 244, dielectric wall, backside via/metal line can route through the dielectric wall to communicate with the front side interconnect, [0053]);
wherein the first front side source/drain contact (Fig. 2(iii), 230, lower source/drain contacts, [0038]) is electrically connected to the back side power rail ([0040-0041]) through the interconnect structure and the metal via (Fig. 2(iii) 244, through-via, [0053]).
Though HUANG teaches a backside power delivery, LIAO as modified by HUANG does not explicitly disclose the semiconductor structure, further comprising: a back side power rail connected to the interconnect structure with a metal via; wherein the first front side source/drain contact is electrically connected to the back side power rail through the interconnect structure and the metal via.
YU teaches the semiconductor structure (Figs. 10/24, 100), further comprising:
a back side power rail connected to the interconnect structure with a metal via (Fig. 24, metal contacts on the backside and the backside power rail are formed by backside processes, [0010], [0066]);
wherein the first front side source/drain contact (Fig. 10, 115a/115b, S/D region, [0036], [0045]) is electrically connected to the back side power rail through the interconnect structure and the metal via ([0036], [0045], [0063], [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIAO as modified by HUANG to incorporate the teachings of YU, such that the semiconductor structure, further comprising: a back side power rail connected to the interconnect structure with a metal via; wherein the first front side source/drain contact is electrically connected to the back side power rail through the interconnect structure and the metal via, so that the epitaxial S/D feature (146) formed over the S/D region (115a/115b) is to be connected power rail to improve the performance of the FETs (YU, [0010], [0063]).
Claim(s) 8, 10, 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIAO, as modified by HUANG, as applied to claim(s) 1-6, 9, 11-15, 18, and 20, and further in view of FROUGIER, (Prior Art used in the previous Office Action filed on 01/23/2026).
Regarding Claim 8, LIAO as modified by HUANG teaches the semiconductor structure of claim 6.
LIAO as modified by HUANG does not explicitly disclose the integrated circuit, further comprising: a middle-of-the-line contact disposed on one end of the interconnect structure; and a metal via connected to the first back side source/drain contact and the other end of the interconnect structure; wherein the first source/drain region is a first back side source/drain region and is electrically connected to a front side signal line through the first back side source/drain contact, the metal via, the interconnect structure and the middle-of-the-line contact.
FROUGIER teaches the integrated circuit (Stacked IC structures, [Col. 1, Lines 50-55]), further comprising: a middle-of-the-line contact (Fig. 17, 1810 conductive metal, [Col 9, Lines 59-Col. 10, Lines 5]) disposed on one end of the interconnect structure; and a metal via connected to the first back side source/drain contact and the other end of the interconnect structure (Figs. 13-17, wrap around metal region, [Col. 9, Lines 10-35]); wherein the first source/drain region is a first back side source/drain region (Figs. 7/17, S1/D1, first source/first drain) and is electrically connected to a front side signal line through the first back side source/drain contact, the metal via, the interconnect structure and the middle-of-the-line contact ([Col. 8, Lines 65-Col. 9, Lines 10]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIAO as modified by HUANG to incorporate the teachings of FROUGIER, such that the semiconductor structure, further comprising: a middle-of-the-line contact disposed on one end of the interconnect structure; and a metal via connected to the first back side source/drain contact and the other end of the interconnect structure; wherein the first source/drain region is a first back side source/drain region and is electrically connected to a front side signal line through the first back side source/drain contact, the metal via, the interconnect structure and the middle-of-the-line contact, so that the aforementioned structural arrangement resulting CFET device with wrap around contacts for use in a semiconductor structure that maintain vertical integration and electrical connection of vertically stacked FETs, i.e. electrical connection/disconnection of nFET and pFET source/drain epitaxies (FROUGIER, [Col. 13, Lines 30-40]).
Regarding Claim 10, LIAO as modified by HUANG teaches the semiconductor structure of claim 1.
HUANG does not explicitly disclose the integrated circuit claim 1, wherein the first field-effect transistor and the second field-effect transistor provide a complementary field-effect transistor structure.
FROUGIER teaches the integrated circuit (Stacked IC structures, [Col. 1, Lines 50-55]) claim 1, wherein the first field-effect transistor (Fig. 7, 820, first FET structure) and the second field-effect transistor (Fig. 12, 1330, second FET structure) provide a complementary field-effect transistor structure ([Col. 13, Lines 30-40]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIAO as modified by HUANG to incorporate the teachings of FROUGIER, such that the semiconductor structure, wherein the first field-effect transistor and the second field-effect transistor provide a complementary field-effect transistor structure, so that the CFETs with wrap around contacts for use in a semiconductor device that maintain vertical integration and electrical connection of vertically stacked FETs, and thus provide the CFET structure provides a way to increase the effective contact area while preserving aggressively scaled contact poly pitch (CPP) also known as transistor gate pitch (FROUGIER, [Col. 13, Lines 30-40]; [Col. 1, Lines 45-50]).
Regarding Claim 17, LIAO as modified by HUANG teaches the semiconductor structure of claim 15.
HUANG further teaches the semiconductor structure (Fig. 2, 200, integrated circuit structure), wherein at least one of the one or more semiconductor structures (Fig. 2, 200, integrated circuit structure, [0042]).
LIAO as modified HUANG does not explicitly disclose the integrated circuit, wherein at least one of the one or more semiconductor structures further comprises: a middle-of-the-line contact disposed on one end of the interconnect structure; and a metal via connected to the first back side source/drain contact and the other end of the interconnect structure; wherein the first source/drain region is a first back side source/drain region and is electrically connected to a front side signal line through the first back side source/drain contact, the metal via, the interconnect structure and the middle-of-the-line contact.
FROUGIER teaches the integrated circuit (Stacked IC structures, [Col. 1, Lines 50-55]), wherein at least one of the one or more semiconductor structures further comprises: a middle-of-the-line contact (Fig. 17, 1810 conductive metal, [Col 9, Lines 59-Col. 10, Lines 5]) disposed on one end of the interconnect structure; and a metal via connected to the first back side source/drain contact and the other end of the interconnect structure (Figs. 13-17, wrap around metal region, [Col. 9, Lines 10-35]); wherein the first source/drain region is a first back side source/drain region (Figs. 7/17, S1/D1, first source/first drain) and is electrically connected to a front side signal line through the first back side source/drain contact, the metal via, the interconnect structure and the middle-of-the-line contact ([Col. 8, Lines 65-Col. 9, Lines 10]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LIAO as modified by HUANG to incorporate the teachings of FROUGIER, such that the semiconductor structure, wherein at least one of the one or more semiconductor structures further comprises: a middle-of-the-line contact disposed on one end of the interconnect structure; and a metal via connected to the first back side source/drain contact and the other end of the interconnect structure; wherein the first source/drain region is a first back side source/drain region and is electrically connected to a front side signal line through the first back side source/drain contact, the metal via, the interconnect structure and the middle-of-the-line contact, so that the aforementioned structural arrangement resulting CFET device with wrap around contacts for use in a semiconductor structure that maintain vertical integration and electrical connection of vertically stacked FETs, i.e. electrical connection/disconnection of nFET and pFET source/drain epitaxies (FROUGIER, [Col. 13, Lines 30-40]).
Regarding Claim 19, LIAO as modified by HUANG teaches the semiconductor structure of claim 11.
LIAO as modified by HUANG does not explicitly disclose the integrated circuit, wherein the first field-effect transistor and the second field-effect transistor provide a complementary field-effect transistor structure.
FROUGIER teaches the integrated circuit (Stacked IC structures, [Col. 1, Lines 50-55]), wherein the first field-effect transistor (Fig. 7, 820, first FET structure) and the second field-effect transistor (Fig. 12, 1330, second FET structure) provide a complementary field-effect transistor structure ([Col. 13, Lines 30-40]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LIAO as modified by HUANG to incorporate the teachings of FROUGIER, such that the semiconductor structure, wherein the first field-effect transistor and the second field-effect transistor provide a complementary field-effect transistor structure, so that the CFETs with wrap around contacts for use in a semiconductor device that maintain vertical integration and electrical connection of vertically stacked FETs, and thus provide the CFET structure provides a way to increase the effective contact area while preserving aggressively scaled contact poly pitch (CPP) also known as transistor gate pitch (FROUGIER, [Col. 13, Lines 30-40]; [Col. 1, Lines 45-50]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220109046 A1 – Figure 2B
STATEMENT OF RELEVANCE – The source/drain contacts (221/222/223/224) are disposed on top and bottom of the source/drain regions (211/212/213/214) of the multi-stack transistor structure.
US 20210296315 A1 – Figure 7
STATEMENT OF RELEVANCE – A cross-sectional illustration of stacked forksheet transistors with a interconnect to a gate electrode from a bottom contact.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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