DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 12/8/2025. Claims 1-20 are pending and have been examined. Claims 1, 3-4, 11, 16-18 and 20 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 11-15 are objected to because of the following informalities:
In regards to claim 11, lines 10-14 amend the language as followed to remove redundant language “…
Claims 12-15 are dependent upon claim 11 above and therefore are similarly objected to for including the deficiencies of claim 11 above.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “A graphics processor” and thus a machine, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “…merge operands associated with the memory access messages to perform a bitwise atomic operation, the one or more memory access messages having addresses within a same 4-byte location in memory”, that under its broadest reasonable interpretation encompasses mental processes and/or mathematical concepts. For example, merging operands to perform a bitwise atomic operation as discussed in paragraphs [0372-0374] comprises performing a bitwise OR or AND operation on operand values of requests that target a same 32-bit memory location in order to perform an additional bitwise operation (e.g. bitwise atomic OR or AND operation), which can be performed mentally (or with the aid or pen and paper); also, a bitwise OR or AND operation can be considered a Boolean operation which is a mathematical operation. (See MPEP 2106.04(a)(2) (I and III)). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind, or with the aid of pen and paper, but for the recitation of generic computer components (i.e. a processor, system interface, circuitry and a memory), then it falls within the “Mental Processes” and/or “Mathematical Concepts” groupings of abstract ideas. Accordingly, independent claim 1 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
a graphics processor comprising: a system interface; a graphics processor core coupled with the system interface and memory access circuitry to process memory access messages received from the graphics processor core, the memory access circuitry configured, to process the memory access messages…the memory access messages
memory
submit a single memory access message including a merged operand and a byte-mask
These additional elements do not integrate the abstract idea into a practical application because (a and b) recite at a high-level of generality using generic computer components (i.e., processor including core and memory access circuitry to process memory access messages using a memory) to apply the exception such that it amounts to no more than mere instructions to implement the abstract idea using a computer as a tool or “apply it” (See MPEP 2106.05(f)); the limitations also recite at a high-level of generality a graphics processor to perform an abstract idea which can be viewed as an attempt to generally link the use of the judicial exception to a technological environment (i.e., graphics computing environment) (see MPEP 2106.05(h)). The additional element (c) does not provide does not integrate the abstract idea into a practical application because it recites insignificant extra-solution activity (e.g. data outputting) (MPEP 2106.05(g)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a and b) use mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)); and the additional elements use a particular type of computing environment (i.e. graphics computing) which ties the abstract idea to a particular field of use which cannot provide significantly more (see MPEP 2106.05(h)). The additional element (c) discloses data outputting which has been deemed by the courts to be well-understood, routine and conventional activities (See MPEP 2106.05 (d)) where the courts have recognized that receiving or transmitting data over a network (Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)). Furthermore, the claimed “circuitry to process memory access messages” does not provide significantly more as paragraph [0364] of the specification indicates the circuitry is conventional memory load/store logic, and thus the claimed circuitry to process memory access messages having addresses within a memory is considered well-understood, routine and conventional and does not provide significantly more than the abstract idea itself, taken alone nor in combination (MPEP 2106.05(d)). While, the claim also discloses a mask which is considered to be well-understood, routine and conventional associated with conventional GPU architectures (See pages 309-310 and Fig. 4.22 of “A Computer Architecture: A Quantitative Approach” which illustrates a GPU including masks and applicant’s own admission in background of disclosure [0002] indicating that shaders usually perform writes with a byte-mask) (see MPEP 2106.05(d)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
Claim 2, further recites details of the graphics processor core of claim 1 executing instructions, and thus describes generic computing components tied to a particular type of computing environment/field (See MPEP 2106.05(f and h)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 3, further recites details of the graphics processor core of claim 1 executing instructions (e.g., thus describes generic computing components tied to a particular type of computing environment/field (See MPEP 2106.05(f and h)) and submitting memory access messages to the circuitry of claim 1 (e.g. insignificant extra-solution activities which are considered well-understood, routine and conventional (See MPEP 2106.05(g and d)). (See MPEP 2106.05 (d)) where the courts have recognized that receiving or transmitting data over a network (Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 4 recites further abstract ideas such as “…merge the operands associated with the memory access messages includes to… determine that the first request is a request to perform a bitwise atomic operation to a first address in memory, the second request is a request to perform the bitwise atomic operation to a second address in memory, and the first address and the second address are to different 1-byte or 2-byte locations within the same 4-byte location in memory; and perform the bitwise atomic operation on an operand of the first request and the operand of the second request to generate a merged operand…determining a byte-mask” which encompass mental processes such as merging of operands based on a determination and performing bitwise atomic operations which can be considered mental processes and/or mathematical concepts (see claim 1 rejection). Thus, additional abstract ideas cannot integrate the abstract idea of claim 1 into a practical application nor provide significantly more than the abstract idea of claim 1. Further, claim 4 recites additional limitations which describe receiving requests and submitting a memory access message which are considered insignificant extra-solution activities which are considered well-understood, routine and conventional activities (See MPEP 2106.05(g and d)). (See MPEP 2106.05 (d)) where the courts have recognized that receiving or transmitting data over a network (Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 5, further recites details of requests in a graphics processor (e.g., thus describes requests (i.e. instructions) implemented on a particular type of processor and therefore describe mere instructions to implement an abstract idea on a computer (i.e. “apply it”) tied to a particular type of computing environment (MPEP 2106.05(f and h)). Furthermore, the claim discloses the requests are associated with masks which are considered to be well-understood, routine and conventional associated with conventional GPU architectures (See pages 309-310 and Fig. 4.22 of “A Computer Architecture: A Quantitative Approach” which illustrates a GPU including multiple masks associated with SIMD lanes processing requests of a multithreaded processor) (see MPEP 2106.05(d)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 6, further recites details of setting a mask to false (writing or setting a bit to “0”) and submitting a memory access message to a memory system which are considered insignificant extra-solution activities (i.e. data outputting or writing a memory) (MPEP 2106.05(g)). Additionally, data outputting or writing to memory has been deemed by the courts to be well-understood, routine and conventional activities (See MPEP 2106.05 (d)) where the courts have recognized that receiving or transmitting data over a network (Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)). Furthermore, the claim discloses masks which are considered to be well-understood, routine and conventional associated with conventional GPU architectures (See pages 309-310 and Fig. 4.22 of “A Computer Architecture: A Quantitative Approach” which illustrates a GPU including multiple masks associated with SIMD lanes processing requests of a multithreaded processor) (see MPEP 2106.05(d)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 7, further recites details of requests in a graphics processor (e.g., thus describes requests (i.e. instructions) implemented on a particular type of processor and therefore describe mere instructions to implement an abstract idea on a computer (i.e. “apply it”) tied to a particular type of computing environment (MPEP 2106.05(f and h)). Furthermore, the claim discloses the requests are associated with masks which are considered to be well-understood, routine and conventional associated with conventional GPU architectures (See pages 309-310, 313-314 and Fig. 4.22 of “A Computer Architecture: A Quantitative Approach” which illustrates a GPU including multiples masks associated with SIMD lanes processing requests of a multithreaded processor) (see MPEP 2106.05(d)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 8, further recites details of requests in a graphics processor (e.g., thus describes requests (i.e. instructions) implemented on a particular type of processor and therefore describe mere instructions to implement an abstract idea on a computer (i.e. “apply it”) tied to a particular type of computing environment (MPEP 2106.05(f and h)). Furthermore, the claim discloses the requests are associated with SIMD channels which are considered to be well-understood, routine and conventional associated with conventional GPU architectures (See pages 309-310, 313-314 and Fig. 4.22 of “A Computer Architecture: A Quantitative Approach” which illustrates a GPU including SIMD lanes (channels) processing requests of a multithreaded processor) (see MPEP 2106.05(d)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 9, further recites details of requests in a graphics processor (e.g., thus describes requests (i.e. instructions) implemented on a particular type of processor and therefore describe mere instructions to implement an abstract idea on a computer (i.e. “apply it”) tied to a particular type of computing environment (MPEP 2106.05(f and h)). Furthermore, the claim discloses the requests are associated with SIMT threads which are considered to be well-understood, routine and conventional associated with conventional GPU architectures (See pages 309-310, 313-314 and Fig. 4.22 of “A Computer Architecture: A Quantitative Approach” which illustrates a GPU including a SIMT processor) (see MPEP 2106.05(d)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 10 describes a further embellishment of the type of operation performed in the abstract idea of claim 1, thus claim 10 merely recites an abstract idea which cannot further integrate the abstract into a practical application nor provide significantly more than the abstract idea itself.
Claims 16-20 are similarly rejected and patent ineligible on the same basis as claims 1 and 3-6 above.
Regarding claim 11:
Subject Matter Eligibility Analysis Step 1:
Claim 11 recites “A method” and thus a process, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 11 recites “…determining that the first address and the second address are to different 1-byte or 2-byte locations within a same 4-byte location in memory; perform the bitwise atomic operation on an operand of the first request and the operand of the second request to generate a merged operand…determine a byte-mask corresponding to the first address and the second address”, that under its broadest reasonable interpretation encompasses mental processes and/or mathematical concepts. For example, determining that a first and a second address are to different 1-byte or 2-byte locations within a same 4-byte location involves an observation or evaluation that can be practically performed in the mind (or with the aid of pen and paper). While, performing a bitwise atomic operation to generate a merged operand and a byte mask as discussed in paragraphs [0372-0374] comprises performing a bitwise OR or AND operation on operand values which can be performed mentally (or with the aid or pen and paper); also, a bitwise OR or AND operation can be considered a Boolean operation which is a mathematical operation. (See MPEP 2106.04(a)(2) (I and III)). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind, or with the aid of pen and paper, but for the recitation of generic computer components, then it falls within the “Mental Processes” and/or “Mathematical Concepts” groupings of abstract ideas. Accordingly, independent claim 11 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 11 further recites additional elements of
a. receiving a first request to perform a bitwise atomic operation on an address… receiving a second request to perform the bitwise atomic operation on a second address
b. a memory of a graphics processor
c. submit a memory access message to the memory of the graphics processor, the memory access message including the merged operand… and submit a single memory access message to the memory of the graphics processor including the merged operand and the byte-mask.
These additional elements do not integrate the abstract idea into a practical application because (b) recites at a high-level of generality using generic computer components (i.e., processor and a memory) to apply the exception such that it amounts to no more than mere instructions to implement the abstract idea using a computer as a tool (See MPEP 2106.05(f)); the limitations also recite at a high-level of generality a graphics processor to perform an abstract idea which can be viewed as an attempt to generally link the use of the judicial exception to a technological environment (i.e., graphics computing environment) (see MPEP 2106.05(h)). The additional elements of (a and c) do not integrate the abstract idea into a practical application because they recite insignificant extra-solution activities of data gathering and outputting (MPEP 2106.05(g)). Therefore, claim 11 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 11 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (b) use mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)); and the additional elements use a particular type of computing environment (i.e. graphics computing)which ties the abstract idea to a particular field of use which cannot provide significantly more (see MPEP 2106.05(h)). Additionally, the additional limitations indicated as insignificant extra-solution activities have been deemed by the courts to be well-understood, routine and conventional activities (See MPEP 2106.05 (d)) where the courts have recognized that receiving or transmitting data over a network (Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).
Therefore, based on the discussion of the additional elements above, claim 11 is not patent eligible.
Claim 12, further recites determining a mask (i.e. setting or unsetting bits of a masks) and submitting a memory access message to a memory which are considered insignificant extra-solution activities (i.e. data outputting or writing a memory) (MPEP 2106.05(g)). Additionally, data outputting or writing to memory has been deemed by the courts to be well-understood, routine and conventional activities (See MPEP 2106.05 (d)) where the courts have recognized that receiving or transmitting data over a network (Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)). Furthermore, the claim discloses masks which are considered to be well-understood, routine and conventional associated with conventional GPU architectures (See pages 309-310 and Fig. 4.22 of “A Computer Architecture: A Quantitative Approach” which illustrates a GPU including multiples masks associated with SIMD lanes processing requests of a multithreaded processor) (see MPEP 2106.05(d)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 13 recites further abstract ideas such as “…wherein determining that the first address and the second address are within a same 4-byte location in memory includes: determining whether the first address and the second address map to a same cache line in a cache memory of the graphics processor; and determining whether a same-address atomic conflict is triggered for the first address and the second address, wherein triggering the same-address conflict indicates that the first address and the second address are within the same 4-byte location in memory” which encompass mental processes (see claim 1 rejection). Thus, additional abstract ideas cannot integrate the abstract idea of claim 1 into a practical application nor provide significantly more than the abstract idea of claim 1. Further, claim 13 recites additional limitations which describe additional generic computer components including a cache memory of the graphics processor which cannot integrate an abstract idea into a practical application provide significantly more (MPEP 2106.05(f)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claims 14-15, describe further embellishments of the memory locations used in the abstract idea of claim 11. Thus, the limitations merely indicate a particular data size implemented in generic computing component (i.e. a memory) (MPEP 2106.05 (f and h)). Thus, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-9 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 4, line 4 the limitation stating “the bitwise atomic operation” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is referring to a “bitwise atomic operation” claim 1, line 7 or a “bitwise atomic operation” claim 4, line 3?
In regards to claim 4, lines 6-7 and 10 there are two instances of the limitation stating “the bitwise atomic operation” which lack clarity. Each instance of the limitation lacks clarity because it is unclear if the limitation is referring to a “bitwise atomic operation” claim 1, line 7, a “bitwise atomic operation” of claim 4, line 3 or a “bitwise atomic operation” of claim 4, line 5?
In regards to claim 4, lines 14-15 limitations stating “the merged operand and the byte-mask” lack clarity. The limitations lack clarity because it is unclear if the limitations are referring to “a merged operand …a byte-mask” of claim 4, lines 11-12 or “a merged operand and a byte-mask” of claim 1, last line?
In regards to claim 6, last line the limitation stating “the merged operand” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is referring to “a merged operand” of claim 1, last line or “a merged operand” of claim 4, line 11?
In regards to claim 18, line 5 the limitation stating “the bitwise atomic operation” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is referring to a “bitwise atomic operation” claim 16, line 8 or a “bitwise atomic operation” claim 18, line 4?
In regards to claim 18, lines 7-8 and 11 there are two instances of the limitation stating “the bitwise atomic operation” which lack clarity. Each instant of the limitation lacks clarity because it is unclear if the limitation is referring to a “bitwise atomic operation” claim 16, line 8, a “bitwise atomic operation” of claim 18, line 4 or a “bitwise atomic operation” of claim 18, line 6?
In regards to claim 20, last line the limitation stating “the merged operand” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is referring to “a merged operand” of claim 18, last line or “a merged operand” of claim 16, line 10?
Claims 5-9 and 19-20 are dependent upon claims 4 and 18 above and therefore are similarly rejected for including the deficiencies of claims 4 and 18 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 10-11 and 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ray, USPAT No. 10,325,344, Hughes, PGPUB No. 2019/0205139 and further in view of Cypher, PGPUB No. 2012/0117323.
In regards to claim 1, Ray discloses A graphics processor (See Figs. 6-7: wherein a GPU (element 614) is disclosed) comprising: a system interface; a graphics processor core coupled with the system interface (See Figs. 2D-3B: wherein interconnect fabric or memory interconnect of a graphics multiprocessor are disclosed and are coupled to a graphics processor core. (see Column 23, lines 13-16 and Column 25, lines 35-43 indicate that details regarding Fig. 1-6 are not discussed again regarding Figs. 6-7 for brevity, thus indicating that the GPU of Figs. 6-7 can include cores and interconnects of GPU of Figs. 2D-3B)) and memory access circuitry to process memory access messages received from the graphics processor core (Column 28, lines 1-40: wherein circuitry (combination of memory controller and cache controller with atomic ALU (elements 905 and 909)) receives memory access messages from graphics shader execution unit of a graphics execution core (See Figs. 7, 9A| Figs. 2D, 3A and Fig. 23 which illustrate graphics processor with cores and shader cores)) the memory access circuitry configured, to process the memory access messages, to merge operands associated with the memory access messages to perform an arithmetic atomic operation, the memory access messages having addresses within a same location in memory. (Column 28, lines 3-67 and Column 29, lines 1-41: wherein circuitry (combination of memory controller and cache controller with atomic ALU (elements 905 and 909)) processes memory access messages by merging operands of atomic_inc messages to perform an atomic add operation. Wherein the one or more memory access messages have a same address location in memory (See Figs. 9A-9B)) and to submit a single memory access message including a merged operand (Column 3, lines 19-31, Column 28, lines 3-67 and Column 29, lines 1-41: wherein the circuitry submits a single atomic memory access message including a merged operand (See Figs. 9A-9B))
Ray does not explicitly disclose memory access circuitry configured, to merge operands associated with the memory access messages to perform a bitwise atomic operation, the memory access messages having addresses within a same 4-byte location in memory, and to submit a single memory access message including a merged operand and a byte-mask. Ray does disclose merging operands for atomic math/arithmetic operations targeting a same 4-byte address in a cache but does not explicitly disclose merging operands for bitwise atomic operations where the address targets a location including 4-bytes in a cache line.
Hughes discloses circuitry configured, to merge operands associated with the memory access requests to perform a bitwise atomic operation ([0057, 0100 and 0133-0135]: wherein optimization circuitry merges operands associated with atomic operation requests of logical (bitwise) operations (See Fig. 3 and 4E)) the memory access requests having addresses within a same 4-byte location in memory, and to submit a single memory access request including a merged operand ([0099-0100 and 0120]: wherein the atomic operation requests have a same address to a 4-byte location in a cache line. And the operands are merged to submit a single request including the merged operand to a cache control circuit (Figs. 4E))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the atomic operation of Ray to be a bitwise atomic operation as disclosed in Hughes. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (merging operands for a specific type of arithmetic atomic operation such as a bitwise atomic operation as disclosed in Hughes) for another (merging operands for arithmetic atomic operations as disclosed in Ray) to obtain predictable results (merging operands to perform bitwise atomic operations) (MPEP 2143, Example B).
It would have also been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the merging of atomic operations in Ray to merge atomic operations based on addresses mapping to a same 4-byte cache line location in cache memory as taught in Hughes. It would have been obvious because it would have been the simple substitution of one known element (merging operands which target a same 4-byte cache line element in a cache location as disclosed in Hughes) for another (merging operands which target a same cache address as disclosed in Ray) to obtain predictable results (merging operands of atomic operations which target a same 4-byte cache line element located at a cache line address) for the benefit of added flexibility. (MPEP 2143, Example B). It would have been further obvious to one of ordinary skill in the art because it would improve efficiency and cost of executing atomic operations (Hughes [0101 and 0106]).
The combination of Ray and Hughes does not disclose circuitry configured, to merge operands to perform memory access operations, the memory access operations having addresses within a same 4-byte location in memory, and to submit a single memory access operation including a merged operand and a byte-mask.
Cypher discloses circuitry configured, to merge operands to perform memory access operations, the memory access operations having addresses within a same 4-byte location in memory ([0032, 0049 and 0057-0058]: wherein circuitry can merge operands for store operations having addresses with a same 32-bit data word (e.g. 4-byte) using a byte-mask) and to submit a single memory access operation including a merged operand and a byte-mask. ([0057-0058 and 0061-0062]: wherein a single store operation is submitted that includes the merged operand and an updated byte-mask)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the memory access messages, including the merged operands, of Ray and Hughes to include a byte-mask as the merged memory operations of Cypher. It would have been obvious to one of ordinary skill in the art because using a byte-mask can allow writes to finer granularities of the cache line (e.g. individual byte control which allows 1-byte writes) which can provide added flexibility and reduced power consumption. In addition, using a byte-mask to merge memory operation operands can allow reduced bandwidth (Cypher [0058]).
Claim 16 is the system corresponding to the graphics processor of claim 1 above, and is similarly rejected on the same basis as claim 1 above. (Note: Claim 16 includes additional limitations stating “a system comprising a memory device” which are taught by Fig. 7 of Ray illustrating a system comprising a memory device (element 730))
In regards to claim 2, the combination of Ray, Hughes and Cypher discloses The graphics processor as in claim 1 (see rejection of claim 1 above) wherein the graphics processor core includes execution resources configured to execute an instruction. (Ray: Figs. 2D-3B: wherein graphics core includes execution resources configured to execute instructions (Column 11, lines 25-41 and Column 12, lines 23-28))
In regards to claim 3, the combination of Ray, Hughes and Cypher discloses The graphics processor as in claim 2 (see rejection of claim 2 above) wherein graphics processor core, in response to execution of the instruction by the execution resources, is configured to submit the memory access messages to the memory access circuitry. (Ray: Figs. 2D-3B and 9A: wherein graphics core includes execution resources configured to execute instructions. Wherein graphics processor core includes a shader execution unit that submits the one or more memory access messages to the circuitry (combination of memory controller and cache controller with atomic ALU (elements 905 and 909)), responsive to instruction execution. (Column 11, lines 25-41 and Column 12, lines 23-28) (Note: see Column 23, lines 13-16 and Column 25, lines 35-43 indicate that details regarding Fig. 1-6 are not discussed again regarding Figs. 6-7 for brevity, thus indicating that the GPU of Figs. 6-7 and Figs. 9A-C include GPU details discussed in Figs. 2D-3B))
Claim 17 is the system corresponding to the graphics processor of claim 3 above, and is similarly rejected on the same basis as claim 3 above.
In regards to claim 4, the combination of Ray, Hughes and Cypher discloses The graphics processor as in claim 3 (see rejection of claim 3 above) wherein to merge the operands associated with the one or more memory access messages (Ray: Column 28, lines 3-67 and Column 29, lines 1-41: wherein circuitry (combination of memory controller and cache controller with atomic ALU (elements 905 and 909)) processes memory access messages by merging operands of atomic_inc messages to perform an atomic add operation. Wherein the one or more memory access messages have a same address targeting a same 32-bit array in memory (See Figs. 9A-9B)) includes to: receive a first request to perform a bitwise atomic operation (Hughes [0057, 0089 and 0100]: wherein a first RAO request (element 412) is received and it can specify an atomic logical operation as described in [0133-0135]) (See Figs. 4B and 4E)) receive a second request to perform the bitwise atomic operation (Hughes [0057, 0089 and 0100]: wherein a second RAO request (element 442) is received and it can specify an atomic logical operation as described in [0133-0135]) (See Figs. 4B and 4E))
determine that the first request is a request to perform a bitwise atomic operation to a first address in memory, the second request is a request to perform the bitwise atomic operation to a second address in memory (Hughes [0057, 0089, 0100 and Fig. 4B/4E]: wherein it is determined that the first and second requests are requests to perform logical atomic operations to a first and second address which is the same address)and the first address and the second address are to locations within the same 4-byte location in memory (Hughes [0057, 0088, 0089, 0100 and Fig. 4B/4E]) and perform the bitwise atomic operation on an operand of the first request and the operand of the second request to generate a merged operand (Hughes [0057 and 0100]: wherein the bitwise logical operation is performed on the operand data of the requests to generate a merged operand) determine a byte-mask corresponding to the first address and the second address (Cypher [0057-0058 and 0061-0062] and Fig. 2) and submit a single memory access message including the merged operand and the byte-mask. (Ray: Column 3, lines 19-31, Column 28, lines 3-67 and Column 29, lines 1-41: wherein the circuitry submits a single atomic memory access message including a merged operand (See Figs. 9A-9B)) | Hughes [0099-0100 and 0120]: wherein the atomic operation requests have a same address to a 4-byte location in a cache line. And the operands are merged to submit a single request including the merged operand to a cache control circuit (Figs. 4E)) |Cypher [0057-0058 and 0061-0062]: wherein a single store operation is submitted that includes the merged operand and an updated byte-mask)
The combination of Ray, Hughes and Cypher thus far does not explicitly disclose the first address and the second address are to different 1-byte or 2-byte locations within the same 4-byte location in memory. Hughes does disclose merging atomic operations targeting a same address of a 4-byte element, and additionally discloses addresses of atomic operations can be used to target any size byte location in a cache line. However, Hughes does not explicitly indicate the addresses are to different 1-byte or 2-byte locations in the same 4-byte location.
Cypher discloses the first address and the second address are to different 1-byte or 2-byte locations within the same 4-byte location in memory ([0028, 0032, 0049, 0057-0058]: wherein store operation addresses target different bytes 1 or 2 bytes within a 32-bit data word)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the addresses of the atomic operations of Hughes within a 4-byte memory location to target different 1-byte or 2-byte memory locations as the memory operations of Cypher. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using memory access addresses to target 1-byte or 2-byte locations within a 4-byte memory location as taught in Cypher) for another (using memory access addresses to target 4-byte locations in memory as taught in Hughes) to obtain predictable results (using atomic operation addresses to target 1-byte or 2-byte locations in 4-byte memory locations) (MPEP 2143, Example B). Furthermore, it would have been obvious because changes in data size have been deemed obvious by the courts (MPEP 2144.04(IV)(A) (In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claim 18 is the system corresponding to the graphics processor of claim 4 above, and is similarly rejected on the same basis as claim 4 above.
Claim 11 is the method corresponding to the graphics processor of claim 4 above and is similarly rejected on the same basis as claim 4 above.
In regards to claim 10, the combination of Ray, Hughes and Cypher discloses The graphics processor as in claim 1 (see rejection of claim 1 above) wherein the bitwise atomic operation is a bitwise atomic OR operation or a bitwise atomic AND operation. (Hughes [0057 and 0133-0134]: wherein atomic bitwise OR and AND operation is disclosed)
In regards to claim 13, the combination of Ray, Hughes and Cypher discloses The method as in claim 11 (see rejection of claim 11 above) wherein determining that the first address and the second address are within a same 4-byte location in memory includes: determining whether the first address and the second address map to a same cache line in a cache memory of the graphics processor (Hughes [0099-0105]: wherein it is determined if remote atomic operations include first and second addresses mapping to a same cache line “g” of a cache memory of a graphics processor (see [0234] for discussion of graphics processor and Figs. 4E-F)) and determining whether a same-address atomic conflict is triggered for the first address and the second address, wherein triggering the same-address conflict indicates that the first address and the second address are within the same 4-byte location in memory. (Hughes [0099-0105]: wherein it is determined if the addresses conflict on a same 4-byte location based on the offsets of the atomic operations specifying the same 4-byte location in the cache line (See Figs. 4E-F))
In regards to claim 14, the combination of Ray, Hughes and Cypher discloses The method as in claim 11 (see rejection of claim 11 above) wherein the first address and the second address are addresses to 1-byte locations within the 4-byte location in memory (Cypher [0028, 0032, 0049, 0057-0058]: wherein store operation addresses target different bytes 1 or 2 bytes within a 32-bit data word)
In regards to claim 15, the combination of Ray, Hughes and Cypher discloses The method as in claim 11 (see rejection of claim 11 above) wherein the first address and the second address are addresses to 2-byte locations within the 4-byte location in memory (Cypher [0028, 0032, 0049, 0057-0058]: wherein store operation addresses target different bytes 1 or 2 bytes within a 32-bit data word)
Claim(s) 5-6, 8-9, 12 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ray, USPAT No. 10,325,344, Hughes, PGPUB No. 2019/0205139 Cypher, PGPUB No. 2012/0117323 and further in view of Elliot, PGPUB No. 2017/0003972.
In regards to claim 5, the combination of Ray, Hughes and Cypher discloses The graphics processor as in claim 4 (see rejection of claim 4 above).
The combination of Ray, Hughes and Cypher does not disclose wherein the first request is associated with a first channel mask and the second request is associated with a second channel mask.
Elliot discloses wherein the first request is associated with a first channel mask and the second request is associated with a second channel mask. ([0176]: wherein a first request (instruction) associated with a first thread is associated with a first execution lane (channel) mask and a second request (instruction) associated with a second thread is associated with a second execution lane (channel) mask (See Figs. 7a-7c and 9))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify SIMD atomic message requests as taught by the combination of Ray and Hughes to use lane masking as disclosed in Elliot. It would have been obvious to one of ordinary skill in the art because masking off lanes which would otherwise perform redundant operation can be used to reduce power consumption in a processor; in addition, it can help avoid threads deadlocking (Elliot [0184-0185]).
Claim 19 is the system corresponding to the graphics processor of claim 5 above, and is similarly rejected on the same basis as claim 5 above.
In regards to claim 6, the combination of Ray, Hughes, Cypher and Elliot discloses The graphics processor as in claim 5 (see rejection of claim 5 above) wherein the memory access circuitry is configured to set the second channel mask to false and submit a memory access message to a memory system of the graphics processor having the first channel mask and the merged operand. (Elliot [0176-0179]: wherein the second channel masks are masked off (set to false or 0) and an atomic message is sent to a shared memory of the graphics processor having the first channel mask indicating execution lane (element 110) is masked on. (Note: Ray: Figs. 9A-C and Hughes disclose issuing atomic messages to memory with merged operands and therefore the combination of references discloses the above limitation))
Claim 20 is the system corresponding to the graphics processor of claim 6 above, and is similarly rejected on the same basis as claim 6 above.
In regards to claim 8, the combination of Ray, Hughes, Cypher and Elliot discloses The graphics processor as in claim 5 (see rejection of claim 5 above) wherein the first request is associated with a first single instruction multiple data (SIMD) channel and the second request is associated with a second SIMD channel. (Ray: Column 25, lines 44-60: wherein SIMD slots (lanes) are disclosed |Elliot: See Figs. 3 and 7a-c)
In regards to claim 9, the combination of Ray, Hughes, Cypher and Elliot discloses The graphics processor as in claim 5 (see rejection of claim 5 above) wherein the first request is associated with a first single instruction multiple thread (SIMT) thread and the second request is associated with a second SIMT thread. (Ray: Column 8, lines 59-67 to Column 9, lines 1-25|Elliot [0040])
In regards to claim 12, the combination of Ray, Hughes and Cypher discloses The method as in claim 11 (see rejection of claim 11 above).
The combination of Ray, Hughes and Cypher does not disclose further comprising: determining a channel mask associated with the memory access message to submit to the memory of the graphics processor; and submitting the memory access message to the memory of the graphics processor using the determined channel mask.
Elliot discloses further comprising: determining a channel mask associated with the memory access message to submit to the memory of the graphics processor ([0148 and 0176-0179]: wherein a mask associated with an atomic message to submit to a shared memory of a graphics processor is disclosed) and submitting the memory access message to the memory of the graphics processor using the determined channel mask. ([0176-0179]: wherein the atomic message is sent to memory using channel mask indicating execution lane (110) is masked on and other lanes are masked off)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify SIMD atomic message requests as taught by the combination of Ray and Hughes to use lane masking as disclosed in Elliot. It would have been obvious to one of ordinary skill in the art because masking off lanes which would otherwise perform redundant operation can be used to reduce power consumption in a processor; in addition, it can help avoid threads deadlocking (Elliot [0184-0185]).
Allowable Subject Matter
Claim 7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) and 101, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments, see pages 10-11 of the remarks, filed on 12/8/2025, with respect to the 35 USC 103 rejection of claim 7 have been fully considered and are persuasive. Therefore, the previous 35 USC 103 rejection of claim 7 has been withdrawn.
Applicant’s arguments, see pages 9-10 of the remarks, filed on 12/8/2025 with respect to the rejection(s) of claim(s) 1, 11 and 16 under 35 USC 103 in view of Ray and Nystad have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ray, Hughes and Cypher.
Claims 2-6, 8-10, 12-15 and 17-20 are dependent upon one of claims 1, 11 and 16 and remain rejected at least based upon dependency.
Applicant's arguments of 35 USC 101 rejections have been fully considered but they are not persuasive. Therefore, the 35 USC 101 rejections have been maintained.
Applicant argues, the 35 USC 101 rejection on pages 8-9 of the remarks filed on 12/8/2025, in the substance that:
“That characterization ignores the claim as a whole and the technical context. The amended claims recite "memory access circuitry," which is specialized circuitry to facilitate load/store/cache operations in a graphics processor that intercepts concurrent memory access messages, detects that multiple request target bytes within the same 4-byte doubleword, merges their operands while preserving atomicity, and issues a single memory access message with appropriate channel masking. That coordinated, real-time manipulation of in-flight GPU memory messages across at cache-line/DW granularity is not something that can be practically performed in a human mind or with pen and paper.
Under MPEP § 2106.04(a)(2), a claim does not "recite a mental process" when it includes limitations that "cannot practically be performed in the human mind." The Federal Circuit has repeatedly recognized that where the human mind is not equipped to perform the recited operations, they are not mental processes. See SRI Int'l v. Cisco, 930 F.3d 1295, 1304 (Fed. Cir. 2019) (detecting suspicious network activity using network monitors is not mental), and SiRF Tech. v. ITC, 601 F.3d 1319 (Fed. Cir. 2010).
In particular, independent claims 1 and 16 recite a "graphics processor" with "memory access circuitry to process memory access messages ... configured ... to merge operands ... the ... messages having addresses within a same 4-byte location in memory." Claim 11 recites receiving plural requests (e.g., "receiving a first request...", "receiving a second request..." to "perform the bitwise atomic operation ... in the memory of the graphics processor"), determining same 4-byte location, performing the bitwise merge, and submitting a single memory access message to the graphics processor's memory. These limitations expressly anchor the operations to GPU load/store hardware and memory messaging; they are not mental calculations, and they cannot be "practically performed in the mind" as required by [MPEP § 2106.04(a)(2)].
Because the claims, properly read as a whole, recite hardware-specific operations that the human mind is not equipped to perform, the "mental process" label does not apply under Step 2A, Prong One. The § 101 rejection should be withdrawn for at least this reason.”
The examiner respectfully disagrees with the applicant’s assertions above because the claims disclose an abstract idea that can be considered a mental process and/or mathematical concept (Boolean operation) and circuitry which merely ties the abstract idea to a GPU computing environment which does not integrate the abstract idea into a practical application or provide significantly more than the abstract idea (See MPEP 2106.05(f), (g) and (h)). For example, the merging of operands in the claims is performed using Boolean operations (e.g., logical operations) which can be performed in the human mind or with the aid of pen and paper (see paragraphs [0372-0374])). Thus, the claims recite an abstract idea (mental process and/or mathematical concepts). The applicant appears to argue that limitations such as a graphics processor, memory access circuitry, requests and memory addresses anchor the operations to a GPU such that they cannot be practically performed in the mind. However, these additional limitations use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). At best the additional elements use a particular type of computing environment (i.e. graphics computing) which ties the abstract idea to a particular technological environment (MPEP 2106.05(h)). Furthermore, applicant discloses in paragraph [0364] that the memory access circuitry is conventional load/store logic to process memory access messages having addresses, and thus the circuitry is well-understood, conventional and routine and does not provide significantly more than the abstract idea itself, taken alone nor in combination (MPEP 2106.05(d)).
Further, the applicant argues that the claim does not recite a mental process when the limitation cannot be performed in the human mind, similar to “SRI Int'l v. Cisco, 930 F.3d 1295, 1304 (Fed. Cir. 2019) (detecting suspicious network activity using network monitors is not mental), and SiRF Tech. v. ITC, 601 F.3d 1319 (Fed. Cir. 2010))”. However, the examiner disagrees because those cases are stating that the claims include no “mental process” because the abstract idea of “detecting suspicious activity in a network” cannot be performed in the human mind. This is different from merging operands (e.g., data) using Boolean operations, which a human could do using pen and paper and additionally this encompasses mathematics as well (e.g. using a logical AND to combine two values can be performed using the human mind and with the aid of pen and paper). The claims of the instant application merely tie performing of the Boolean operations (math or mental process) to being performed on specific type of processor (e.g. a Graphics processor using conventional load/store logic). Thus, the claims recite an abstract idea and no additional elements which would integrate the abstract idea into a practical application nor provide significantly more.
Applicant's arguments of previous 35 USC 112 rejections have been fully considered but they are not persuasive. Therefore, the previous 35 USC 112 rejections have been maintained.
Applicant argues, the 35 USC 112 rejection on page 9 of the remarks filed on 12/8/2025, in the substance that:
“Claims 1-10 and 16-20 are rejected under 35 U.S.C.112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Applicant respectfully submits that this rejection is overcome by way of amendment to the claims.”
The examiner respectfully disagrees because the applicant did not amend similar claims 4 and 18 to correct the clarity issues regarding the limitations stating “the bitwise atomic operation”. The examiner suggests the applicant amend the claims to refer to different “respective bitwise atomic operations” or that each recitation refers to the same “bitwise atomic operation” as to overcome the previous 112 rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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