ETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Examiner's Amendment
An examiner' s amendment to the record appears below. Should the changes and/or additions be unacceptable to applicant, an amendment may be filed as provided by 37 CFR 1.312. To ensure consideration of such an amendment, it MUST be submitted no later than the payment of the issue fee.
The application has been amended as follows:
31. (Amended) The package of claim 16, wherein the first chiplet includes a first trench capacitor, a first memory, a first power management integrated circuit or a first voltage regulator, and wherein the second chiplet includes a second trench capacitor, a second memory, a second power management integrated circuit or a second voltage regulator.
35. (Amended) The package of claim 16, wherein the first integrated device is coupled to the first metallization portion through a first plurality of solder interconnects, and wherein the second integrated device is coupled to the first metallization portion through a second plurality of solder interconnects.
36. (Amended) The package of claim 17, wherein the first integrated device is coupled to the first metallization portion through a third plurality of solder interconnects, and wherein the second integrated device is coupled to the first metallization portion through a fourth plurality of solder interconnects.
37. (Amended) The package of claim 17, wherein the first integrated device is coupled to and touching the first metallization portion, and wherein the second integrated device is coupled to and touching the first metallization portion.
38. (Amended) The package of claim 1, wherein the first metallization portion comprises a first surface and second surface, wherein the second surface of the first metallization portion is opposite to the first surface of the first metallization portion, wherein the first integrated device coupled to and touching the first surface the first metallization portion, and wherein the second integrated device coupled to and touching the first surface of first metallization portion.
39. (Amended) The package of claim 38, wherein the second surface of the first metallization portion faces in a direction of the second metallization portion.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/28/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Status of Application
In response to Office action mailed 09/04/2025, Applicants amended claims 1, 10, 16, 17, cancelled claims 21-30 and added claims 31-40 in the response filed 01/28/2026.
Through an interview with Applicant, dated 04/13/2026, claims 31 and claims 36-40 have been amended.
Claim(s) 1-20 and 31-39 are pending examination.
Response to Arguments
Applicant's arguments, see 01/28/2026 Remarks, with respect to the rejection of claim(s) 1, 3-4, 13-15, 17 and 19 under 35 U.S.C. § 102 have been fully considered but they are not persuasive. Applicants argue the Chen reference does not teach nor suggest "a first integrated device coupled to and touching the first metallization portion; and a second integrated device coupled to and touching the first metallization portion". However, if you consider the first integrated device 106a as including a first plurality of die interconnects 106a-4 and the second integrated device 106a including a second plurality of die interconnects 106a-4 (as defined in claim 13); then Chen does teach the amended claim limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (PG Pub 2020/0043893; hereinafter Chen).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 13c provided above, Chen teaches a package (para [0009-0050]) comprising:
a first metallization portion (annotated “metal-1” in Fig. 13c above);
a first integrated device (106a,106a-4; annotated “device-1” in Fig. 13c above) coupled to and touching the first metallization portion 114b though 106a-4;
a second integrated device (106a,106a-4; annotated “device-2” in Fig. 13c above) coupled to and touching the first metallization portion through 106a-4;
a second metallization portion (annotated “metal-2” in Fig. 13c above) coupled to the first metallization portion through a first plurality of pillar interconnects 108;
a first chiplet 106b (“chiplet-1”) located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion (see Fig. 13c); and
a second chiplet 106b (“chiplet-2”) located between the first metallization portion and the second metallization portion (see Fig. 13c), wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion (see Fig. 13c).
Regarding claim 3, refer to the Examiner’s mark-up of Fig. 13c provided above, Chen teaches a first encapsulation layer 112’’ coupled to the first metallization portion 114b, the first integrated device (“device-1”) and the second integrated device (“device-2”) (see Fig. 13c).
Regarding claim 4, refer to the Examiner’s mark-up of Fig. 13c provided above, Chen teaches a second encapsulation layer 110’ coupled to the first metallization portion 114b, the second metallization portion (“metal-2”), the first chiplet 106b (“chiplet-1”) and the second chiplet 106b (“chiplet-2”), wherein the second encapsulation layer is located between the first metallization portion and the second metallization portion (see Fig. 13c).
Regarding claim 13, refer to the Examiner’s mark-up of Fig. 13c provided above, Chen teaches the first integrated device 106a (“device-1”) includes a first plurality of die interconnects 106a-4 (left) comprising a first minimum spacing (see Fig. 13c), and wherein the second integrated device 106a (“device-2”) includes a second plurality of die interconnects 106a-4 (right) comprising a second minimum spacing (see Fig. 13c).
Regarding claim 14, refer to the Examiner’s mark-up of Fig. 13c provided above, Chen teaches the first chiplet 106b (chiplet-1) includes a plurality of interconnects 106b-2 comprising a third minimum spacing (see Fig. 13c).
Regarding claim 15, refer to the Examiner’s mark-up of Fig. 13c provided above, Chen teaches the first integrated device 106a (“device-1”) includes a plurality of die interconnects 106a-4 (left) comprising a first minimum spacing (see Fig. 13c), and wherein the first chiplet 106b (chiplet-1) includes a plurality of interconnects 106b-2 comprising a second minimum spacing (see Fig. 13c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied to claim 1 above, and further in view of Wang et al. (PG Pub 2018/0366436; hereinafter Wang).
Regarding claim 2, refer to the Examiner’s mark-up of Fig. 13c provided above, Chen teaches the first metallization portion (“metal-1”) and the second metallization portion (“metal-2”), he does not teach “a bridge located between the first metallization portion and the second metallization portion. “
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In the same field of endeavor, refer to the Examiner’s modified mark-up of Fig. 1-14 provided above, Wang teaches a multi-chip module (para [0016-0083]) comprising: a bridge 103 (para [0019]) on a first metallization layer 145 (see Fig. 1-14).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the bridge between the first metallization portion and the second metallization portion of Chen, as taught by Wang, to bridge communication between the first and the second integrated devices.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied to claim 1 above, and further in view of Shao et al. (PG Pub 2018/0053730; hereinafter Shao).
Regarding claim 5, refer to the Examiner’s mark-up of Fig. 13c provided above, Chen teaches the first chiplet 106b (“chiplet-1”) and the second chiplet 106b (“chiplet-2”), he does not teach the functionality of the chiplet such that the first and second chiplet includes a trench capacitor, a memory, a power management integrated circuit or a voltage regulator. management integrated circuit or a second voltage regulator.
In the same field of endeavor, Shao teaches a semiconductor package (para [0027-0107]) comprising: a chiplet 102 (para [0027]); wherein the chiplet can be “a chip, an integrated circuit die, a semiconductor device, a memory chip, an interconnect structure, another type of device, or the like” (para [0027]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first and second chiplet of Chen, function as taught by Shao, for the purpose of creating a robust device.
Claim(s) 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen and Shao, as applied to claim 1 above, and further in view of Hung et al. (PG Pub 2018/0025992; hereinafter Hung).
Regarding claim 6, refer to the figures cited above, in the combination of Chen and Shao, Chen teaches the first integrated device and the second integrated device are coupled to the first metallization portion through a plurality of conductive posts 106a-4. He does not explicitly teach the plurality of conductive posts are solder interconnects.
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In the same field of endeavor, refer to Fig. 2a through Fig. 2I (primary emphasis on Fig. 2I provided above, Hung teaches a semiconductor package (para [0021-0030]) comprising: a plurality of conductive posts 36 (para [0023]) are solder interconnects (clm 12; “each of the plurality of conductive posts is a solder paste”).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the material composition of the plurality of conductive posts comprise solder, as taught by Hung, for the purpose of choosing a suitable and well-recognized conductive post material composition.
Regarding claim 7, refer to the Examiner’s mark-up of Fig. 13c provided above, Chen teaches the first chiplet and the second chiplet are coupled to the first metallization portion through a plurality of conductive posts 106b-2. He does not explicitly teach the plurality of conductive posts are solder interconnects.
In the same field of endeavor, refer to Fig. 2a through Fig. 2I (primary emphasis on Fig. 2I provided above, Hung teaches a semiconductor package (para [0021-0030]) comprising: a plurality of conductive posts 36 (para [0023]) are solder interconnects (clm 12; “each of the plurality of conductive posts is a solder paste”).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the material composition of the plurality of conductive posts comprise solder, as taught by Hung, for the purpose of choosing a suitable and well-recognized conductive post material composition.
Claim(s) 8-9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen and Hung, as applied to claim 7 above, and further in view of Wang et al. (PG Pub 2018/0366436; hereinafter Wang).
Regarding claim 8, refer to the cited figures above, in the combination of Chen and Hung, Chen teaches the first metallization portion (metal-1) and the second metallization portion (metal-2) Chen does not teach “a bridge located between the first metallization portion and the second metallization portion, wherein the bridge is coupled to the first metallization portion through a third plurality of solder interconnects.”
In the same field of endeavor, refer to the Examiner’s modified mark-up of Fig. 1-14 provided above, Wang teaches a multi-chip module (para [0016-0083]) comprising: a bridge 103 (para [0019]) on a first metallization layer 145 (see Fig. 1-14); wherein the bridge is coupled to the first metallization portion through a third plurality of solder interconnects (solder balls) (see Fig. 1-14 above).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the bridge between the first metallization portion and the second metallization portion of Chen, as taught by Wang, to bridge communication between the first and the second integrated devices.
Regarding claim 9, refer to the figures cited above, the combination of Chen, Hung and Wang teach a front side of the bridge 103-Wang (bottom) faces the first metallization portion 145 (top)-Wang, wherein a front side of the first chiplet (bottom of chiplet-1)-Chen faces the first metallization portion 114b-Chen, and wherein a front side of the second chiplet (bottom of chiplet-2)-Chen faces the first metallization portion (see Fig. 13c).
Allowable Subject Matter
Claims 10-12, 16-20 and 31-37 are allowed.
Claims 38-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 10, the first chiplet is coupled to the second metallization portion through a first plurality of solder interconnects, and wherein the second chiplet is coupled to the second metallization portion through a second plurality of solder interconnects. Claims 11-12 would be allowable, because they depend on allowable claim 10.
Claim 16 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 16, a first metallization portion; a first integrated device coupled to the first metallization portion, wherein the first integrated device includes a first plurality of transistors comprising a first minimum spacing; and a second integrated device coupled to the first metallization portion; a second metallization portion coupled to the first metallization portion through a first plurality of pillar interconnects ;a first chiplet located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion, wherein the first chiplet includes a second plurality of transistors comprising a second minimum spacing; and a second chiplet located between the first metallization portion and the second metallization portion, wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion. Claims 31-35 would be allowable, because they depend on allowable claim 16.
Claim 17 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 17, a package comprising: a first metallization portion; a first integrated device coupled to the first metallization portion; a second integrated device coupled to the first metallization portion; a second metallization portion coupled to the first metallization portion through a first plurality of pillar interconnects; a first chiplet located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion, and wherein the first chiplet is coupled to the second metallization portion through a first plurality of solder interconnects; and a second chiplet located between the first metallization portion and the second metallization portion, wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion, and wherein the second chiplet is coupled to the second metallization portion through a second plurality of solder interconnects. Claims 18-20 and 36-37 would be allowable, because they depend on allowable claim 17.
Claim 38 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 38, the first metallization portion comprises a first surface and second surface, wherein the second surface of the first metallization portion is opposite to the first surface of the first metallization portion, wherein the first integrated device coupled to and touching the first surface the first metallization portion, and wherein the second integrated device coupled to and touching the first surface of first metallization portion. Claim 39 would be allowable, because it depends on allowable claim 38.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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