DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 11/14/25
Applicant’s amendment to claims 1, 6, 7, 9, 14, 15 and 17 is acknowledged.
Claims 1-20 are pending and claims 4 and 17-20 are withdrawn.
Claims 1-3 and 5-16 are subject to examination at this time.
Response to Arguments
Applicant's arguments filed 11/14/25 have been fully considered but they are not persuasive.
Regarding claim 1:
Referring to Ewert’s fig. 12f, second conductive layer 108 is a discontinuous layer with discrete portions. Thus, there are portions of 108 disposed away from opening 111+107 that are insulated by layer 103 from the opening as annotated below.
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Regarding claim 9:
Referring to Ewert’s fig. 12f, even though the opening (111+107) forms a stepped structure, the sidewalls extend continuously in the vertical direction because there is no break/gap in the sidewalls of the opening. A continuous line is not required to be only a straight line. For example, a staircase is continuous even though it is a stepped structure.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, lines 13-14, it is unclear if “the solder mask” refers to the first solder mask or the second solder mask.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 5-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ewert et al., US Publication No. 2011/0189848 A1 in view of Baik et al, US Publication No. 2017/0117252 A1.
Ewert teaches:
1. A semiconductor device assembly comprising (see fig. 12 annotated below; also see figs. 10-11 and fig. 15):
a semiconductor die (e.g. see flip chip formed above bumps 100 in fig. 11; see flip chip at para. [0118] – [0121]);
a substrate (105/110/108) (e.g. see circuit board at para. [0046];) coupled to the semiconductor die, the substrate including:
a primary conductive layer (110 bottom) including a first surface (e.g. bottom surface) of the substrate;
….
a secondary conductive layer (108) including a second surface (e.g. top surface) of the substrate;
a second solder mask layer (103) coupled to the second surface; and
an inner conductive layer (110 middle) positioned between the primary conductive layer (110 bottom) and the secondary conductive layer (108),
wherein the inner conductive layer (110 middle) includes a bond pad (110 directly below 100) positioned at an end of an opening (111+107) that extends from the second solder mask layer (103) through the secondary conductive layer (108) to the bond pad (110 directly below 100) of the inner conductive layer (110 middle),
wherein the opening (111+107) includes sidewalls extending form the bond pad (110 directly below 100) to an outer surface of the solder mask (103), and wherein a conductive material (e.g. Second conductive layer 108 is a discontinuous layer with discrete portions. Thus, there are portions of 108 disposed away from opening 111+107 that are insulated by layer 103 from the opening.) in the second conductive layer (108) is insulated from the sidewalls of the openings; and
a solder ball (100) attached to the bond pad. See Ewert at para. [0001] – [0157], figs. 1-15.
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Regarding claim 1:
Ewert does not expressly teach a first solder mask layer coupled to the first surface.
Ewert teaches the substrate is a circuit board at para. [0046].
In an analogous art, Baik teaches (see fig. 1A) a first solder mask layer (40) coupled to a first surface (e.g. bottom surface) of a circuit board (1). See Baik at para. [0058], also see para. [0102] – [0103], fig. 2A.
Ewert further teaches:
2. The semiconductor device assembly of claim 1, wherein the substrate (105/110/108) further includes:
a first insulating layer (105) between the primary conductive layer (110 bottom) and the inner conductive layer (110 middle); and
a second insulating layer (105) between the secondary conductive layer (108) and the inner conductive layer (110 middle), fig. 12.
3. The semiconductor device assembly of claim 1, wherein the semiconductor die (e.g. flip chip) is coupled to the substrate by the solder ball (100), para. [0118] – [0121], figs. 11-12.
Regarding claim 5:
In the embodiment in fig. 12, Ewert does not teach a second inner conductive layer or a second bond pad.
However, it would have been obvious to one of ordinary skill in the art to form a second inner conductive layer and a second bond pad because Ewert teaches these elements in the embodiment in fig. 15.
Thus, one of ordinary skill in the art modifying Ewert’s fig. 12 with the elements of a second inner conductive layer and a second bond pad as taught in in fig. 15 would arrive at the claimed limitations.
5. The semiconductor device assembly of claim 1, wherein the inner conductive layer (110 middle of fig. 12) is a first inner conductive layer, the semiconductor device assembly further comprising:
a second inner conductive layer (114 along 112 in fig. 15) positioned between the primary conductive layer (110 bottom of fig. 12; also corresponds to bottom 110 of fig. 15) and the first inner conductive layer (110 middle of fig. 12),
wherein the second inner conductive layer (114 along 112 in fig. 15) includes a second bond pad (114 along 112 directly below 113 in fig. 15) that is configured to receive a second external connection (107 in fig. 15) through a second opening that extends from the second solder mask layer (103) through the secondary conductive (108) and the first inner conductive layer (110 middle of fig. 12) to the second bond pad. (Also see the 35 USC 112 rejection above.)
Regarding claim 6:
Ewert further teaches:
6. The semiconductor device assembly of claim 1, wherein the sidewalls of the opening (111+107) comprise a prepreg material (e.g. The substrate (105/110/108) can comprise a fiber-reinforced organic material or a glass fiber composite at para. [0046]. These materials suggest prepreg material.)
Furthermore, it would have been obvious to one having ordinary skill in the art to form sidewalls of the opening to comprise a prepreg material, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Ewert further teaches:
7. The semiconductor device assembly of claim 6, wherein the secondary conductive layer (108) includes the prepreg material (e.g. The substrate 105/110/108 can comprise a fiber-reinforced organic material or a glass fiber composite at para. [0046]. These materials suggest prepreg material.) between the conductive material and the openings (111+107) (e.g. Layer 105 is disposed between 108 and opening portion 111 in fig. 12.)
8. The semiconductor device assembly of claim 1, wherein the opening is one of an array of a plurality of openings (111+107), and wherein the solder ball is one of a plurality of solder balls (100) that comprise a ball grid array (BGA) (e.g. see “grid of contacts” at para. [0003] and solder balls at para. [0121])
Regarding claims 9-10:
Ewert and Baik teach the limitations as applied to claim 1 above.
Ewert further teaches the added limitation:
wherein the opening (111+1-7) includes sidewalls extending continuously in a vertical direction between the bond pad (110 directly below 100) and an outer surface of the second solder mask layer (103), fig. 12.
Regarding claim 11:
In the embodiment in fig. 12, Ewert does not teach a second bond pad.
However, it would have been obvious to one of ordinary skill in the art to form a second bond pad because Ewert teaches in an embodiment in fig. 15 with a plurality of bond pads.
11. The semiconductor package substrate of claim 9, (see fig. 15) wherein the bond pad (110 left) is a first bond pad, the substrate further comprising: a second bond pad (110 right) positioned on (e.g. on the bottom of) the secondary layer (108).
Regarding claims 12-13:
Ewert and Baik teach the limitations as applied to claim 5 above.
Regarding claim 14:
Ewert teaches the limitations as applied to claim 6 above.
Ewert further teaches:
15. The semiconductor package substrate of claim 9, wherein the secondary layer (108) includes a conductive portion that is exposed in one of the sidewalls of the opening (111+107), fig. 12.
Regarding claim 16:
Ewert further teaches:
16. The semiconductor package substrate of claim 9, wherein the opening has a width of approximately 300 μm (e.g. Ewert teaches in fig. 3 the via 104 can have a width of 200 microns at para. [0108]. The bottom of opening 111+107 shares a same width as the top of the via 104. Thus, the opening can have a width of 200 microns.)
Ewert does not expressly teach a width of approximately 300 μm.
However, absent any disclosure by the Applicant a width of approximately 300 μm critical or provides for unexpected results, such width can be considered within the skill level of one of ordinary skill in the art or by the guidance provided by Ewert. See MPEP § 2144.05, Obviousness of Ranges:
“Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical.” (Emphasis added.)
In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)…Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions. (Emphasis added.)
Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent").
[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Ewert with the teachings of Baik because the solder resist can provide electrical insulation in a circuit board. See Baik’s at para. [0055].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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/Michele Fan/
Primary Examiner, Art Unit 2818
13 January 2026