DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election with traverse of Species 2 shown in Fig. 1B, Claims 1-8, 10-15, and 17-20 in the response to restriction requirements filed 11/17/25 is acknowledged. Traversal was based on a ground that there is no burden in examining all species (e.g., three species) together. The Examiner disagrees with the arguments, and grounds for established burden in examining three species together were clearly established by the Restriction Requirements mailed 09/18/25. These grounds include: different classification for Species 3 in comparison with Species 1 and 2, different field of search for all species, such as employing different quotes and using different electronic resources, checking for various non-prior arts issues. At the same time, as the Restriction Requirements stated, when the species chosen for examination is allowed, non-examined species would be considered for rejoinder, and they will be rejoined with the examined species if they contain all limitations of an allowable generic claim of the examined species.
Status of Claims
Claims 9 and 16 are withdrawn from further consideration as being drawn to a nonelected invention.
Claims 1-8, 10-15, and 17-20 are examined on merits herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first interconnect feature extending from the lower etch stop layer to the upper etch stop layer, and a vertical stack of a second interconnect feature and a third interconnect feature extending from the lower etch stop layer to the upper etch stop layer”, as Claim 14 recites, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Specification is objected to because of the following informality:
Paragraph 0104 of a published application US 2024/00719913 states that interconnect features extend between two etch stop layer. The recitation is unclear since extension of interconnect features between two adjacent (in a vertical direction) electrically insulating etch stop layers means that these interconnect features have no electrical connection with interconnect features disposed in a lower and in upper layers. Please, note that a main reason of this objection is Claim 14 that repeats the recitation of paragraph 0104.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 14-15 and 17-18 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 14: Claim 14 recites: “a first interconnect feature extending from the lower etch stop layer to the upper etch stop layer; and a vertical stack of a second interconnect feature and a third interconnect feature extending from the lower etch stop layer to the upper etch stop layer”, and a same disposition of interconnect features is repeated again with additional details.
The recitation is unclear, since the claimed disposition of interconnect features in a layer disposed between two adjacent and electrically insulating etch stop layers prevents electrical connection between the interconnect features in this layer with interconnect features located in a lower layer and in an upper layer.
Appropriate correction is required to clarify the claimed language.
For this Office Action, based at least on figures of the application, the cited limitation of Claim 14 was interpreted as: “a first interconnect feature extending from and/or through the lower etch stop layer to the upper etch stop layer; and a vertical stack of a second interconnect feature and a third interconnect feature extending from and/or through the lower etch stop layer to the upper etch stop layer”. Further limitations of Claim 14 related to etch stop layers and interconnects were interpreted in a similar way.
In re Claims 15 and 17-18: Claims 15 and 17-18 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 14.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yen et al. (US 2015/0364371).
In re Claim 1, Yen teaches an integrated circuit structure, comprising (Fig. 12; see also Figs. 1-11 for understanding a structure of Fig. 12):
a first interconnect layer – with gates 26 and being an interconnect layer with respect to source and drain regions 24 (paragraph 0014) - including a first interconnect feature and a second interconnect feature 42A right and 42 left, accordingly, (paragraph 0015); and
a second interconnect layer – with dielectrics 46 and 58 (at least when they comprise a same dielectric material, paragraph 0031) - above the first interconnect layer, the second interconnect layer including
a third interconnect feature 64B, a fourth interconnect feature 52A, and a fifth interconnection feature 64C,
the third interconnect feature 64B extending from an upper surface of the first interconnect feature 42A right to an upper surface of the second interconnect layer,
the fourth interconnect feature 52A extending from an upper surface of the second interconnect feature 42A left to below the upper surface of the second interconnect layer, and
the fifth interconnect feature 64C extending from an upper surface of the fourth interconnect feature 52A to the upper surface of the second interconnect layer.
In re Claim 11, Yen teaches the integrated circuit structure of Claim 1, wherein (Fig. 12) a vertical height of the third interconnect feature 64B is within 1 nanometer of a sum of vertical heights of the fourth 52A and fifth interconnect features 64C: Yen does not teach any difference in a vertical height of the third interconnect feature and a sum of vertical heights of the fourth 52A and fifth 54C interconnect features, meaning compliance with the limitation: “within 1 nanometer”.
In re Claim 12, Yen teaches the integrated circuit structure of Claim 1, wherein (Fig. 12)
at least a section of the upper surface of the first interconnect feature 42A right is within a first horizontal plane (inherently), wherein
at least a section of the upper surface of the second interconnect feature 42A left is within a second horizontal plane (inherently), and wherein
the first and second horizontal planes are vertically separated by at most 1 nm: Yen does not teach any vertical separation between upper surfaces of the first and second interconnect features, meaning compliance with limitation: “the first and second horizontal planes are vertically separated by at most 1 nm”, since the separation in the Yen structure is equal to zero.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as Claims 14 and 18 are understood, Claims 1, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hotta et al. (US 2007/0020829) in view of Chen et al. (US 2021/0391255).
In re Claim 1, Hotta teaches an integrated circuit structure, comprising (Fig. 12; see also Figs. 1-11 for some numbers):
a first interconnect layer – with dielectric 17 (paragraph 0061) - including a first interconnect feature 19-right and a second interconnect feature 19-center (see Fig. 2 showing number 19, paragraph 0058); and
a second interconnect layer – with dielectric 23 (paragraph 0064) above the first interconnect layer, the second interconnect layer including
a third interconnect feature - a via portion of 33-right (paragraph 0072), a fourth interconnect feature – a via portion of 33-left, and a fifth interconnection feature – a line portion of 33-left, the third interconnect feature extending from an upper surface of the first interconnect feature 19-right to below the upper surface of the second interconnect layer (with a six interconnect feature – being a line of 33-right -extending from a top of the third interconnect feature to the upper surface of the second interconnect layer),
the fourth interconnect feature extending from an upper surface of the second interconnect feature 19-center to below the upper surface of the second interconnect layer being separated from the upper surface of the second interconnect layer with a line portion, and
the fifth interconnect feature extending from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer.
Hotta does not teach the third interconnect feature extending to an upper surface of the second interconnect.
Chen teaches (Fig. 9, paragraph 0043) an interconnect feature 905B extending from an upper surface of a lower-level interconnect 810 to an upper surface of interconnect 900, wherein the interconnect 900 also includes a stack of two features 905A, a lower part of which being a via portion and an upper part being a line portion.
Hotta and Chen teach analogous arts directed to a multilevel interconnect, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Hotta structure in view of the Chen structure, since they are from the same field of endeavor, and Chen created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Hotta structure by substituting its stack of the third and sixth interconnect features with a single third interconnect feature – similar to feature 905B of Chen - extending from the first interconnect feature to the upper surface of the second interconnect layer, if such interconnect feature is preferred for the manufacturer:
See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 14, Hotta teaches an integrated circuit structure, comprising (Fig. 14; see also Figs. 2-13 for some numbers):
an upper etch stop layer 24/34 (paragraph 0073) and a lower etch stop layer 18/21/22 (paragraphs 0061, 0064), without any intervening etch stop layer between the upper and lower etch stop layers, each of the upper and lower etch stop layers comprising corresponding dielectric materials;
a first interconnect feature – as a via of a right interconnect 33 (paragraph 0072) extending from the lower etch stop layer to below the upper etch stop layer and being separated from the upper etch stop layer with a line of the right interconnect 33 creating the stack with the first interconnect feature; and
a vertical stack of a second interconnect feature – as a via of a left interconnect 33, and a third interconnect feature – as a line of the left interconnect 33 - extending from the lower etch stop layer to the upper etch stop layer, such that (i) the second interconnect feature extends from the lower etch stop layer, (ii) the third interconnect feature extends from the upper etch stop layer, and (iii) an upper surface of the second interconnect feature and a lower surface of the third interconnect feature makes contact at a plane between the upper and lower etch stop layers.
Hotta does not teach that the first interconnect feature extending to the upper etch stop layer. However, Hotta teaches that the upper etch stop layer is disposed over an insulating layer 23 (paragraph 0064) incorporating the vertical stack with the line of the vertical stack reaching the top of the insulating layer 23.
Chen teaches (Fig. 9, paragraph 0043) an interconnect feature 905B extending from an upper surface of a lower-level interconnect 810 to an upper surface of interconnect 900, wherein the interconnect 900 also includes a stack of two features 905A, a lower part of which being a via portion and an upper part being a line portion.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Hotta structure by substituting its stack of the via and line of the right interconnect feature 33 with a single first interconnect feature – similar to feature 905B of Chen - extending from the lower etch stop layer to the upper etch stop layer (based on the disposition of the right interconnect 33 of Hotta), if such interconnect feature is preferred for the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 18, Hotta/Chen teaches the integrated circuit structure of Claim 14 as cited above, with the first interconnect feature created per Chen.
Since Hotta/Chen does not teach that the first and the stack of the second and third interconnect features are extended to a different top level, it would have been obvious for one of ordinary skill in the art before filing the invention that a vertical height of the first interconnect feature is within 1 nanometer of a vertical height of the vertical stack of the second and third interconnect features.
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Hotta/Chen in view of Chin et al (US 2023/00154792).
In re Claim 2, Hotta/Chen teaches the integrated circuit structure of Claim 1 as cited above.
Hotta further teaches (Fig. 12; see also Figs. 8-11 for a better understanding and as showing numbers of some elements) that the fourth interconnect feature comprises (i) conductive fill material – such as copper (paragraph 0072), (ii) a first section of a layer comprising conductive material on sidewalls of the conductive fill material – such as barrier of TiN (paragraph 0072 with a thickness of about 50 nm), and (iii) a second section of the layer comprising conductive material on a bottom surface of the conductive fill material – as another part of barrier TiN (paragraph 0072).
Hotta/Chen does not teach that a thickness of the first section of the layer is at least 10% more than a thickness of the second section of the layer.
Chin teaches (Fig. 9) a barrier layer comprised sublayers 901 and 903 on sidewall of an interconnect feature filled with copper 248 and a barrier layer comprised only 903 on a bottom of the interconnect feature. Chin identifies 901 as a barrier and 903 as a liner, but teaches (paragraph 0023) that liners and barriers comprised same materials (including TiN), teaches that a thickness of a barrier on the sidewall is about 2 nm (paragraph 0111) and teaches that a ratio of thickness of a barrier and a liner is in a range from 0.5 to 4.0 (paragraph 0054). When a thickness of layer 901 is chosen to be 2 nm and a thickness of layer 901 is chosen to be 4 time less (e.g., 0.5 nm), a thickness of layer 901 would be at least 10% more than a thickness of layer 903. Chin further teaches (paragraph 0052) that the thickness of 2 nm of a barrier is sufficient for precenting copper diffusion from the interconnect feature 248.
Hotta/Chen and Chin teach analogous arts directed to interconnect comprised a barrier layer surrounded a fill material, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Hotta/Chen circuit in view of the Chin circuit, since they are from the same field of endeavor, and Chin created a circuit that successfully operates.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Hotta circuit by substituting its thick barrier layer of the fourth interconnect features with a thinner barrier layer of Chin being at least 10% thicker on the sides than on the bottom, when it is desirable to reduce amount of barrier material used. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 3, Hotta/Chen teaches the integrated circuit structure of Claim 1 as cited above.
Hotta further teaches (Fig. 12; see also Figs. 8-11 for a better understanding and as showing numbers of some elements) that the fourth interconnect feature comprises (i) conductive fill material – such as copper (not shown by number, but described as being surrounded by barrier TiN layer, paragraph 0072), (ii) a first section of a layer comprising conductive material on sidewalls of the conductive fill material – such as barrier of TiN (paragraph 0072 with a thickness of about 50 nm), and (iii) a second section of the layer comprising conductive material on a bottom surface of the conductive fill material – as another part of barrier TiN (paragraph 0072).
Hotta/Chen does not teach that a thickness of the first section of the layer is at least 1 nm more than a thickness of the second section of the layer.
Chin teaches (Fig. 9) a barrier layer comprised sublayers 901 and 903 on sidewall of an interconnect feature filled with copper 248 and a barrier layer comprised only 903 on a bottom of the interconnect feature. Chin identifies 901 as a barrier and 903 as a liner, but teaches (paragraph 0023) that liners and barriers comprised same materials (including TiN), teaches that a thickness of a barrier on the sidewall is about 2 nm (paragraph 0111) and teaches that a ratio of thickness of a barrier and a liner is in a range from 0.5 to 4.0 (paragraph 0054). When a thickness of layer 901 is chosen to be 2 nm and a thickness of layer 901 is chosen to be 4 time less (e.g., 0.5 nm), a thickness of layer 901 would be at least 1 nm more than a thickness of layer 903. Chin further teaches (paragraph 0052) that the thickness of 2 nm of a barrier is sufficient for precenting copper diffusion from the interconnect feature 248.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Hotta/Chen circuit of Claim 1 by substituting its thick barrier layer of the fourth interconnect features with a thinner barrier layer of Chin being at least 1 nm thicker on the sides than on the bottom, when it is desirable to reduce amount of barrier material used. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 4, Hotta/Chen/Chin teaches the integrated circuit structure of Claim 3 as cited above, wherein, as it is clear from Claim 3 and Fig. 12 of Hotta, the second section of the layer is between (i) the conductive fill material of the fourth interconnect feature (being a via of interconnect 33) and (ii) the second interconnect feature – 19 center.
In re Claim 5, Hotta/Chen/Chin teaches the integrated circuit structure of Claim 3 as cited above with Chin teaching the barrier layer of different thicknesses. Although Chin teaches (Fig. 9), wherein the first section 901 (barrier) of the layer and the second section 903 (liner) of the layer comprised different materials, Chin also teaches (paragraph 0023) that barriers and liners are chosen from a same range of materials.
It would have been obvious for one of ordinary skill in the art before filing the application to create the barrier sublayers from a same material, when it is desirable to limit a number of barrier materials in the circuit.
In re Claim 6, Hotta/Chen/Chin teaches the integrated circuit structure of Claim 3 as cited above.
Hotta and Chin teach that the layer is a barrier layer (as shown for Claim 3), which comprises one or more of cobalt, nickel, ruthenium, molybdenum, manganese, titanium, tungsten, or tantalum – as shown for Claim 3, it comprises Ti (per Hotta and Chin), while Chin also teaches Ru and Co (paragraph 0023) for a barrier layer, and wherein the conductive fill material comprises one or more of copper, ruthenium, molybdenum, tungsten, aluminum, tin, indium, antimony, or bismuth – it was shown for Claim 3, that the fill material comprises copper.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hotta/Chen/Chin in view of Lee et al. (US 2020/0098685).
In re Claim 7, Hotta/Chen/Chin teaches the integrated circuit structure of Claim 3 as cited above and wherein the layer is a first layer.
Hotta/Chen/Chin does not teach that the fourth interconnect feature further comprises a second layer comprising conductive material on an upper surface of the conductive fill material, the second layer at least in part between the conductive fill material and the fifth interconnect feature, and wherein the second layer has a thickness of at least 2 nanometers.
Lee teaches (Fig. 2C, paragraph 0027) a second interconnect layer 48 incorporating a fourth interconnect feature 82 and a fifth interconnect feature 92 disposed on the fourth interconnect feature 82, wherein the fourth interconnect feature 82 comprises a first layer – as a part of a barrier layer 106 disposed on sidewalls - and also comprises a second layer - as a part of the barrier layer 106 disposed on the conductive fill material 108, where a thickness of the second layer is less than 50 nm (paragraph 0037), e.g., being at least 2 nm.
Hotta/Chen/Chin and Lee teach analogous arts directed to interconnect comprised a plurality of lines and vias surrounded by a barrier layer, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Hotta/Chen/Chin circuit in view of the Lee circuit, since they are from the same field of endeavor, and Lee created a circuit that successfully operates.
Considering that structures in which metal vias and metal lines created in a stack and being separated by a barrier layer are known in the art (see, for example, Nguyen, US 2006/0180930), it would have been obvious for one of ordinary skill in the art before filing the application to modify the Hotta/Chen/Chin structure of Claim 3 by substituting the fourth interconnect feature not comprising a second layer with a fourth interconnect feature comprising a second – barrier – layer on the conductive fill layer (as shown in Lee) and having a thickness of more than 2 nm, if such fourth interconnect feature if such fourth interconnect feature is preferred for the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 8, Hotta/Chen/Chin/Lee teaches the integrated circuit structure of Claim 7 as cited above, wherein, as is clear from Claim 7, the second layer, being a barrier layer, is also a capping layer disposed on the upper surface of the conductive fill material.
Lee further teaches that a barrier layer can be a cobalt layer (paragraph 0035), in line with various other metals and metal nitrides.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Hotta/Chen/Chin/Lee structure of Claim 7 by creating at least the second layer from cobalt, per Lee, if such material is preferred by the manufacturer for the top barrier layer. In accordance with MPEP 2144.07 Art Recognized Suitability for an Intended Purpose, the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hotta/Chen in view of Lin et al (US 2021/0343588).
In re Claim 10, Hotta/Chen teaches the integrated circuit structure of Claim 1 as cited above.
Hotta also shows (Fig. 12; see also Figs. 2-11 for some numbers) that a horizontal width of the second interconnect feature – 19-center - is greater than a horizontal width of the first interconnect feature – 19-right, but does not teach that a difference is at least 2 nanometers. It would have been for one of ordinary skill in the art before filing the application to understand that the width of the second interconnect should be at least twice greater than the width of the first interconnect feature since the second interconnect feature is disposed on and electrically connected to two lower disposed vias 15, while the first interconnect feature is disposed on and electrically connected to one via 15. However, Hotta does not teach widths of his first and second interconnect features, both being metal lines.
Lin teaches (paragraph 0037) that a width of conductive lines is in a range from 40 nm to 100 nm.
Hotta/Chen and Lin teach analogous arts directed to integrated circuit comprised conductive lines and vias, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Hotta/Chen device in view of the Lin device, since they are from the same field of endeavor, and Lin created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Hotta/Chen device of Claim 1 by creating its metal lines with a width chosen from the range taught by Lin, in order to enable such parameter of the structure as conductive line width. Where the width of 40 nm is chosen for the first interconnect feature and width of 80 nm is chosen for the second conductive feature (based on the consideration above), it would have been obvious for one of ordinary skill in the art before filing the application that a horizontal width of the second interconnect feature is at least 2 nm greater than a horizontal width of the first interconnect feature.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chen.
In re Claim 1, Lee teaches an integrated circuit structure, comprising (Fig. 1):
a first interconnect layer 76 including a first interconnect feature 70 and a second interconnect feature 72 (paragraphs 27-28); and
a second interconnect layer 86/96 (paragraph 0028) above the first interconnect layer 76, the second interconnect layer including
a third interconnect feature 80, a fourth interconnect feature 82, and a fifth interconnection feature 92 (paragraph 0028),
the third interconnect feature extending from an upper surface of the first interconnect feature 70 to an intermediate part of the second interconnect layer 86/96,
the fourth interconnect feature 82 extending from an upper surface of the second interconnect feature 72 to below the upper surface of the second interconnect layer, and
the fifth interconnect feature 92 extending from an upper surface of the fourth interconnect feature 70 to the upper surface of the second interconnect layer 86/96.
Lee does not teach that the third interconnect feature extends to an upper surface of the second interconnect layer, since the third interconnect feature is a line created in a stack with via 90 (being a sixth interconnect feature), where the via is connected the upper surface of the second interconnect layer.
Chen teaches (Fig. 9, paragraph 0043) an interconnect feature extending from an upper surface of a lower-level interconnect 810 to an upper surface of interconnect 900, wherein the interconnect 900 also includes a stack 905A of two features.
Lee and Chen teach analogous arts directed to a multilevel interconnect, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Lee structure in view of the Chen structure, since they are from the same field of endeavor, and Chen created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Lee structure by substituting its stack of the third and sixth interconnect features with a single third interconnect feature – similar to feature 905B of Chen - extending from the first interconnect feature to the upper surface of the second interconnect layer, if such interconnect feature is preferred for the manufacturer:
See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee/Chen in view of Lin.
In re Claim 13, Lee/Chen teaches the integrated circuit structure of Claim 1 as cited above.
Lee further teaches (Fig. 1) that the upper surface of the fourth interconnect feature 82 is wider than a bottom surface of the fifth interconnect feature 92, but does not teach that the difference is at least 1 nm, since Lee does not teach width of his interconnect features. However, in the Lee structure, the fourth interconnect feature is a via and fifth – is a line.
Lin teaches that a width of conductive vias can be chosen from a range from 8 nm to 20 nm (paragraph 0027) and a width of conductive lines can be chosen from a range from 14 nm to 30 nm (paragraph 0037).
Lee/Chen and Lin teach analogous arts directed to integrated circuit comprised conductive lines and vias, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Lee/Chen circuit in view of the Lin circuit, since they are from the same field of endeavor, and Lin created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Lee/Chen structure of Claim 1 by creating its conductive lines with a width of 30 nm and its vias with a width of 20 nm (per Lin), in order to enable such parameters as width of conductive lines and vias. It would have been obvious for one of ordinary skill in the art before filing the application that with the above modification, the upper surface of the fourth interconnect feature would be at least 1 nm wider than a bottom surface of the fifth interconnect feature.
As far as the claim is understood, Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hotta/Chen in view of Seidel et al. (US 2010/0219534).
In re Claim 15, Hotta/Chen teaches the integrated circuit structure of Claim 14 as cited above, but does not teach that the first interconnect feature and the vertical stack are laterally separated by at most 400 nanometers.
Seidel teaches (Claim 9) that a spacing between two neighboring metal regions is 100 nm or less.
Hotta/Chen and Seidel teach analogous arts directed to a structure comprised a plurality of metal regions, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Hotta/Chen structure in view of the Seidel structure, since they are from the same field of endeavor, and Seidel created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Hotta/Chen circuit by separating the first interconnect feature and the vertical stack by a distance of 100 nm or less (which would comply with the claim limitation) in order to enable such parameter for the circuit as spacing between its metallic components.
As far as the claim is understood, Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee.
In re Claim 14, Lee teaches an integrated circuit structure, comprising (Fig. 1):
an upper etch stop layer 56 and a lower etch stop layer 54 (paragraph 0026), without any intervening etch stop layer between the upper and lower etch stop layers, each of the upper and lower etch stop layers comprising corresponding dielectric materials (paragraph 0026);
a first interconnect feature 70 (paragraph 0072) extending from the lower etch stop layer 54 to below the upper etch stop layer; and
a second interconnect feature 72 (paragraph 0072) extending from the lower etch stop layer 54 to the upper etch stop layer 56, such that (i) the second interconnect feature 72 extends from the lower etch stop layer,
For interlayer layer 76, Lee does not teach a vertical stack of a second interconnect feature and a third interconnect feature created such that (ii) the third interconnect feature extends from the upper etch stop layer, and (iii) an upper surface of the second interconnect feature and a lower surface of the third interconnect feature makes contact at a plane between the upper and lower etch stop layers.
However, for interlayer 86/96, Lee teaches an interconnect feature being a stack of features being a metal line 80 and a via 90 (paragraph 0027) extending from a bottom to a top of the interlayer, where via 90 extends from a top of the interlayer and line 80 extends from a bottom of the interlayer such that these features make contact at a plane between the top and bottom of the interlayer.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Lee structure by substituting its second interconnect with a stack of a second interconnect – similar to line 80 – and a via – similar to via 90, the stack extending between the (and through) the upper and lower etch stop layers and making a contact between these etch stop layers, wherein it is desirable creating the second interconnect as a stack of a metal line and a via: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
As far as the claim is understood, Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lin.
In re Claim 17, Lee teaches the integrated circuit structure of Claim 14, wherein a horizontal width of the second interconnect feature is greater than a horizontal width of the first interconnect feature (as is clear from Claim 14 and Figs. 1 and 2C).
Lee does not teach that a horizontal width of the second interconnect feature is greater than a horizontal width of the first interconnect feature by at least 2 nm.
Lin teaches (paragraphs 0027 and 0037) that a width of a conductive line is chosen from a range from 14 nm to 30 nm and a width of a conductive via is chosen from a range from 8 nm to 20 nm.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Lee structure of Claim 14 by creating its conductive lines with a width of 30 nm and its vias with a width of 20 nm (per Lin), in order to enable such parameters as width of conductive lines and vias. It would have been obvious for one of ordinary skill in the art before filing the application that with the above modification, the upper surface of the fourth interconnect feature would be at least 2 nm wider than a bottom surface of the fifth interconnect feature.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chin.
In re Claim 19, Lee teaches an integrated circuit structure, comprising (Figs. 1 and 2C):
a vertical stack of a lower interconnect feature 64, an intermediate interconnect feature 72, and an upper interconnect feature 82 (paragraphs 0026-0028), wherein
a lower surface of the intermediate interconnect feature 72 is on an upper surface of the lower interconnect feature 64, and a lower surface of the upper interconnect feature 82 is on an upper surface of the intermediate interconnect feature 72, wherein
the intermediate interconnect feature 72 comprises (i) conductive fill material 104 (paragraph 0034), (ii) a first section of a layer 102 comprising conductive material on side surfaces of the conductive fill material 104, and (iii) a second section of a second layer 102 comprising conductive material on a bottom surface of the conductive fill material 104.
Lee does not teach that a thickness of the first section is at least 0.75 nm is greater than a thickness of the second section. However, Lee teaches that his first and second sections are sections of a barrier layer (paragraph 0034) having a thickness of 50 nm (paragraph 0035).
Chin teaches (Fig. 9) a barrier layer having different thicknesses on sidewalls and a bottom surrounding a conductive fill layer: in particular, Chin teaches that a sidewall a barrier layer comprises two sublayers 901 and 903, while only sublayer 903 is disposed on a bottom of an interconnect feature. Chin identifies 901 as a barrier and 903 as a liner, but teaches (paragraph 0023) that liners and barriers comprised same materials (including TiN), teaches that a thickness of a barrier on the sidewall is about 2 nm (paragraph 0111), which is sufficient for a barrier layer to prevent diffusion from a conductive fill material(paragraph 0052), and teaches that a ratio of thickness of a barrier and a liner is in a range from 0.5 to 4.0 (paragraph 0054). Since materials of first and second sublayers are the same, they can be viewed as a single layer of one material with a larger thickness is disposed on sidewalls and with a lower thickness is disposed on a bottom.
It would have further been obvious for one of ordinary skill in the art before filing the application to modify the Lee structure by creating the second section being twice thinner than the first section (per Chin), if such shape of the conductive material is desirable: In accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant. With this modification, it would have been obvious that the thickness of the first section of the layer would be at least 0.75 nm more than the thickness of the second section.
In re Claim 20, Lee/Chin teaches the integrated circuit structure of Claim 19 as cited above, wherein, as is clear from Claim 19, the layer is a barrier layer and the first section of the layer and the second section of the layer are elementally same.
Lee/Chin further teaches that:
the barrier layer comprises one or more of cobalt, nickel, ruthenium, molybdenum, manganese, titanium, tungsten, or tantalum – Lee teaches barrier layers comprising Ti, Ta, Co, Mn, W (paragraphs 0034-0035);
the conductive fill material comprises one or more of copper, ruthenium, molybdenum, tungsten, aluminum, tin, indium, antimony, or bismuth – Lee teaches the conducive fill material 108 being Cu, Al, In, Sn, Mo (paragraph 0036)
the integrated circuit structure further comprising (Lee, Fig. 1):
an upper etch stop layer 56 and a lower etch stop layer 54 (paragraph 0026), without any intervening etch stop layer therebetween, wherein
the intermediate interconnect feature 72 and the upper interconnect feature 82 extends at least in part between the upper and lower etch stop layers – 72 extends between the etch stop layers, while 82 does not, wherein
the lower interconnect feature 64 is below the lower etch stop layer 54.
Conclusion
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 11/23/25