DETAILED ACTION
This Office action responds to Applicant’s RCE arguments filed on 12/24/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 10/02/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/24/2025 has been entered.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-4, 10-14, 21-23, and 25.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 10-12 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over by Nayini (US 2021/0125952) in view of Kalandar (US 9721928).
Regarding claim 1, Nayini (see, e.g., Nayini: figs. 1-13) shows most aspects of the instant invention including a semiconductor device structure, comprising:
A substrate 166 including a signal pad 170 (see, e.g., Nayini: par. [0039]) and at least one first non-signal pad 180 (see, e.g., Nayini: par. [0040])
A semiconductor housing portion 110 including a signal pin 112 (see, e.g., Nayini: par. [0030]) and at least one first non-signal pin 114 (see, e.g., Nayini: par. [0031])
First bonding members 140/182 configured to bond the signal pad 170 and the signal pin 112, and to bond the first non-signal pad 180 and the first non-signal pin 114
wherein:
The first non-signal pad 180 and the first non-signal pin 114 each have an L-shape in a plan view (see, e.g., Nayini: fig. 2 and par. [0039])
Nayini, however, fails (see, e.g., Nayini: figs. 1-13) to specify that the first non-signal pin is connected to a ground or a power supply. Moreover, Nayini shows that the first non-signal pin that is connected by a solder bump to the first non-signal pad is a non-functional component. Kalandar, in a similar device to Nayini, teaches (see, e.g., Kalandar: fig. 1B) that a non-signal pin 115 is connected by a solder bump 104 to the non-signal pad 146, and that the non-signal pin is also connected to a ground or a power supply (see, e.g., Kalandar: col.5/II.61-67 – col.6/II.1-3). Kalandar further teaches that the non-signal pin is connected to a ground or power supply because as chip voltages drop and electrical current requirements become more stringent, it is sometimes more advantageous to distribute power and ground directly to the core of the die, e.g., using the flip-chip area array bumps (see, e.g., Kalandar: col.2/II.39-49). Kalandar also shows that these low-inductance, low-resistance power and ground paths can also reduce simultaneous switching noise and ground bounce (see, e.g., Kalandar: col.2/II.39-49). Kalandar further shows that, on especially sensitive signal paths, additional power and ground bumps can be used to surround a sensitive input/output (I/O) signal bump, thereby electrically shielding the latter from the noise induced by adjacent circuitry (see, e.g., Kalandar: col.2/II.39-49).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a non-signal pin of Kalandar connected to a ground or a power supply in the device of Nayini in order to distribute power and ground directly to the core of the die by using the flip-chip area array bumps, and also to reduce simultaneous switching noise and ground bounce.
Regarding claim 2, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows that the first non-signal pad 180 and the first non-signal pin 114 are located at one of four corner areas of an outer periphery of the semiconductor portion 110 in the plan view.
Regarding claim 3, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows that:
An area of the first non-signal pad 180 is larger than an area of the signal pad 170 in the plan view
An area of the first non-signal pin 114 is larger than an area of the signal pin 112 in the plan view
Regarding claim 4, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows that:
The signal pad 170 is located inside the semiconductor housing portion with respect to the first non-signal pad 180 in the plan view
The signal pin 112 is located inside the semiconductor housing portion with respect to the first non-signal pin 114 in the plan view
Regarding claim 10, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows that the substrate 166 includes a multilayer wiring substrate (see, e.g., Nayini: par. [0038]).
Regarding claim 11, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows that the signal pin 112 includes a signal terminal (see, e.g., Nayini: par. [0045]).
Regarding claim 12, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows that the signal pad 170 includes a signal terminal (see, e.g., Nayini: par. [0045]).
Regarding claim 25, Nayini (see, e.g., Nayini: figs. 1-13) shows most aspects of the instant invention including a semiconductor device structure, comprising:
A substrate 166 including a signal pad 170 (see, e.g., Nayini: par. [0039]) and at least one first non-signal pad 180 (see, e.g., Nayini: par. [0040])
A semiconductor housing portion 110 including a plurality of signal pins 112 (see, e.g., Nayini: par. [0030]) and at least one first non-signal pin 114 (see, e.g., Nayini: par. [0031])
First bonding members 140/182 configured to bond the signal pad 170 and the signal pin 112, and to bond the first non-signal pad 180 and the first non-signal pin 114
wherein:
The first non-signal pad 180 and the first non-signal pin 114 each have an L-shape in a plan view (see, e.g., Nayini: fig. 2 and par. [0039])
The plurality of signal pins 112 are located on a first region of the surface of the semiconductor housing portion 110 (see, e.g., Nayini: figs. 2 and 13)
The first non-signal pin 114 is located on a second region of the surface of the semiconductor housing portion 110 (see, e.g., Nayini: figs. 2 and 13)
The second region has the L-shape
The first region abuts an inner corner of the L-shaped second region (see, e.g., Nayini: figs. 2 and 13)
Nayini, however, fails (see, e.g., Nayini: figs. 1-13) to specify that the first non-signal pin is connected to a ground or a power supply. Moreover, Nayini shows that the first non-signal pin that is connected by a solder bump to the first non-signal pad is a non-functional component. Kalandar, in a similar device to Nayini, teaches (see, e.g., Kalandar: fig. 1B) that a non-signal pin 115 is connected by a solder bump 104 to the non-signal pad 146, and that the non-signal pin is also connected to a ground or a power supply (see, e.g., Kalandar: col.5/II.61-67 – col.6/II.1-3). Kalandar further teaches that the non-signal pin is connected to a ground or power supply because as chip voltages drop and electrical current requirements become more stringent, it is sometimes more advantageous to distribute power and ground directly to the core of the die, e.g., using the flip-chip area array bumps (see, e.g., Kalandar: col.2/II.39-49). Kalandar also shows that these low-inductance, low-resistance power and ground paths can also reduce simultaneous switching noise and ground bounce (see, e.g., Kalandar: col.2/II.39-49). Kalandar further shows that, on especially sensitive signal paths, additional power and ground bumps can be used to surround a sensitive input/output (I/O) signal bump, thereby electrically shielding the latter from the noise induced by adjacent circuitry (see, e.g., Kalandar: col.2/II.39-49).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a non-signal pin of Kalandar connected to a ground or a power supply in the device of Nayini in order to distribute power and ground directly to the core of the die by using the flip-chip area array bumps, and also to reduce simultaneous switching noise and ground bounce.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over by Nayini in view of Kalandar in further view of Karnezos (US 6373131).
Regarding claim 13, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows most aspects of the instant invention (see paragraph 6 above) including a semiconductor device structure that has that a signal pin 112.
Nayini in view of Kalandar, however, fails (see, e.g., Nayini: figs. 1-13) to show that the signal pin 112 has a circular shape in the plan view. Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) is silent about the shape of the signal pin 112, however, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows in fig.4 an elliptical shape of the signal pin 140. Karnezos, in a similar device to Nayini in view of Kalandar, teaches (see, e.g., Karnezos: fig. 3A-3B) that the shape of the signal pin 117 is circular (see, e.g., Karnezos: col.9/II.32-41).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the elliptical signal pin of Nayini in view of Kalandar or the circular signal pin of Karnezos because these were recognized in the semiconductor art for their use as signal pads, as taught by Nayini in view of Kalandar and by Karnezos, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over by Nayini in view of Kalandar in further view of Xu (US 2023/0137512).
Regarding claim 14, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows most aspects of the instant invention (see paragraph 6 above) including a semiconductor device structure that has a substrate 116 and a semiconductor chip housed in the semiconductor housing portion 110.
Nayini in view of Kalandar, however, fails (see, e.g., Nayini: figs. 1-13) to specify a controller mounted on the substrate 116 that is configured to control a semiconductor chip. Xu, in a similar device to Nayini in view of Kalandar, teaches (see, e.g., Xu: fig. 10) a controller 124 that is mounted on the substrate 100. Xu also teaches that the controller can be an ASIC for controlling the signals and data to and from the memories dies (see, e.g., Xu: par. [0041]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the controller of Xu in the device of Nayini in view of Kalandar in order to control the signals and data to and from the memories dies.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over by Nayini in view of Kalandar in further view of Ye (US 2020/0366091).
Regarding claim 21, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows most aspects of the instant invention (see paragraph 6 above) including a semiconductor device structure that has a semiconductor chip housed in the semiconductor housing portion 110.
Nayini in view of Kalandar, however, fails (see, e.g., Nayini: figs. 1-13) to specify that a power supply is outside of semiconductor housing portion 110. Ye, in a similar device to Nayini in view of Kalandar, teaches (see, e.g., Ye: fig. 7) a power supply 30/31 that is outside of semiconductor housing portion 1 (see, e.g., Ye: par. [0052]). Ye also shows that, in the spatial arrangement of a system of providing power to a chip on a mainboard, the number of the post-stage power supply modules 31 connected to the preceding-stage power supply module is increased, which can share the power of the chip 1, thus, the volumetric size of each of the post-stage power supply modules 31 can be reduced (see, e.g., Ye: par. [0052]). Since the sizes of the first post-stage power supply module 30 and the second post-stage power supply module 31 are reduced, the first post-stage power supply module 30 and the second post-stage power supply module 31 can utilize the area of the mainboard where the high speed signal lines 4 are distributed in high density, thereby they can be closer to the chip 1, and because of their small sizes, they can even be disposed between two adjacent wirings of the high speed signal lines 4 that are spread by an angle (see, e.g., Ye: par. [0052]). Since the path between each of the first post-stage power supply module 30 and the second post-stage power supply module 31 and the chip 1 becomes shorter, the transmission impedances decrease (see, e.g., Ye: par. [0052]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the power supply outside of the semiconductor housing portion of Ye in the device of Nayini in view of Kalandar in order to provide a better spatial arrangement of a system of providing power to a chip on a mainboard that can utilize the area of the mainboard where the high speed signal lines are distributed in high density, and also to decrease the transmission impedances.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over by Nayini in view of Kalandar in further view of Zhang (US 2021/0305184).
Regarding claim 22, Nayini in view of Kalandar (see, e.g., Nayini: figs. 1-13) shows most aspects of the instant invention (see paragraph 6 above) including a semiconductor device structure that has a semiconductor chip housed in the semiconductor housing portion 110 and a first non-signal pin 114.
Nayini in view of Kalandar, however, fails (see, e.g., Nayini: figs. 1-13) to specify that a first non-signal pin 114 is separated from an outer periphery of the semiconductor housing portion 110 in a plan view. Zhang, in a similar device to Nayini in view of Kalandar, teaches (see, e.g., Zhang: fig. 2) a first non-signal pin 121 separated from an outer periphery of the semiconductor housing portion 11 in a plan view (see, e.g., Zhang: par. [0033]). Zhang also shows that, based on the above structure, stress resistance (i.e., the ability to resist stress) of each pad 121 located in a different area of the substrate 11 can be strengthened, structural strength of the pad 121 and bonding strength of the pad 121 can be increased, such that the pad 12 can be prevent from being disconnected from the solder bumps 13 due to stress concentration in the edge area 111 caused by impacts, drops and the like during testing and using, and thus, the chip 1 can obtain better test results with increasing number of impact tests, thereby improving life of the chip 1, and the circuit board assembly and the electronic device including the chip 1 (see, e.g., Zhang: par. [0052]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first non-signal pin of Zhang separated from an outer periphery of the semiconductor housing portion in the device of Nayini in view of Kalandar in order to prevent the non-signal pins from being disconnected from the corresponding solder bumps due to stress concentration in the edge area caused by impacts, drops and the like during testing.
Regarding claim 23, Nayini in view of Kalandar in view of Zhang shows (see, e.g., Nayini: figs. 1-13) that the first non-signal pin 114 is closer to a corner of the outer periphery of the semiconductor housing 110 in the plan view then the signal pin 112.
Response to Arguments
Applicants’ arguments have been considered but are moot in view of the new grounds of rejection.
The applicants argue:
Nayini in view of Kalandar fails to anticipates or otherwise render obvious that “… the first non-signal pin is connected to a ground or a power supply …”, as recited in exemplary claims 1, and 25.
The examiner responds:
Applicant considers that Nayini in view of Kalandar fails to anticipates or otherwise render obvious that “… the first non-signal pin is connected to a ground or a power supply …” because persons with ordinary skills in the art would not be motivated to combine Nayini reference with Kalandar reference to reach the features recited in claim 1. Applicant considers that the element 114 of Nayini is formed for purposes of avoiding violating dicing rules and is thus electrically inactive, when the element 164 (or 104) of the instant application is formed to provide electrical connection.
Indeed, the element 114 of Nayini is electrically inactive and it is formed from a dummy solder structure as a metal pad during dicing (see, e.g., Nayini: par. [0027]). Nayini clearly shows (see, e.g., Nayini: fig. 7) that, after dicing, the element 114 has the structure of a pin. Moreover, Nayini shows that the element 114 is a mounting metal pin (see, e.g., Nayini: par. [0030]) that is part of a mounting structure comprising element 114 (metal pin), 182 (solder), and element 180 (metal pad). This particular mounting structure comprising element 114 (metal pin), 182 (solder), and element 180 (metal pad) has all the structure limitations of an electrical interconnect between two substrates, even if there is no electrical connection in this interconnect. In this context (a mounting interconnect between two substrates 110/166), one with ordinary skills in the art can bring the Kalandar reference, where it is clearly showed a mounting interconnect (between the substrate 110 and 140) that has an electrical connection 115/104/146.
Kalandar, in a similar device to Nayini, teaches (see, e.g., Kalandar: fig. 1B) that a non-signal pin 115 is connected by a solder bump 104 to the non-signal pad 146, and that the non-signal pin is also connected to a ground or a power supply (see, e.g., Kalandar: col.5/II.61-67 – col.6/II.1-3). Kalandar further teaches that the non-signal pin is connected to a ground or power supply because as chip voltages drop and electrical current requirements become more stringent, it is sometimes more advantageous to distribute power and ground directly to the core of the die, e.g., using the flip-chip area array bumps (see, e.g., Kalandar: col.2/II.39-49). Kalandar also shows that these low-inductance, low-resistance power and ground paths can also reduce simultaneous switching noise and ground bounce (see, e.g., Kalandar: col.2/II.39-49). Kalandar further shows that, on especially sensitive signal paths, additional power and ground bumps can be used to surround a sensitive input/output (I/O) signal bump, thereby electrically shielding the latter from the noise induced by adjacent circuitry (see, e.g., Kalandar: col.2/II.39-49).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a non-signal pin of Kalandar connected to a ground or a power supply in the device of Nayini in order to distribute power and ground directly to the core of the die by using the flip-chip area array bumps, and also to reduce simultaneous switching noise and ground bounce.
The applicants argue:
Nayini in view of Kalandar fails to anticipates or otherwise render obvious that “… the first non-signal pin is located on a second region of the surface of the semiconductor housing portion, the second region having the L-shape, the first region abutting an inner corner of the L-shaped second region."…”, as recited in exemplary claim 25.
The examiner responds:
In light of the new rejection, Nayini in view of Kalandar clearly shows that:
The plurality of signal pins 112 are located on a first region of the surface of the semiconductor housing portion 110 (see, e.g., Nayini: figs. 2 and 13)
The first non-signal pin 114 is located on a second region of the surface of the semiconductor housing portion 110 (see, e.g., Nayini: figs. 2 and 13)
The second region has the L-shape
The first region abuts an inner corner of the L-shaped second region (see, e.g., Nayini: figs. 2 and 13)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814