DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 12/22/2025, with respect to the rejections of claims 1-3, 5-8, and 10-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn
Applicant's arguments filed 12/22/2025 with respect to the rejections of claims 4 and 9 have been fully considered but they are not persuasive.
Applicant argues the Cheng does not teach “vias comprising a magnetic material”. The examiner agrees. The claims 4 and 9 relied upon Cheng in view of Liao and Bharath wherein Bharath teaches the magnetic material “Cobalt, zirconium and tantalum” Paragraph 0038 in “CZT” the same materials as disclosed within the specification [See MPEP 2112.01]. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Therefore, upon further consideration, a new ground(s) of rejection is made incorporating Bharath into the base claims, see rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being obvious over US 20230065446 A1 Cheng hereafter “Cheng” and in further view of US 20210336063 A1 Liao et al hereafter “Liao” and US 20200066830 A1 Bharath et al hereafter “Bharath”.
Claim 1 Cheng teaches an integrated circuit structure, comprising:
a front-side structure (the structure within the bounds of VEP2 fig. 40) comprising:
a device layer (a top portion of GAAP within the bounds of VEP2 fig. 40) having a plurality of nanowire-based transistors (sufficiently illustrated fig. 40 not labeled, “nanostructures” 22 labeled Fig. 39); and
a plurality of metallization layers (comprising IP, CP, TP, M1 fig. 40) above the nanowire-based transistors of the device layer [illustrated fig. 40], wherein one of the metallization layers includes one or more vias [ “inductor portion IP” meets the requirement of being magnetic (Paragraph 0120) under broadest reasonable interpretation Inductors are magnetic, fig. 40 further illustrates the Inductors of IP take the shape and/or form of one or more vias in the cross section of fig. 40]; and
a backside structure (Comprising at least M3, M4 and SP) below the nanowire-based transistors of the device layer,
the backside structure including metal lines [sufficiently illustrated within fig. 40 but not labeled, labeled and referred to at least 75 and/or 163 fig. 39].
Cheng does not explicitly teach the metal lines including a ground metal line nor the vias comprising the magnetic material.
Liao teaches a backside structure (150 fig. 22) including metal lines (comprising 154, 162, 164) that are grounded metal lines [Paragraph 0098 “The UBMs 162 and the external connectors 164 may also be referred to as backside input/output pads that may provide signal, reference voltage, supply voltage, and/or ground connections to the nano-FETs of the device layer 120” sufficiently discloses grounding as function that a metallization layer such as a under-bump metallization layer, and/or external connector and/or metal line (154 fig. 22) can provide].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the metal lines included in the backside structure Cheng teaches and modified it such that they include a ground metal line as Liao teaches such that “the backside structure including a ground metal line” to necessarily ground the device and/or set a reference voltage of the device to ground.
Bharath teaches an inductive layer (comprising 103 and/or 104 and/or 107) comprising one or more vias comprising the magnetic material (102a, met under MPEP 2112.01 the materials are the same as disclosed) comprising CZT [103 fig. 2A Paragraph 0038 “In some embodiments, magnetic core block 103 comprises cobalt-zirconium-tantalum alloy (e.g., CZT).].
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cheng in view of Liao in further view of Bharath and select a known material such as CZT such that the “via comprises magnetic material” as selection of a known material for its known material properties and/or suitability for its intended use (in this case magnetism) is prima facie type obviousness [see MPEP 2144.07], and/or to increase the inductance/magnetism of the via.
Claim 2 Cheng in view of Liao and Bharath teaches as shown above the integrated circuit structure of claim 1,
Wherein the one or more vias comprising the magnetic material is at least a 1 x 6 array of vias comprising the magnetic material [sufficiently illustrated fig. 40].
Cheng does not teach wherein the one or more vias comprising the magnetic material is a 2 x 5 array of vias comprising the magnetic material.
It would have been obvious to one of ordinary skill in the art to duplicate and/or rearrange the one or more vias comprising the magnetic material such that “the one or more vias comprising the magnetic material is a 2 x 5 array of vias comprising the magnetic material” as Duplication and/or rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 B. and/or C.].
Claim 3 Cheng in view of Liao and Bharath teaches as shown above the integrated circuit structure of claim 1, Wherein the one or more vias comprising the magnetic material is at least a 1 x 6 array of vias comprising the magnetic material [sufficiently illustrated fig. 40]
wherein the one or more vias comprising the magnetic material is a 4 x 10 array of vias comprising the magnetic material.
It would have been obvious to one of ordinary skill in the art to duplicate and/or rearrange the one or more vias comprising the magnetic material such that “the one or more vias comprising the magnetic material is a 4 x 10 array of vias comprising the magnetic material” as Duplication and/or rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 B. and/or C.].
Claim 4 Cheng in view of Liao and Bharath as shown above teaches the integrated circuit structure of claim 1, wherein the one or more vias comprising the magnetic material are included in an enclosure (layer IP forms part of an and enclosure under broadest reasonable interpretation enclosing a top portion of the device illustrated fig. 40) comprising Cobalt, Zirconium and Tantalum [met in view of Bharath as shown above, Paragraph 0038 “In some embodiments, magnetic core block 103 comprises cobalt-zirconium-tantalum alloy (e.g., CZT)]
Claim 5 Cheng in view of Liao and Bharath teaches the integrated circuit structure of claim 1, wherein the one or more vias comprising the magnetic material are included in a DC-DC convertor comprising the ground metal line [This limitation is met under MPEP 2112.01 the Prior art of Cheng in view of Liao is structurally identical and/or the same as what is claimed and/or disclosed thus the requirement to function as a DC-DC convertor with the ground metal line met, Examiners notes: Based on the disclosure the examiner has interpreted the required structure to form a DC-DC convertor as the one or more vias comprising the magnetic material and the ground metal line as embodied in fig. 4 of the instant application, should the applicant intended to claim and/or imply any additional structure that contributes to forming a DC-DC convertor the examiner recommends explicitly claiming that structure].
Claim 6 Cheng teaches an integrated circuit structure, comprising:
a front-side structure (the structure contained within the bounds of VEP2 fig. 40) comprising:
a device layer (comprising a top region of GAAP within the bounds of VEP2 fig. 40) having a plurality of fin-based transistors (illustrated fig. 40, not labeled, labeled as comprising at least 82, 22, 74, 200 fig. 39, sufficiently disclosed as being a fin based structure paragraph 0026 “he present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin-line FETs (FinFETs), or gate-all-around (GAA) devices” ); and
a plurality of metallization layers (Comprising at least M1, TP, CP, IP fig. 40) above the fin-based transistors of the device layer [sufficiently illustrated fig. 40], wherein one of the metallization layers includes one or more vias [“inductor portion IP” meets the requirement of being magnetic (Paragraph 0120) under broadest reasonable interpretation Inductors are magnetic, fig. 40 further illustrates the Inductors of IP take the shape and/or form of one or more vias in the cross section of fig. 40]; and
a backside structure (comprising M3, M4 and/or SP fig. 40) below the fin-based transistors of the device layer,
the backside structure including metal lines [sufficiently illustrated within fig. 40 but not labeled, labeled and referred to at least 75 and/or 163 fig. 39].
Cheng does not explicitly teach the metal lines including a ground metal line nor the vias comprising the magnetic material.
Liao teaches a backside structure (150 fig. 22) including metal lines (comprising 154, 162, 164) that are grounded metal lines [Paragraph 0098 “The UBMs 162 and the external connectors 164 may also be referred to as backside input/output pads that may provide signal, reference voltage, supply voltage, and/or ground connections to the nano-FETs of the device layer 120” sufficiently discloses grounding as function that a metallization layer such as a under-bump metallization layer, and/or external connector and/or metal line (154 fig. 22) can provide].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the metal lines included in the backside structure Cheng teaches and modified it such that they include a ground metal line as Liao teaches such that “the backside structure including a ground metal line” to necessarily ground the device and/or set a reference voltage of the device to ground.
Bharath teaches an inductive layer (comprising 103 and/or 104 and/or 107) comprising one or more vias comprising the magnetic material (102a, met under MPEP 2112.01 the materials are the same as disclosed) comprising CZT [103 fig. 2A Paragraph 0038 “In some embodiments, magnetic core block 103 comprises cobalt-zirconium-tantalum alloy (e.g., CZT).].
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cheng in view of Liao in further view of Bharath and select a known material such as CZT such that the “via comprises magnetic material” as selection of a known material for its known material properties and/or suitability for its intended use (in this case magnetism) is prima facie type obviousness [see MPEP 2144.07], and/or to increase the inductance/magnetism of the via.
Claim 7 Cheng in view of Liao and Bharath teaches as shown above the integrated circuit structure of claim 6, wherein the one or more vias comprising the magnetic material is a 1 x 6 array of vias comprising the magnetic material. [sufficiently illustrated fig. 40].
Cheng does not teach wherein the one or more vias comprising the magnetic material is a 2 x 5 array of vias comprising the magnetic material.
It would have been obvious to one of ordinary skill in the art to duplicate and/or rearrange the one or more vias comprising the magnetic material such that “the one or more vias comprising the magnetic material is a 2 x 5 array of vias comprising the magnetic material” as Duplication and/or rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 B. and/or C.].
Claim 8 Cheng in view of Liao and Bharath teaches as shown above the integrated circuit structure of claim 6, wherein the one or more vias comprising the magnetic material is a 1 x 6 array of vias comprising the magnetic material. [sufficiently illustrated fig. 40].
wherein the one or more vias comprising the magnetic material is a 4 x 10 array of vias comprising the magnetic material.
It would have been obvious to one of ordinary skill in the art to duplicate and/or rearrange the one or more vias comprising the magnetic material such that “the one or more vias comprising the magnetic material is a 4 x 10 array of vias comprising the magnetic material” as Duplication and/or rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 B. and/or C.].
Claim 9 Cheng in view of Liao and Bharath teaches as shown above the integrated circuit structure of claim 6, wherein the one or more vias comprising the magnetic material are included in an enclosure (layer IP forms part of an and enclosure under broadest reasonable interpretation enclosing a top portion of the device illustrated fig. 40) the enclosure comprising Cobalt, Zirconium and Tantalum [met in view of Bharath as shown above, Paragraph 0038 “In some embodiments, magnetic core block 103 comprises cobalt-zirconium-tantalum alloy (e.g., CZT)]
Claim 10 Cheng in view of Liao and Bharath teaches as shown above the integrated circuit structure of claim 6, wherein the one or more vias comprising the magnetic material are included in a DC-DC convertor comprising the ground metal line. [This limitation is met under MPEP 2112.01 the Prior art of Cheng in view of Liao is structurally identical and/or the same as what is claimed and/or disclosed thus the requirement to function as a DC-DC convertor with the ground metal line met, Examiners notes: Based on the disclosure the examiner has interpreted the required structure to form a DC-DC convertor as the one or more vias comprising the magnetic material and the ground metal line as embodied in fig. 4 of the instant application, should the applicant intended to claim and/or imply any additional structure that contributes to forming a DC-DC convertor the examiner recommends explicitly claiming that structure].
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20140092574 A1 Zillman et al hereafter “Zillman”, and further in view of Cheng and Liao and Bharat.
Claim 11 Zillman teaches a computing device (1000 fig. 8), comprising:
a board (1002 fig. 8); and a component [a plurality of components are sufficiently illustrated fig. 8] coupled to the board [sufficiently illustrated fig. 8].
Zillman does not teach the component including an integrated circuit structure, comprising: a front-side structure comprising: a device layer having a plurality of nanowire-based transistors; and a plurality of metallization layers above the nanowire-based transistors of the device layer, wherein one of the metallization layers includes one or more vias comprising a magnetic material; and a backside structure below the nanowire-based transistors of the device layer, the backside structure including a ground metal line.
Cheng teaches a component (illustrated fig. 40) including an integrated circuit structure [sufficiently disclosed as “integrated logic and passive device structure” Paragraph 0025], comprising:
a front-side structure (comprising the structure contained within the boundary of VEP2 fig. 40) comprising:
a device layer (comprising the top portion of GAAP contained within the boundary of VEP2 fig. 40) having a plurality of nanowire-based transistors (illustrated fig. 40 but not labeled, labeled within fig. 39 as comprising 22, 74, 82, and 200); and
a plurality of metallization layers (comprising M1, TP, CP, and/or IP fig. 40) above the nanowire-based transistors of the device layer, wherein one of the metallization layers includes one or more vias comprising the magnetic material [ “inductor portion IP” meets the requirement of being magnetic (Paragraph 0120) under broadest reasonable interpretation Inductors are magnetic, fig. 40 further illustrates the Inductors of IP take the shape and/or form of one or more vias in the cross section of fig. 40]; and
a backside structure (comprising M3, M4, and/or SP fig. 40) below the nanowire-based transistors of the device layer,
the backside structure including metal lines [sufficiently illustrated within fig. 40 but not labeled, labeled and referred to at least 75 and/or 163 fig. 39].
Cheng does not explicitly teach the metal lines including a ground metal line nor the vias comprising the magnetic material.
Liao teaches a backside structure (150 fig. 22) including metal lines (comprising 154, 162, 164) that are grounded metal lines [Paragraph 0098 “The UBMs 162 and the external connectors 164 may also be referred to as backside input/output pads that may provide signal, reference voltage, supply voltage, and/or ground connections to the nano-FETs of the device layer 120” sufficiently discloses grounding as function that a metallization layer such as a under-bump metallization layer, and/or external connector and/or metal line (154 fig. 22) can provide].
It would be obvious to one of ordinary skill in the art to include the device of Cheng teaches to one of the plurality of components coupled to the board (such as the RRAM and/or processor 1004, and/or communication chip 1006) Zillman teaches such that “the component including an integrated circuit structure, comprising: a front-side structure comprising: a device layer having a plurality of nanowire-based transistors; and a plurality of metallization layers above the nanowire-based transistors of the device layer, wherein one of the metallization layers includes one or more vias; and a backside structure below the nanowire-based transistors of the device layer, the backside structure including a ground metal line” to increase the transistor density and/or device density [Cheng paragraph 0025 “the present disclosure provides a novel integrated logic and passive device structure which is capable of increasing transistor density. Some embodiments of the present disclosure provides a method of stacking the passive device on the backside of the logic device to increase density. In the related art, the method of increasing density was largely directed towards arranging both the passive devices/components (e.g., resistor, capacitor, inductor, DRAM, RRAM, or the like) and the logic devices (e.g., integrated circuits) on the front side of a substrate”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the metal lines included in the backside structure Zillman in view of Cheng teaches and modified it such that they include a ground metal line as Liao teaches such that “the backside structure including a ground metal line” to necessarily ground the device and/or set a reference voltage of the device to ground.
Bharath teaches an inductive layer (comprising 103 and/or 104 and/or 107) comprising one or more vias comprising the magnetic material (102a, met under MPEP 2112.01 the materials are the same as disclosed) comprising CZT [103 fig. 2A Paragraph 0038 “In some embodiments, magnetic core block 103 comprises cobalt-zirconium-tantalum alloy (e.g., CZT).].
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Zillman in view of Cheng and Liao in further view of Bharath and select a known material such as CZT such that the “via comprises magnetic material” as selection of a known material for its known material properties and/or suitability for its intended use (in this case magnetism) is prima facie type obviousness [see MPEP 2144.07], and/or to increase the inductance/magnetism of the via.
Claim 12 Zillman in view of Cheng and Liao and Bharath teaches the computing device of claim 11, further comprising:
a memory coupled to the board (sufficiently disclosed at least DRAM fig. 8 Zillman).
Claim 13 Zillman in view of Cheng and Liao and Bharath teaches the computing device of claim 11, further comprising:
a communication chip coupled to the board (1006 fig. 8).
Claim 14 Zillman in view of Cheng and Liao and Bharath teaches as shown above the computing device of claim 11, wherein the component is a packaged integrated circuit die (disclosed in “the processor 1004 includes an integrated circuit die packaged within the processor 1004” Paragraph 0049 Zillman as shown above the processor would include the disclosed device of Cheng).
Claim 15 Zillman in view of Cheng and Liao and Bharath teaches as shown above the computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (as shown above the processor and/or communication would include the disclosed device of Cheng)).
Claim 16 Zillman teaches A computing device, comprising:
a board (1002 fig. 8); and
a component (DRAM, and/or 1004, and/or 1006 fig. 8) coupled to the board [sufficiently illustrated fig. 8].
Zillman does not teach the component including an integrated circuit structure, comprising:
a front-side structure comprising:
a device layer having a plurality of fin-based transistors; and
a plurality of metallization layers above the fin-based transistors of the device layer, wherein one of the metallization layers includes one or more vias comprising a magnetic material; and
a backside structure below the fin-based transistors of the device layer, the backside structure including a ground metal line.
Cheng teaches a component (3 fig. 40) including an integrated circuit structure [sufficently disclosed as integrated fig. 0025 “a novel integrated logic and passive device structure”], comprising:
a front-side structure (the structure contained within the boundary of VEP3 fig. 40) comprising:
a device layer (the upper portion of GAAP contained within the boundary of VEP3 fig. 40) having a plurality of fin-based transistors (illustrated but not labeled fig. 40, labeled as comprising 82, 74, 22, and 200 fig. 39 disclosed as being fin based transistors paragraph 0026 “FinFETs”); and
a plurality of metallization layers (comprising at least M1, TP, CP, and/or IP fig. 40) above the fin-based transistors of the device layer, wherein one of the metallization layers includes one or more vias [“inductor portion IP” meets the requirement of being magnetic (Paragraph 0120) under broadest reasonable interpretation Inductors are magnetic, fig. 40 further illustrates the Inductors of IP take the shape and/or form of one or more vias in the cross section of fig. 40]; and
a backside structure (comprising M3, M4 and/or SP fig. 40) below the fin-based transistors of the device layer,
the backside structure including metal lines [sufficiently illustrated within fig. 40 but not labeled, labeled and referred to at least 75 and/or 163 fig. 39].
Cheng does not explicitly teach the metal lines including a ground metal line nor the vias comprising the magnetic material.
Liao teaches a backside structure (150 fig. 22) including metal lines (comprising 154, 162, 164) that are grounded metal lines [Paragraph 0098 “The UBMs 162 and the external connectors 164 may also be referred to as backside input/output pads that may provide signal, reference voltage, supply voltage, and/or ground connections to the nano-FETs of the device layer 120” sufficiently discloses grounding as function that a metallization layer such as a under-bump metallization layer, and/or external connector and/or metal line (154 fig. 22) can provide].
It would be obvious to one of ordinary skill in the art to include the device of Cheng teaches to one of the plurality of components coupled to the board (such as the RRAM and/or processor 1004, and/or communication chip 1006) Zillman teaches such that “the component including an integrated circuit structure, comprising: a front-side structure comprising: a device layer having a plurality of fin-based transistors; and a plurality of metallization layers above the fin-based transistors of the device layer, wherein one of the metallization layers includes one or more vias; and a backside structure below the fin-based transistors of the device layer, the backside structure including a ground metal line” to increase the transistor density and/or device density [Cheng paragraph 0025 “the present disclosure provides a novel integrated logic and passive device structure which is capable of increasing transistor density. Some embodiments of the present disclosure provides a method of stacking the passive device on the backside of the logic device to increase density. In the related art, the method of increasing density was largely directed towards arranging both the passive devices/components (e.g., resistor, capacitor, inductor, DRAM, RRAM, or the like) and the logic devices (e.g., integrated circuits) on the front side of a substrate”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the metal lines included in the backside structure Zillman in view of Cheng teaches and modified it such that they include a ground metal line as Liao teaches such that “the backside structure including a ground metal line” to necessarily ground the device and/or set a reference voltage of the device to ground.
Bharath teaches an inductive layer (comprising 103 and/or 104 and/or 107) comprising one or more vias comprising the magnetic material (102a, met under MPEP 2112.01 the materials are the same as disclosed) comprising CZT [103 fig. 2A Paragraph 0038 “In some embodiments, magnetic core block 103 comprises cobalt-zirconium-tantalum alloy (e.g., CZT).].
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Zillman in view of Cheng and Liao in further view of Bharath and select a known material such as CZT such that the “via comprises magnetic material” as selection of a known material for its known material properties and/or suitability for its intended use (in this case magnetism) is prima facie type obviousness [see MPEP 2144.07], and/or to increase the inductance/magnetism of the via.
Claim 17 Zillman in view of Cheng and Liao teaches as shown above the computing device of claim 16, further comprising:
a memory coupled to the board (DRAM fig. 8 Zillman).
Claim 18 Zillman in view of Cheng and Liao and Bharath teaches as shown above the computing device of claim 16, further comprising:
a communication chip coupled to the board (1006 fig. 8 Zillman).
Claim 19 Zillman in view of Cheng and Liao and Bharath teaches as shown above the computing device of claim 16, wherein the component is a packaged integrated circuit die (sufficiently disclosed paragraph 0049 Zillman “The processor 1004 includes an integrated circuit die packaged within the processor 1004” in view of Cheng as shown above it includes the component).
Claim 20 as shown above Zillman in view of Cheng and Liao and Bharath teaches the computing device of claim 16, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (in view of Cheng the processor 1004 and/or the communication ship 1006 of Zillman includes the component).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893