DETAILED ACTION
The Office Action is sent in response to Applicant’s Communication received on 08/24/2022 and 11/23/2022 for application number 17/894,873. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/declaration, IDS, and Claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Remark
Examiner notes that Fig.1 item 102 OP1, show “{qOP1, rOP2}” while the specification on paragraph 24 states “The integer portion of OP1 is qOP1, and the fractional portion of OP1 when interpreted as an integer is rOP1”. This may be inconsistent with what the applicant want to show.
Specification
The abstract of the disclosure is objected to because the abstract exceeds 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
Claim Objections
Claims 1 and 12 objected to because of the following informalities:
In claim 1, ll.14. in the approximation circuit, "
β
, as fixed point value” should read as “
β
, as a fixed point value” (emphasis added).
In claim 12, p.18, ll.6. in the approximation circuit, "
β
, as fixed point value” should read as “
β
, as a fixed point value” (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 (and 12), states the following limitation wherein a summing circuit is configured to “add[ing]…
q
x
+
r
x
/
n
+
q
β
+
r
β
/
n
in response to
s
x
=
s
y
, and subtract[ing]
q
x
+
r
x
/
n
-
q
β
-
r
β
/
n
in response to
s
x
≠
s
y
"
. However, the “subtract" operation would only imply subtraction, the following equation includes addition. This makes it unclear if “subtract” means to subtract (
q
x
+
r
x
/
n
-
q
β
-
r
β
/
n
) from another variable or some other form of subtract.
The remaining claims effectively depends on either claim 1 or 12, and are rejected for the reasons given above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, claims 1-11 recite an adder and, therefore, are all directed to a machine. Claims 12-20 recite a method and, therefore, are a process. All claims therefore fall into one of the four statutory categories at step 1.
Under the Alice Framework Step 2A prong 1, claim 1 recites
An adder for fractional logarithmic number system (FLNS) format operands, comprising:
A compare-and-swap circuit configured to input first and second FLNS operands represented by fixed point values and provide a greater one of the first and second operands as a operand x, and provide a lesser or equal to of the first and second operands as operand y, wherein
s
x
and
s
y
are sign bits of x and y, respectively,
q
x
a
n
d
q
y
are integer portions of x and y, respectively, fraction potions of x and y that as integers have bales
r
x
a
n
d
r
y
,
respectively,
x
=
s
x
*
2
q
x
+
r
x
n
,
y
=
s
y
*
2
q
y
+
r
y
n
,
n
=
2
w
r
,
w
r
is a bit-width of
r
x
a
n
d
r
y
, and the compare and swap circuit is configured to provide
s
x
as a sign bit,
s
z
of a sum
z
=
x
1
+
y
x
f
o
r
x
≠
0
;
A subtraction circuit configured to subtract
(
q
y
+
r
x
/
n
)
-
(
q
x
+
r
x
/
n
)
and output
q
a
a
n
d
r
a
, wherein
a
=
y
/
x
;
An approximation circuit configured to provide an approximation of
1
+
a
to a nearest FLNS value,
β
, as fixed point value having an integer portion
q
β
and a fraction portion that as an integer has a value
r
β
; and
A summing circuit configured to add
q
x
+
r
x
/
n
+
q
β
+
r
β
/
n
in response to
s
x
=
s
y
, and subtract
q
x
+
r
x
/
n
-
q
β
-
r
β
/
n
in response to
s
x
≠
s
y
, to provide the sum as a fixed point value having an integer portion
q
z
and a fraction portion that as an integer has a value
r
z
;
The above underlined limitations are related to multiplication using addition under the logarithmic number system which amounts to mathematical calculations and relationships that falls within the “mathematical Concepts” grouping of abstract ideas. (see specification paragraphs 16-17 for data format, 21-23 for approximated
β
, 24-26 for the initial steps, 27-48 for the approximation equations, operations, and mappings, and 49-53 for the overall process). Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “A compare-and-swap circuit configured to input first and second FLNS operands represented by fixed point values”, “A subtraction circuit configured to…”, “An approximation circuit configured to..”, and “A summing circuit configured to…”. However, the additional elements of “A compare-and-swap circuit configured to … and provide…”, “A subtraction circuit configured to…”, “An approximation circuit configured to..”, and “A summing circuit configured to…” are recited at a high-level of generality (i.e., as a generic computer component for processing the data for the math; and as a generic computer components for applying the math operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “A compare-and-swap circuit configured to input first and second FLNS operands represented by fixed point values…” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “A compare-and-swap circuit configured to … and provide…”, “A subtraction circuit configured to…”, “An approximation circuit configured to..”, and “A summing circuit configured to…” are recited at a high-level of generality (i.e., as a generic computer component for processing the data for the math; and as a generic computer components for applying the math operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “A compare-and-swap circuit configured to input first and second FLNS operands represented by fixed point values…” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 2-11 recite further steps and details to multiplication using addition under the logarithmic number system which amounts to mathematical calculations and relationships and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
Claim 2 is merely directed to the approximation circuit providing data with respect to the abstract idea. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 3 is merely directed to the approximation circuit applying the mathematical operations and relationships that map the input to an output based on mathematical conditions. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 4 is merely directed to the approximation circuit applying the mathematical operations and relationships that map the input to an output based on mathematical conditions. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 5 is merely directed to the approximation circuit components applying the mathematical operations and relationships that map the input to an output. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional element: “a look-up table that implements the third mapping”. However, the additional element of “a look-up table that implements the third mapping” is recited at a high-level of generality (i.e., as a generic computer component for mapping the data according to the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a look-up table that implements the third mapping” is recited at a high-level of generality (i.e., as a generic computer component for mapping the data according to the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 6 is merely directed to the approximation circuit components applying the mathematical operations and relationships that map the input to an output. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “a first decision-tree circuit” and “a second decision-tree circuit”. However, the additional elements of “a first decision-tree circuit” and “a second decision-tree circuit” are recited at a high-level of generality (i.e., as a generic computer components for mapping the data according to the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first decision-tree circuit” and “a second decision-tree circuit” are recited at a high-level of generality (i.e., as a generic computer components for mapping the data according to the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 7 is merely directed to the approximation circuit applying the mathematical operations and relationships that map the input to an output based on mathematical conditions. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 8 is merely directed to the approximation circuit applying the mathematical operations and relationships that map the input to an output based on mathematical conditions. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 9 is merely directed to the summing circuit components converting the data in response to the math. Examiner notes that in view of Gottschalk v. Benson, 409 U.S. 63, 70, 175 USPQ 673, 676 (1972), the conversion of binary-coded-decimal (BCD) numerals into pure binary numbers is directed to “Mathematical Concepts” of abstract ideas. As such, conversion from one data format to another is directed to abstract ideas. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “a twos-complement converter circuit”, “a selector circuit” and “an adder circuit”. However, the additional elements of “a twos-complement converter circuit”, “a selector circuit” and “an adder circuit” are recited at a high-level of generality (i.e., as a generic computer components for converting the data according to the math; and as a generic computer component for addition) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a twos-complement converter circuit”, “a selector circuit” and “an adder circuit” are recited at a high-level of generality (i.e., as a generic computer components for converting the data according to the math; and as a generic computer component for addition) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 10 is merely directed to the approximation circuit components applying the mathematical operations and relationships that map the input to an output based on mathematical conditions. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “a first decision-tree circuit” and “a second decision-tree circuit”. However, the additional elements of “a first decision-tree circuit” and “a second decision-tree circuit” are recited at a high-level of generality (i.e., as a generic computer components for mapping the data according to the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first decision-tree circuit” and “a second decision-tree circuit” are recited at a high-level of generality (i.e., as a generic computer components for mapping the data according to the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 11 is merely directed to the approximation circuit components applying the mathematical operations and relationships that map the input to an output based on mathematical conditions. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional element: “a look-up table that implements the third mapping”. However, the additional element of “a look-up table that implements the third mapping” is recited at a high-level of generality (i.e., as a generic computer component for mapping the data according to the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a look-up table that implements the third mapping” is recited at a high-level of generality (i.e., as a generic computer component for mapping the data according to the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claims 12-20 are directed to claims 1-7 and 10-11, respectively. A mere change in statutory class is obvious. As such, claims 12-20 are rejected for the reasons given above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 9 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Parhami (NPL: “Computing with Logarithmic Number System Arithmetic: Implementation Methods and Performance Benefits”, from IDS filed 08/24/2022), and in view of Stouraitis et al (NPL: Analysis of Logarithmic Number System Processors”), hereinafter Stouraitis, and further in view of Dally et al. (US 2021/0056446 A1, from IDS filed 08/24/2022), hereinafter Dally, and further in view of Electrical Technology (NPL: “Binary adder & Subtractor – Construction, Types & Applications”), hereinafter ET.
Regarding claim 1, Parhami discloses:
For LNS operands wherein
s
x
and
s
y
are sign bits of x and y, respectively,
L
x
a
n
d
L
y
are magnitude portions of x and y, respectively [“a number x is representing by its sign
S
x
and the binary logarithm of its magnitude
L
x
” Sec.2.1]
the ALU is configured to provide
s
x
as a sign bit,
s
z
of a sum
z
=
x
1
+
y
x
f
o
r
x
≠
0
;
[“
S
z
=
S
x
” “
L
z
=
log
2
|
x
1
±
y
x
|
=
log
2
x
+
log
2
1
±
y
/
x
=
log
2
x
+
log
2
1
±
2
L
y
-
L
x
” Equations 7 and 8, Sec.2.2]
A subtraction circuit [Fig.3, first ALU] configured to subtract
L
y
-
L
x
and output
L
a
, wherein
a
=
y
/
x
[“Let d = Ly – Lx” Sec.2.2];
An approximation circuit [Fig.2 and 3,
Φ
±
tables] configured to provide an approximation of
1
+
a
to a nearest FLNS value,
β
, [“
Φ
±
=
log
2
|
1
±
2
d
|
“ sec.2.2, which is also
Φ
±
=
log
2
|
1
±
2
d
|
=
log
2
|
1
±
y
/
x
|
=
log
2
|
1
+
a
|
]; and
A summing circuit [Fig.3, second ALU] configured to compute
x
+
Φ
+
v
in response to
s
x
=
s
y
, and compute
x
+
Φ
-
v
in response to
s
x
≠
s
y
, to provide the sum as a fixed point value
L
z
[“For addition/subtraction, the left adder-subtractor computes Ly – Lx, the lookup table provides the value of log2|1 ± 2(Ly – Lx)|, and the right adder-subtractor perform the addition of Equation (8)” sec.2.2; see fig.2 for the values of the tables and see eq.1];
However, Parhami does not explicitly disclose:
A compare-and-swap circuit configured to input first and second FLNS operands represented by fixed point values and provide a greater one of the first and second operands as a operand x, and provide a lesser or equal to of the first and second operands as operand y, wherein
q
x
a
n
d
q
y
are integer portions of x and y, respectively , fraction potions of x and y that as integers have values
r
x
a
n
d
r
y
,
respectively,
x
=
s
x
*
2
q
x
+
r
x
n
,
y
=
s
y
*
2
q
y
+
r
y
n
,
n
=
2
w
r
,
w
r
is a bit-width of
r
x
a
n
d
r
y
, A subtraction circuit configured to subtract
(
q
y
+
r
x
/
n
)
-
(
q
x
+
r
x
/
n
)
and output
q
a
a
n
d
r
a
, wherein
a
=
y
/
x
; An approximation circuit configured to provide an approximation of
1
+
a
to a nearest FLNS value,
β
, as fixed point value having an integer portion
q
β
and a fraction portion that as an integer has a value
r
β
; and A summing circuit configured to add
q
x
+
r
x
/
n
+
q
β
+
r
β
/
n
in response to
s
x
=
s
y
, and subtract
q
x
+
r
x
/
n
-
q
β
-
r
β
/
n
in response to
s
x
≠
s
y
, to provide the sum as a fixed point value having an integer portion
q
z
and a fraction portion that as an integer has a value
r
z
;
In the analogous art of Logarithmic Arithmetic processors, Stouraitis teaches
A compare-and-swap circuit [Fig.1, Comparator] configured to input first and second FLNS operands represented by fixed point values and provide a greater one of the first and second operands as a operand x, and provide a lesser or equal to of the first and second operands as operand y, and configured to provide
s
x
as a sign bit,
s
z
of a sum. [Addition, “
c
=
x
+
Φ
v
a
n
d
S
c
=
S
x
w
i
t
h
v
=
x
-
y
a
n
d
Φ
v
=
log
r
(
1
+
r
-
v
)
” p.520]
Stouraitis also teaches a subtraction circuit; An approximation circuit; and a summing circuit [figure 1, first ALU,
Φ
a
n
d
Ψ
tables, and second ALU after the comparator];
It would have been obvious to one of ordinary skill in the art, to notice that the figure 2 of Parhami requires that the magnitude of
L
x
be greater than or equal to
L
y
in order to compute equation 3, which would require an implementation to ensure that the inputs are correctly inputted. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Parhami and Stouraitis before him before the effective filing date of the claimed invention to incorporate the comparator as taught by Stouraitis into the adder as disclosed by Parhami, to allow for the proper inputs for Parhami [fig.3] using the comparator designed for logarithmic number system to ensure compatibility with the inputs as required for the mathematical operations for logarithmic number systems with minimal time [Stouraitis: Sec.II].
However, Parhami and Stouraitis does not explicitly disclose: wherein
q
x
a
n
d
q
y
are integer portions of x and y, respectively , fraction potions of x and y that as integers have values
r
x
a
n
d
r
y
,
respectively,
x
=
s
x
*
2
q
x
+
r
x
n
,
y
=
s
y
*
2
q
y
+
r
y
n
,
n
=
2
w
r
,
w
r
is a bit-width of
r
x
a
n
d
r
y
, A subtraction circuit configured to subtract
(
q
y
+
r
x
/
n
)
-
(
q
x
+
r
x
/
n
)
and output
q
a
a
n
d
r
a
, wherein
a
=
y
/
x
; An approximation circuit configured to provide an approximation of
1
+
a
to a nearest FLNS value,
β
, as fixed point value having an integer portion
q
β
and a fraction portion that as an integer has a value
r
β
; and A summing circuit configured to add
q
x
+
r
x
/
n
+
q
β
+
r
β
/
n
in response to
s
x
=
s
y
, and subtract
q
x
+
r
x
/
n
-
q
β
-
r
β
/
n
in response to
s
x
≠
s
y
, to provide the sum as a fixed point value having an integer portion
q
z
and a fraction portion that as an integer has a value
r
z
;
In the analogous art of Logarithmic number systems, Dally teaches that logarithmic numbers have the format
v
=
s
2
(
e
q
+
e
r
n
)
[“when the base of the logarithmic format is restricted to be of the form
b
=
2
1
/
n
for an integer n… the exponent can be decomposed or separated into an integer quotient component
e
q
and a remainder component
e
r
… When n is a power of 2, the least-significant bits of the exponent are the remainder component and the most-significant bits of the exponent are the quotient component...” par.35]
It would have been obvious to one of ordinary skill in the art, having the teachings of Parhami, Stouraitis, and Dally before him before the effective filing date of the claimed invention to modify the LNS format of Parhami, to use the equivalent LNS format of Dally to simplify addition operations by using the quotient and remainder components [Dally: par.33-38].
However, Parhami, Stouraitis, and Dally does not explicitly disclose a summing circuit configured to add
q
x
+
r
x
/
n
+
q
β
+
r
β
/
n
in response to
s
x
=
s
y
, and subtract
q
x
+
r
x
/
n
-
q
β
-
r
β
/
n
in response to
s
x
≠
s
y
, to provide the sum as a fixed point value having an integer portion
q
z
and a fraction portion that as an integer has a value
r
z
;
In the analogous art of binary adder and subtractor architectures, ET discloses a two’s complement combined adder/subtractor circuit [p.12].
Parhami discloses A summing circuit [Fig.3, second ALU] configured to compute
x
+
Φ
+
v
in response to
s
x
=
s
y
, and compute
x
+
Φ
-
v
in response to
s
x
≠
s
y
, to provide the sum as a fixed point value
L
z
[“For addition/subtraction, the left adder-subtractor computes Ly – Lx, the lookup table provides the value of log2|1 ± 2(Ly – Lx)|, and the right adder-subtractor perform the addition of Equation (8)” sec.2.2; see fig.2 for the values of the tables and see eq.1];
It would have been obvious to one of ordinary skill in the art, having the teachings of Parhami, Stouraitis, Dally, and ET before him before the effective filing date of the claimed invention to modify the second output of Parhami, to use the combined circuit of ET to reduce the need for a separate subtractor circuit and handle negative numbers using only an adder [Dally: par.33-38].
Regarding claim 2, Parhami, Stouraitis, Dally, and ET disclose the invention substantially as claimed. See the discussion of claim 1 above.
Parhami discloses wherein the approximation circuit is configured to provide
β
to the FLNS value nearest to
(
1
+
2
d
)
in response to
s
x
=
s
y
, and the FLNS value nearest to
1
-
2
d
in response to
s
z
≠
s
y
. [
Φ
±
represents addition and subtraction respectively, which corresponds to the operations done on the two inputs]
Stouraitis also discloses providing
β
to the FLNS value nearest to
(
1
+
2
d
)
in response to
s
x
=
s
y
, and the FLNS value nearest to
1
-
2
d
in response to
s
z
≠
s
y
. [Equations 2.iii and 2.iv]
However, Parhami and Stouraitis does not explicitly disclose providing
(
1
±
2
q
a
+
r
a
n
)
In the analogous art of Logarithmic number systems, Dally teaches that logarithmic numbers have the format
v
=
s
2
(
e
q
+
e
r
n
)
[“when the base of the logarithmic format is restricted to be of the form
b
=
2
1
/
n
for an integer n… the exponent can be decomposed or separated into an integer quotient component
e
q
and a remainder component
e
r
… When n is a power of 2, the least-significant bits of the exponent are the remainder component and the most-significant bits of the exponent are the quotient component...” par.35]
It would have been obvious to one of ordinary skill in the art, having the teachings of Parhami, Stouraitis, and Dally before him before the effective filing date of the claimed invention to modify the LNS format of Parhami, to use the equivalent LNS format of Dally to simplify addition operations by using the quotient and remainder components [Dally: par.33-38].
Regarding claim 9, Parhami, Stouraitis, Dally, and ET disclose the invention substantially as claimed. See the discussion of claim 1 above.
Parhami discloses wherein the approximation circuit is configured to provide
β
to the FLNS value nearest to
(
1
+
2
d
)
in response to
s
x
=
s
y
, and the FLNS value nearest to
1
-
2
d
in response to
s
z
≠
s
y
. [
Φ
±
represents addition and subtraction respectively, which corresponds to the operations done on the two inputs]
And an adder circuit [Fig.3, second ALU].
However, Parhami, Parhami, and Dally does not explicitly disclose the additional limitations.
ET discloses:
A two-complement converter circuit configured to convert the binary to a negative twos-complement value [figure on p.12, B2 to inverter]
A selector circuit configured to select as an addend the binary in response to addition and select as the addend the negative twos-complement value in response to subtraction [figure on p.12, Mux, selecting between normal binary and twos-complement based on addition or subtraction]; and
An adder circuit configured to add X to the addend [figure on p.12, adds A and B].
It would have been obvious to one of ordinary skill in the art, having the teachings of Parhami, Stouraitis, Dally, and ET before him before the effective filing date of the claimed invention to modify the second output of Parhami, to use the combined circuit of ET to reduce the need for a separate subtractor circuit and handle negative numbers using only an adder [Dally: par.33-38]. The combination of Parhami, Stouraitis, Dally, and ET discloses the additional limitations of the claim.
Claims 12-13 are directed to claims 1-2. A mere change in statutory class if obvious. Claims 12-13 is rejected for the reasons given above.
Allowable Subject Matter
Claims 3-8, 10-11 and 14-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcoming all related rejections under 35 U.S.C. 101 and/or 35 U.S.C. 112.
Regarding claim 3, the prior art above alone or in combination with any other reference fails to disclose or provide motivation for at least the following limitation in combination with the rest of the claim limitations: “…map each range… in response to
s
x
≠
s
y
a
n
d
x
≥
2
|
y
|
”. As the prior art discloses mappings based on
s
x
≠
s
y
and not explicitly on
x
≥
2
|
y
|
.
Regarding claims 4-6, the claims effectively depends on claim 3 and would be allowable for the reasons given above and overcoming all related rejections.
Regarding claim 7, the prior art above alone or in combination with any other reference fails to disclose or provide motivation for at least the following limitation in combination with the rest of the claim limitations: “…map each range… in response to
s
x
≠
s
y
a
n
d
q
a
≠
0
”. As the prior art discloses mappings based on
s
x
≠
s
y
and not explicitly on
q
a
≠
0
.
Regarding claim 8, the claim effectively depends on claim 7 and would be allowable for the reasons given above and overcoming all related rejections.
Regarding claim 10, the prior art above alone or in combination with any other reference fails to disclose or provide motivation for at least the following limitation in combination with the rest of the claim limitations: “…map each range… in response to
s
x
≠
s
y
a
n
d
q
a
≠
0
…”. As the prior art discloses mappings based on
s
x
≠
s
y
and not explicitly on
q
a
≠
0
.
Regarding claim 11, the claim effectively depends on claim 10 and would be allowable for the reasons given above and overcoming all related rejections.
Claims 14-20 are directed to claims 3-7 and 10-11, respectively, and would be allowable for the reasons given above and overcoming all related rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Alam et al. (NPL: “Log Precision Logarithmic Number Systems: Beyond Base-2”) discloses the tables based on sign and operations. See eq.10 and 11.
Arnold et al. (NPL: “Bipartite Implementation of the Residue Logarithmic Number System”) discloses relation of operations to outputs. See sec.2.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182